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<EDKSYSTEM EDKVERSION="14.7" EDWVERSION="1.2" TIMESTAMP="Fri Apr 21 16:15:41 2017">
<SYSTEMINFO ARCH="zynq" DEVICE="xc7z010" PACKAGE="clg400" PART="xc7z010clg400-1" SOURCE="/local/ucart/MicroCART_17-18/quad/sytem/system.xmp" SPEEDGRADE="-1"/>
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<EXTERNALPORTS>
<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="0" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="53" LSB="0" MHS_INDEX="2" MSB="53" NAME="processing_system7_0_MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="3" NAME="processing_system7_0_PS_SRSTB_pin" SIGNAME="processing_system7_0_PS_SRSTB">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="4" NAME="processing_system7_0_PS_CLK_pin" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="5" NAME="processing_system7_0_PS_PORB_pin" SIGNAME="processing_system7_0_PS_PORB">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="6" NAME="processing_system7_0_DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="7" NAME="processing_system7_0_DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="8" NAME="processing_system7_0_DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="9" NAME="processing_system7_0_DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="10" NAME="processing_system7_0_DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="11" NAME="processing_system7_0_DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" MHS_INDEX="12" NAME="processing_system7_0_DDR_WEB_pin" SIGNAME="processing_system7_0_DDR_WEB">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="13" MSB="2" NAME="processing_system7_0_DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="14" LSB="0" MHS_INDEX="14" MSB="14" NAME="processing_system7_0_DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="15" NAME="processing_system7_0_DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="16" NAME="processing_system7_0_DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="17" MSB="31" NAME="processing_system7_0_DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="18" MSB="3" NAME="processing_system7_0_DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="19" MSB="3" NAME="processing_system7_0_DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="20" MSB="3" NAME="processing_system7_0_DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="21" NAME="processing_system7_0_DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="22" NAME="processing_system7_0_DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="23" NAME="pwm_recorder_0_pwm_in_master_pin" SIGNAME="pwm_recorder_0_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_0" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="24" NAME="pwm_recorder_1_pwm_in_master_pin" SIGNAME="pwm_recorder_1_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_1" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="25" NAME="pwm_recorder_2_pwm_in_master_pin" SIGNAME="pwm_recorder_2_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_2" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="26" NAME="pwm_recorder_3_pwm_in_master_pin" SIGNAME="pwm_recorder_3_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_3" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="27" NAME="pwm_recorder_4_pwm_in_master_pin" SIGNAME="pwm_recorder_4_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_4" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="28" NAME="pwm_recorder_5_pwm_in_master_pin" SIGNAME="pwm_recorder_5_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_5" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="29" MSB="3" NAME="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="btns_4bits_tri_io" PORT="GPIO_IO_I"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="30" NAME="processing_system7_0_UART0_TX_pin" SIGNAME="processing_system7_0_UART0_TX">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="31" NAME="processing_system7_0_UART0_RX_pin" SIGNAME="processing_system7_0_UART0_RX">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" MHS_INDEX="32" NAME="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_0" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="33" NAME="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_1" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="34" NAME="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_2" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="35" NAME="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_3" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<MODULES>
<MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="IP" MODTYPE="clock_generator">
<DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_generator.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="7z010">
<DESCRIPTION>Device</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="clg400">
<DESCRIPTION>Package</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1">
<DESCRIPTION>Speed Grade</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Varaible Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION> Varaible Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION> Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION> Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Clock Deskew</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Variable Phase Shift</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>C_EXT_RESET_HIGH</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="CLK_N"/>
<CONNECTION INSTANCE="External Ports" PORT="CLK_P"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="24" NAME="LOCKED" SIGNAME="clock_generator_0_LOCKED_0">
<CONNECTIONS>
<CONNECTION INSTANCE="reset_0" PORT="Dcm_locked"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES/>
</MODULE>
<MODULE HWVERSION="3.00.a" INSTANCE="reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
<DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sys_reset.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx">
<DESCRIPTION>Device Subfamily</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
<DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
<DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
<DESCRIPTION>External Reset Active High </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
<DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="zynq">
<DESCRIPTION>Device Family</DESCRIPTION>
</PARAMETER>
</PARAMETERS>
<PORTS>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="clock_generator_0_LOCKED_0">
<CONNECTIONS>
<CONNECTION INSTANCE="clock_generator_0" PORT="LOCKED"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
<PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
<PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
<PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
<PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
<PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
<PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
<PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
</IOINTERFACES>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_0" IPTYPE="PERIPHERAL" MHS_INDEX="2" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76ea0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76eaffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_0_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_0_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_1" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="axi_interconnect">
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Base Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Number of Slave Slots </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="12">
<DESCRIPTION>Number of Master Slots </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>AXI ID Widgth </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>AXI Address Widgth </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
<DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
<DESCRIPTION>Master AXI Data Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>AXI Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002">
<DESCRIPTION>Master AXI Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000042800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079400000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079420000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079440000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079460000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e20000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e40000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e60000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e80000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076ea0000">
<DESCRIPTION>Master AXI Base Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004280ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007940ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007942ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007944ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007946ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e2ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e4ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e6ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e8ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076eaffff">
<DESCRIPTION>Master AXI High Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000001">
<DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e100">
<DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
<DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Propagate USER Signals</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>WUSER Signal Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>RUSER Signal Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>BUSER Signal Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
<DESCRIPTION>AXI Connectivity</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Secure</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI W Register </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI R Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI B Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI AW Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI AR Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI W Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI R Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI B Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Interconnect Architecture</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Generate Interrupts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2">
<DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
<DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
<DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
<DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Simulation debug</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
</PARAMETER>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET0_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_1_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="3" MSB="11" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARESETN"/>