<EDKSYSTEM EDKVERSION="14.7" EDWVERSION="1.2" TIMESTAMP="Fri Apr 21 16:15:41 2017">
<SYSTEMINFO ARCH="zynq" DEVICE="xc7z010" PACKAGE="clg400" PART="xc7z010clg400-1" SOURCE="/local/ucart/MicroCART_17-18/quad/sytem/system.xmp" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="0" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="53" LSB="0" MHS_INDEX="2" MSB="53" NAME="processing_system7_0_MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="3" NAME="processing_system7_0_PS_SRSTB_pin" SIGNAME="processing_system7_0_PS_SRSTB">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="4" NAME="processing_system7_0_PS_CLK_pin" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="5" NAME="processing_system7_0_PS_PORB_pin" SIGNAME="processing_system7_0_PS_PORB">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="6" NAME="processing_system7_0_DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="7" NAME="processing_system7_0_DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="8" NAME="processing_system7_0_DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="9" NAME="processing_system7_0_DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="10" NAME="processing_system7_0_DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="11" NAME="processing_system7_0_DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" MHS_INDEX="12" NAME="processing_system7_0_DDR_WEB_pin" SIGNAME="processing_system7_0_DDR_WEB">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="13" MSB="2" NAME="processing_system7_0_DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="14" LSB="0" MHS_INDEX="14" MSB="14" NAME="processing_system7_0_DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="15" NAME="processing_system7_0_DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="16" NAME="processing_system7_0_DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="17" MSB="31" NAME="processing_system7_0_DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="18" MSB="3" NAME="processing_system7_0_DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="19" MSB="3" NAME="processing_system7_0_DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="20" MSB="3" NAME="processing_system7_0_DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="21" NAME="processing_system7_0_DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
<CONNECTIONS/>
</PORT>
<PORT DIR="IO" MHS_INDEX="22" NAME="processing_system7_0_DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="23" NAME="pwm_recorder_0_pwm_in_master_pin" SIGNAME="pwm_recorder_0_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_0" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="24" NAME="pwm_recorder_1_pwm_in_master_pin" SIGNAME="pwm_recorder_1_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_1" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="25" NAME="pwm_recorder_2_pwm_in_master_pin" SIGNAME="pwm_recorder_2_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_2" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="26" NAME="pwm_recorder_3_pwm_in_master_pin" SIGNAME="pwm_recorder_3_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_3" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="27" NAME="pwm_recorder_4_pwm_in_master_pin" SIGNAME="pwm_recorder_4_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_4" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MHS_INDEX="28" NAME="pwm_recorder_5_pwm_in_master_pin" SIGNAME="pwm_recorder_5_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_recorder_5" PORT="pwm_in_master"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="29" MSB="3" NAME="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="btns_4bits_tri_io" PORT="GPIO_IO_I"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="30" NAME="processing_system7_0_UART0_TX_pin" SIGNAME="processing_system7_0_UART0_TX">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MHS_INDEX="31" NAME="processing_system7_0_UART0_RX_pin" SIGNAME="processing_system7_0_UART0_RX">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" MHS_INDEX="32" NAME="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_0" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="33" NAME="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_1" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="34" NAME="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_2" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MHS_INDEX="35" NAME="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="pwm_signal_out_wkillswitch_3" PORT="pwm_out_sm"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<MODULES>
<MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="IP" MODTYPE="clock_generator">
<DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_generator.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="7z010">
<DESCRIPTION>Device</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="clg400">
<DESCRIPTION>Package</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1">
<DESCRIPTION>Speed Grade</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Varaible Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION> Varaible Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION> Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION> Variable Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Clock Deskew</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0">
<DESCRIPTION>Required Phase</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Required Group</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
<DESCRIPTION>Buffered</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
<DESCRIPTION>Variable Phase Shift</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>C_EXT_RESET_HIGH</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
<DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="CLK_N"/>
<CONNECTION INSTANCE="External Ports" PORT="CLK_P"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="24" NAME="LOCKED" SIGNAME="clock_generator_0_LOCKED_0">
<CONNECTIONS>
<CONNECTION INSTANCE="reset_0" PORT="Dcm_locked"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES/>
</MODULE>
<MODULE HWVERSION="3.00.a" INSTANCE="reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
<DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sys_reset.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx">
<DESCRIPTION>Device Subfamily</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
<DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
<DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
<DESCRIPTION>External Reset Active High </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
<DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
<DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="zynq">
<DESCRIPTION>Device Family</DESCRIPTION>
</PARAMETER>
</PARAMETERS>
<PORTS>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="clock_generator_0_LOCKED_0">
<CONNECTIONS>
<CONNECTION INSTANCE="clock_generator_0" PORT="LOCKED"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
<PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
<PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
<PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
<PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
<PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
<PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
<PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
</IOINTERFACES>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_0" IPTYPE="PERIPHERAL" MHS_INDEX="2" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76ea0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76eaffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_0_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_0_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_1" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="axi_interconnect">
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Base Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Number of Slave Slots </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="12">
<DESCRIPTION>Number of Master Slots </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>AXI ID Widgth </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>AXI Address Widgth </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
<DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
<DESCRIPTION>Master AXI Data Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>AXI Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002">
<DESCRIPTION>Master AXI Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000042800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079400000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079420000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079440000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079460000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e20000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e40000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e60000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e80000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076ea0000">
<DESCRIPTION>Master AXI Base Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004280ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007940ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007942ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007944ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007946ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e2ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e4ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e6ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e8ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076eaffff">
<DESCRIPTION>Master AXI High Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000001">
<DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e100">
<DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
<DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Propagate USER Signals</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>WUSER Signal Width </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>RUSER Signal Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>BUSER Signal Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
<DESCRIPTION>AXI Connectivity</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
<DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Secure</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
<DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
<DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI W Register </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI R Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Slave AXI B Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI AW Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI AR Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI W Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI R Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
<DESCRIPTION>Master AXI B Register</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Interconnect Architecture</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Generate Interrupts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2">
<DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
<DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
<DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
<DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Simulation debug</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
</PARAMETER>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET0_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_1_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="3" MSB="11" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARESETN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_1_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi_interconnect_1_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_interconnect_1_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WID" DIR="I" MPD_INDEX="18" NAME="S_AXI_WID" SIGNAME="axi_interconnect_1_S_WID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WLAST" DIR="I" MPD_INDEX="21" NAME="S_AXI_WLAST" SIGNAME="axi_interconnect_1_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WUSER" DIR="I" MPD_INDEX="22" NAME="S_AXI_WUSER" SIGNAME="axi_interconnect_1_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_WREADY" DIR="O" MPD_INDEX="24" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_BID" DIR="O" MPD_INDEX="25" NAME="S_AXI_BID" SIGNAME="axi_interconnect_1_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_BUSER" DIR="O" MPD_INDEX="27" NAME="S_AXI_BUSER" SIGNAME="axi_interconnect_1_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_BVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_BREADY" DIR="I" MPD_INDEX="29" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARID" DIR="I" MPD_INDEX="30" NAME="S_AXI_ARID" SIGNAME="axi_interconnect_1_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="32" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARUSER" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARUSER" SIGNAME="axi_interconnect_1_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARVALID" DIR="I" MPD_INDEX="40" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_ARREADY" DIR="O" MPD_INDEX="41" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RID" DIR="O" MPD_INDEX="42" NAME="S_AXI_RID" SIGNAME="axi_interconnect_1_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="43" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RLAST" DIR="O" MPD_INDEX="45" NAME="S_AXI_RLAST" SIGNAME="axi_interconnect_1_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RUSER" DIR="O" MPD_INDEX="46" NAME="S_AXI_RUSER" SIGNAME="axi_interconnect_1_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RVALID" DIR="O" MPD_INDEX="47" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_S_RREADY" DIR="I" MPD_INDEX="48" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="49" MSB="11" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi_interconnect_1_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="50" MSB="11" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="51" MSB="383" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="52" MSB="95" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="53" MSB="35" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="54" MSB="23" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="55" MSB="23" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="56" MSB="47" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="57" MSB="35" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="58" MSB="47" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="59" MSB="47" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="60" MSB="11" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="61" MSB="11" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="62" MSB="11" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="63" MSB="11" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi_interconnect_1_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="64" MSB="383" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="65" MSB="47" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="66" MSB="11" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi_interconnect_1_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="67" MSB="11" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="68" MSB="11" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="69" MSB="11" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="70" MSB="11" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi_interconnect_1_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="71" MSB="23" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="72" MSB="11" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="73" MSB="11" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="74" MSB="11" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="75" MSB="11" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="76" MSB="383" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="77" MSB="95" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="78" MSB="35" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="79" MSB="23" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="80" MSB="23" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="81" MSB="47" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="82" MSB="35" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="83" MSB="47" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="84" MSB="47" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="85" MSB="11" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="86" MSB="11" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="87" MSB="11" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="88" MSB="11" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi_interconnect_1_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="89" MSB="383" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="90" MSB="23" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="91" MSB="11" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi_interconnect_1_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="92" MSB="11" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="93" MSB="11" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="94" MSB="11" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="142" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="144" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="145" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="147" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="148" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="149" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="151" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="153" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="154" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="155" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="156" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="158" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="160" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="162" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="163" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="164" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="165" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="167" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="169" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="171" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="172" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="173" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="174" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="175" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="176" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="178" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="180" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="181" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="182" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="183" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="184" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="185" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="187" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="189" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="190" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="192" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="193" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="194" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="196" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="198" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="199" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="200" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="201" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="202" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="203" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_1" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e80000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e8ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_1_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_1_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1994915840" BASENAME="C_BASEADDR" BASEVALUE="0x76e80000" HIGHDECIMAL="1994981375" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e8ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_2" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e60000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e6ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_2_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_2_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1994784768" BASENAME="C_BASEADDR" BASEVALUE="0x76e60000" HIGHDECIMAL="1994850303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e6ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_3" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e40000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e4ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_3_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_3_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1994653696" BASENAME="C_BASEADDR" BASEVALUE="0x76e40000" HIGHDECIMAL="1994719231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e4ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_4" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e20000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e2ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_4_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_4_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1994522624" BASENAME="C_BASEADDR" BASEVALUE="0x76e20000" HIGHDECIMAL="1994588159" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e2ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_5" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
<DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e00000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e0ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_5_pwm_in_master">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_5_pwm_in_master_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1994391552" BASENAME="C_BASEADDR" BASEVALUE="0x76e00000" HIGHDECIMAL="1994457087" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e0ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.01.b" INSTANCE="btns_4bits_tri_io" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
<DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v1_01_b;d=ds744_axi_gpio.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Device Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="BTNs_4Bits_TRI_IO"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
<DESCRIPTION>AXI Base Address </DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
<DESCRIPTION>AXI High Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9">
<DESCRIPTION>AXI Address Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>AXI Data Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
<DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
<DESCRIPTION>GPIO Data Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="8" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
<DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
<DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
<DESCRIPTION>Channel 1 3-state Default Value </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Enable Channel 2 </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
<DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
<DESCRIPTION>Channel 2 3-state Default Value </DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
<DESCRIPTION>AXI Protocol</DESCRIPTION>
</PARAMETER>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="1" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="2" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[8:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="12" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[8:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
<DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
<DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
<PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
<PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
<PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_0" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
<DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79460000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7946ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="2034630656" BASENAME="C_BASEADDR" BASEVALUE="0x79460000" HIGHDECIMAL="2034696191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7946ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
<DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79440000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7944ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="2034499584" BASENAME="C_BASEADDR" BASEVALUE="0x79440000" HIGHDECIMAL="2034565119" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7944ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_2" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
<DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79420000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7942ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="2034368512" BASENAME="C_BASEADDR" BASEVALUE="0x79420000" HIGHDECIMAL="2034434047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7942ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_3" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
<DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79400000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7940ffff"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
<CONNECTIONS>
<CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="2034237440" BASENAME="C_BASEADDR" BASEVALUE="0x79400000" HIGHDECIMAL="2034302975" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7940ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.03.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
<DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v1_03_a;d=axi_timer_ds764.pdf" TYPE="IP"/>
</DOCUMENTATION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
<DESCRIPTION>AXI Protocol</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
<DESCRIPTION>Device Family</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_timer_0">
<DESCRIPTION>C_INSTANCE</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
<DESCRIPTION>Count Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
<DESCRIPTION>Only One Timer is present</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
<DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
<DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
<DESCRIPTION>GEN0 Active Level</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
<DESCRIPTION>GEN1 Active Level</DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="9" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x42800000">
<DESCRIPTION>AXI Base Address </DESCRIPTION>
</PARAMETER>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="10" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4280ffff">
<DESCRIPTION>AXI High Address</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="11" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="5">
<DESCRIPTION>AXI Address Width</DESCRIPTION>
</PARAMETER>
<PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
<DESCRIPTION>AXI Data Width</DESCRIPTION>
</PARAMETER>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
<DESCRIPTION>Capture Trig 0</DESCRIPTION>
</PORT>
<PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
<DESCRIPTION>Capture Trig 1</DESCRIPTION>
</PORT>
<PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
<DESCRIPTION>Generate Out 0</DESCRIPTION>
</PORT>
<PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
<DESCRIPTION>Generate Out 1</DESCRIPTION>
</PORT>
<PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
<DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
</PORT>
<PORT DIR="O" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="9" MSB="4" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[4:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="19" MSB="4" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[4:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1115684864" BASENAME="C_BASEADDR" BASEVALUE="0x42800000" HIGHDECIMAL="1115750399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4280ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.00.a" INSTANCE="ps7_axi_interconnect_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="15" MODCLASS="BUS" MODTYPE="ps7_axi_interconnect">
<DESCRIPTION TYPE="SHORT">PS7 AXI Interconnect</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 AXI4 Memory-Mapped Interconnect</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS/>
<PORTS>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="BREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="114" NAME="M_AXI_GP0_BREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="112" NAME="M_AXI_GP0_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="113" NAME="M_AXI_GP0_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="WVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="117" NAME="M_AXI_GP0_WVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="4" MPD_INDEX="119" MSB="31" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="RREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="115" NAME="M_AXI_GP0_RREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="6" MPD_INDEX="123" MSB="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="141" NAME="M_AXI_GP0_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="8" MPD_INDEX="118" MSB="31" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="WID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="9" MPD_INDEX="120" MSB="31" NAME="M_AXI_GP0_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="10" MPD_INDEX="124" MSB="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="11" MPD_INDEX="121" MSB="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="12" MPD_INDEX="122" MSB="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="13" MPD_INDEX="125" MSB="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="14" MPD_INDEX="126" MSB="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="15" MPD_INDEX="127" MSB="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="16" MPD_INDEX="128" MSB="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="17" MPD_INDEX="129" MSB="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="BID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="18" MPD_INDEX="146" MSB="31" NAME="M_AXI_GP0_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="19" MPD_INDEX="130" MSB="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="WDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="20" MPD_INDEX="131" MSB="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="21" MPD_INDEX="132" MSB="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="22" MPD_INDEX="137" MSB="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="23" MPD_INDEX="133" MSB="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="24" MPD_INDEX="134" MSB="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="25" MPD_INDEX="135" MSB="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="WREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="145" NAME="M_AXI_GP0_WREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="27" MPD_INDEX="136" MSB="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="WSTRB" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="28" MPD_INDEX="138" MSB="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WSTRB" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="139" NAME="M_AXI_GP0_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="140" NAME="M_AXI_GP0_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="BVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="142" NAME="M_AXI_GP0_BVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="RLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="143" NAME="M_AXI_GP0_RLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="RVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="144" NAME="M_AXI_GP0_RVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="RID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="34" MPD_INDEX="147" MSB="31" NAME="M_AXI_GP0_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="BRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="35" MPD_INDEX="148" MSB="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="RRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="36" MPD_INDEX="149" MSB="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="RDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="37" MPD_INDEX="150" MSB="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP0" DEF_SIGNAME="WLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="116" NAME="M_AXI_GP0_WLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="BREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="154" NAME="M_AXI_GP1_BREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="40" MPD_INDEX="174" MSB="3" NAME="M_AXI_GP1_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="41" MPD_INDEX="158" MSB="31" NAME="M_AXI_GP1_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="WID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="42" MPD_INDEX="160" MSB="31" NAME="M_AXI_GP1_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="43" MPD_INDEX="164" MSB="1" NAME="M_AXI_GP1_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="44" MPD_INDEX="161" MSB="1" NAME="M_AXI_GP1_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="45" MPD_INDEX="162" MSB="1" NAME="M_AXI_GP1_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="46" MPD_INDEX="165" MSB="1" NAME="M_AXI_GP1_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="47" MPD_INDEX="166" MSB="2" NAME="M_AXI_GP1_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="48" MPD_INDEX="167" MSB="2" NAME="M_AXI_GP1_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="49" MPD_INDEX="168" MSB="2" NAME="M_AXI_GP1_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="50" MPD_INDEX="169" MSB="31" NAME="M_AXI_GP1_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="BID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="51" MPD_INDEX="186" MSB="31" NAME="M_AXI_GP1_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="52" MPD_INDEX="170" MSB="31" NAME="M_AXI_GP1_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="WDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="53" MPD_INDEX="171" MSB="31" NAME="M_AXI_GP1_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="54" MPD_INDEX="172" MSB="3" NAME="M_AXI_GP1_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="55" MPD_INDEX="173" MSB="3" NAME="M_AXI_GP1_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="RLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="56" MPD_INDEX="183" NAME="M_AXI_GP1_RLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="57" MPD_INDEX="177" MSB="3" NAME="M_AXI_GP1_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="58" MPD_INDEX="181" NAME="M_AXI_GP1_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="59" MPD_INDEX="175" MSB="3" NAME="M_AXI_GP1_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="60" MPD_INDEX="176" MSB="3" NAME="M_AXI_GP1_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="WSTRB" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="61" MPD_INDEX="178" MSB="3" NAME="M_AXI_GP1_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WSTRB" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="WREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="62" MPD_INDEX="185" NAME="M_AXI_GP1_WREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="63" MPD_INDEX="179" NAME="M_AXI_GP1_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="64" MPD_INDEX="180" NAME="M_AXI_GP1_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="BVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="65" MPD_INDEX="182" NAME="M_AXI_GP1_BVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="RVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="66" MPD_INDEX="184" NAME="M_AXI_GP1_RVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="RDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="67" MPD_INDEX="190" MSB="31" NAME="M_AXI_GP1_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="RID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="68" MPD_INDEX="187" MSB="31" NAME="M_AXI_GP1_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="BRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="69" MPD_INDEX="188" MSB="1" NAME="M_AXI_GP1_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="RRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="70" MPD_INDEX="189" MSB="1" NAME="M_AXI_GP1_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="RREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="71" MPD_INDEX="155" NAME="M_AXI_GP1_RREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="WVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="72" MPD_INDEX="157" NAME="M_AXI_GP1_WVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="73" MPD_INDEX="152" NAME="M_AXI_GP1_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="74" MPD_INDEX="159" MSB="31" NAME="M_AXI_GP1_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWID" VECFORMULA="[32-1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="WLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="75" MPD_INDEX="156" NAME="M_AXI_GP1_WLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="76" MPD_INDEX="163" MSB="2" NAME="M_AXI_GP1_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="77" MPD_INDEX="153" NAME="M_AXI_GP1_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="78" MPD_INDEX="237" NAME="S_AXI_GP1_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="79" MPD_INDEX="318" NAME="S_AXI_HP0_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="80" MPD_INDEX="365" NAME="S_AXI_HP1_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="81" MPD_INDEX="411" NAME="S_AXI_HP2_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="82" MPD_INDEX="457" NAME="S_AXI_HP3_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="83" MPD_INDEX="277" NAME="S_AXI_ACP_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="84" MPD_INDEX="355" MSB="5" NAME="S_AXI_HP0_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="85" MPD_INDEX="356" MSB="5" NAME="S_AXI_HP0_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="86" MPD_INDEX="357" MSB="63" NAME="S_AXI_HP0_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="87" MPD_INDEX="358" MSB="7" NAME="S_AXI_HP0_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WSTRB" VECFORMULA="[((64/8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="88" MPD_INDEX="409" NAME="S_AXI_HP2_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="89" MPD_INDEX="407" NAME="S_AXI_HP2_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="90" MPD_INDEX="364" NAME="S_AXI_HP1_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="91" MPD_INDEX="367" MSB="1" NAME="S_AXI_HP1_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="92" MPD_INDEX="377" NAME="S_AXI_HP1_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="93" MPD_INDEX="380" NAME="S_AXI_HP1_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="94" MPD_INDEX="368" MSB="5" NAME="S_AXI_HP1_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="95" MPD_INDEX="381" NAME="S_AXI_HP1_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="96" MPD_INDEX="369" MSB="5" NAME="S_AXI_HP1_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="97" MPD_INDEX="370" MSB="63" NAME="S_AXI_HP1_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="98" MPD_INDEX="375" NAME="S_AXI_HP1_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="99" MPD_INDEX="376" NAME="S_AXI_HP1_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="100" MPD_INDEX="378" NAME="S_AXI_HP1_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="101" MPD_INDEX="383" NAME="S_AXI_HP1_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="102" MPD_INDEX="386" MSB="2" NAME="S_AXI_HP1_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="103" MPD_INDEX="384" MSB="1" NAME="S_AXI_HP1_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="104" MPD_INDEX="406" NAME="S_AXI_HP2_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="105" MPD_INDEX="385" MSB="1" NAME="S_AXI_HP1_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="106" MPD_INDEX="387" MSB="1" NAME="S_AXI_HP1_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="107" MPD_INDEX="388" MSB="1" NAME="S_AXI_HP1_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="108" MPD_INDEX="389" MSB="2" NAME="S_AXI_HP1_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="109" MPD_INDEX="390" MSB="2" NAME="S_AXI_HP1_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="110" MPD_INDEX="391" MSB="2" NAME="S_AXI_HP1_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="111" MPD_INDEX="392" MSB="31" NAME="S_AXI_HP1_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="112" MPD_INDEX="393" MSB="31" NAME="S_AXI_HP1_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="113" MPD_INDEX="394" MSB="3" NAME="S_AXI_HP1_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="114" MPD_INDEX="395" MSB="3" NAME="S_AXI_HP1_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="115" MPD_INDEX="396" MSB="3" NAME="S_AXI_HP1_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="116" MPD_INDEX="287" NAME="S_AXI_ACP_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="117" MPD_INDEX="281" MSB="2" NAME="S_AXI_ACP_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="118" MPD_INDEX="282" MSB="63" NAME="S_AXI_ACP_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RDATA" VECFORMULA="[63:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="119" MPD_INDEX="283" NAME="S_AXI_ACP_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="120" MPD_INDEX="284" NAME="S_AXI_ACP_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="121" MPD_INDEX="286" NAME="S_AXI_ACP_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="122" MPD_INDEX="289" NAME="S_AXI_ACP_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="123" MPD_INDEX="302" MSB="3" NAME="S_AXI_ACP_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="124" MPD_INDEX="290" MSB="2" NAME="S_AXI_ACP_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="125" MPD_INDEX="298" MSB="3" NAME="S_AXI_ACP_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="126" MPD_INDEX="291" MSB="2" NAME="S_AXI_ACP_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="127" MPD_INDEX="292" MSB="2" NAME="S_AXI_ACP_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="128" MPD_INDEX="293" MSB="2" NAME="S_AXI_ACP_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="129" MPD_INDEX="294" MSB="2" NAME="S_AXI_ACP_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="130" MPD_INDEX="295" MSB="31" NAME="S_AXI_ACP_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="131" MPD_INDEX="296" MSB="31" NAME="S_AXI_ACP_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="132" MPD_INDEX="297" MSB="3" NAME="S_AXI_ACP_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="133" MPD_INDEX="299" MSB="3" NAME="S_AXI_ACP_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="134" MPD_INDEX="303" MSB="1" NAME="S_AXI_ACP_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="135" MPD_INDEX="300" MSB="3" NAME="S_AXI_ACP_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="136" MPD_INDEX="306" MSB="1" NAME="S_AXI_ACP_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="137" MPD_INDEX="301" MSB="3" NAME="S_AXI_ACP_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="138" MPD_INDEX="305" MSB="2" NAME="S_AXI_ACP_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="139" MPD_INDEX="304" MSB="1" NAME="S_AXI_ACP_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="140" MPD_INDEX="307" MSB="1" NAME="S_AXI_ACP_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="141" MPD_INDEX="308" MSB="2" NAME="S_AXI_ACP_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARUSER" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="4" LSB="0" MHS_INDEX="142" MPD_INDEX="309" MSB="4" NAME="S_AXI_ACP_ARUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARUSER" VECFORMULA="[4:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWUSER" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="4" LSB="0" MHS_INDEX="143" MPD_INDEX="310" MSB="4" NAME="S_AXI_ACP_AWUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWUSER" VECFORMULA="[4:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="144" MPD_INDEX="311" MSB="63" NAME="S_AXI_ACP_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WDATA" VECFORMULA="[63:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="145" MPD_INDEX="312" MSB="7" NAME="S_AXI_ACP_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WSTRB" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="146" MPD_INDEX="195" NAME="S_AXI_GP0_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="147" MPD_INDEX="194" NAME="S_AXI_GP0_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="148" MPD_INDEX="242" MSB="2" NAME="S_AXI_GP1_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="149" MPD_INDEX="243" NAME="S_AXI_GP1_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="150" MPD_INDEX="244" NAME="S_AXI_GP1_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="151" MPD_INDEX="246" NAME="S_AXI_GP1_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="152" MPD_INDEX="249" NAME="S_AXI_GP1_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="153" MPD_INDEX="252" MSB="2" NAME="S_AXI_GP1_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="154" MPD_INDEX="250" MSB="1" NAME="S_AXI_GP1_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="155" MPD_INDEX="315" NAME="S_AXI_HP0_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="156" MPD_INDEX="251" MSB="1" NAME="S_AXI_GP1_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="157" MPD_INDEX="253" MSB="1" NAME="S_AXI_GP1_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="158" MPD_INDEX="254" MSB="1" NAME="S_AXI_GP1_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="159" MPD_INDEX="255" MSB="2" NAME="S_AXI_GP1_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="160" MPD_INDEX="256" MSB="2" NAME="S_AXI_GP1_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="161" MPD_INDEX="257" MSB="2" NAME="S_AXI_GP1_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="162" MPD_INDEX="258" MSB="31" NAME="S_AXI_GP1_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="163" MPD_INDEX="259" MSB="31" NAME="S_AXI_GP1_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="164" MPD_INDEX="260" MSB="31" NAME="S_AXI_GP1_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="165" MPD_INDEX="261" MSB="3" NAME="S_AXI_GP1_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="166" MPD_INDEX="263" MSB="3" NAME="S_AXI_GP1_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="167" MPD_INDEX="262" MSB="3" NAME="S_AXI_GP1_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="168" MPD_INDEX="266" MSB="3" NAME="S_AXI_GP1_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="169" MPD_INDEX="314" NAME="S_AXI_HP0_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="170" MPD_INDEX="264" MSB="3" NAME="S_AXI_GP1_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="171" MPD_INDEX="265" MSB="3" NAME="S_AXI_GP1_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="172" MPD_INDEX="267" MSB="3" NAME="S_AXI_GP1_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WSTRB" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="173" MPD_INDEX="268" MSB="31" NAME="S_AXI_GP1_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="174" MPD_INDEX="269" MSB="31" NAME="S_AXI_GP1_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="175" MPD_INDEX="270" MSB="31" NAME="S_AXI_GP1_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="176" MPD_INDEX="363" NAME="S_AXI_HP1_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="177" MPD_INDEX="361" NAME="S_AXI_HP1_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="178" MPD_INDEX="317" NAME="S_AXI_HP0_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="179" MPD_INDEX="316" NAME="S_AXI_HP0_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="180" MPD_INDEX="223" MSB="3" NAME="S_AXI_GP0_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="181" MPD_INDEX="213" MSB="1" NAME="S_AXI_GP0_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="182" MPD_INDEX="214" MSB="1" NAME="S_AXI_GP0_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="183" MPD_INDEX="215" MSB="2" NAME="S_AXI_GP0_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="184" MPD_INDEX="216" MSB="2" NAME="S_AXI_GP0_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="185" MPD_INDEX="217" MSB="2" NAME="S_AXI_GP0_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="186" MPD_INDEX="218" MSB="31" NAME="S_AXI_GP0_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="187" MPD_INDEX="219" MSB="31" NAME="S_AXI_GP0_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="188" MPD_INDEX="220" MSB="31" NAME="S_AXI_GP0_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="189" MPD_INDEX="221" MSB="3" NAME="S_AXI_GP0_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="190" MPD_INDEX="234" NAME="S_AXI_GP1_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="191" MPD_INDEX="222" MSB="3" NAME="S_AXI_GP0_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="192" MPD_INDEX="226" MSB="3" NAME="S_AXI_GP0_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="193" MPD_INDEX="232" NAME="S_AXI_GP1_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="194" MPD_INDEX="224" MSB="3" NAME="S_AXI_GP0_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="195" MPD_INDEX="227" MSB="3" NAME="S_AXI_GP0_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WSTRB" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="196" MPD_INDEX="228" MSB="31" NAME="S_AXI_GP0_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="197" MPD_INDEX="229" MSB="31" NAME="S_AXI_GP0_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="198" MPD_INDEX="230" MSB="31" NAME="S_AXI_GP0_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="199" MPD_INDEX="320" MSB="1" NAME="S_AXI_HP0_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="200" MPD_INDEX="319" NAME="S_AXI_HP0_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="201" MPD_INDEX="236" NAME="S_AXI_GP1_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="202" MPD_INDEX="239" MSB="1" NAME="S_AXI_GP1_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="203" MPD_INDEX="245" NAME="S_AXI_GP1_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="204" MPD_INDEX="247" NAME="S_AXI_GP1_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="205" MPD_INDEX="240" MSB="31" NAME="S_AXI_GP1_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="206" MPD_INDEX="248" NAME="S_AXI_GP1_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="207" MPD_INDEX="241" MSB="2" NAME="S_AXI_GP1_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="208" MPD_INDEX="193" NAME="S_AXI_GP0_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="209" MPD_INDEX="198" MSB="1" NAME="S_AXI_GP0_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="210" MPD_INDEX="192" NAME="S_AXI_GP0_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="211" MPD_INDEX="238" MSB="1" NAME="S_AXI_GP1_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="212" MPD_INDEX="235" NAME="S_AXI_GP1_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="213" MPD_INDEX="196" NAME="S_AXI_GP0_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="214" MPD_INDEX="199" MSB="1" NAME="S_AXI_GP0_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="215" MPD_INDEX="205" NAME="S_AXI_GP0_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="216" MPD_INDEX="207" NAME="S_AXI_GP0_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="217" MPD_INDEX="200" MSB="31" NAME="S_AXI_GP0_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RDATA" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="218" MPD_INDEX="208" NAME="S_AXI_GP0_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="219" MPD_INDEX="201" MSB="31" NAME="S_AXI_GP0_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="220" MPD_INDEX="202" MSB="31" NAME="S_AXI_GP0_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RID" VECFORMULA="[(32- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="221" MPD_INDEX="203" NAME="S_AXI_GP0_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="222" MPD_INDEX="204" NAME="S_AXI_GP0_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="223" MPD_INDEX="206" NAME="S_AXI_GP0_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="224" MPD_INDEX="209" NAME="S_AXI_GP0_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="225" MPD_INDEX="212" MSB="2" NAME="S_AXI_GP0_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="226" MPD_INDEX="225" MSB="3" NAME="S_AXI_GP0_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="227" MPD_INDEX="233" NAME="S_AXI_GP1_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="228" MPD_INDEX="210" MSB="1" NAME="S_AXI_GP0_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="229" MPD_INDEX="211" MSB="1" NAME="S_AXI_GP0_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="230" MPD_INDEX="435" MSB="2" NAME="S_AXI_HP2_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="231" MPD_INDEX="436" MSB="2" NAME="S_AXI_HP2_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="232" MPD_INDEX="437" MSB="2" NAME="S_AXI_HP2_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="233" MPD_INDEX="438" MSB="31" NAME="S_AXI_HP2_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="234" MPD_INDEX="439" MSB="31" NAME="S_AXI_HP2_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="235" MPD_INDEX="440" MSB="3" NAME="S_AXI_HP2_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="236" MPD_INDEX="441" MSB="3" NAME="S_AXI_HP2_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="237" MPD_INDEX="442" MSB="3" NAME="S_AXI_HP2_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="238" MPD_INDEX="443" MSB="3" NAME="S_AXI_HP2_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="239" MPD_INDEX="458" MSB="1" NAME="S_AXI_HP3_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="240" MPD_INDEX="445" MSB="3" NAME="S_AXI_HP2_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="241" MPD_INDEX="444" MSB="3" NAME="S_AXI_HP2_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="242" MPD_INDEX="446" MSB="5" NAME="S_AXI_HP2_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="243" MPD_INDEX="454" NAME="S_AXI_HP3_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="244" MPD_INDEX="447" MSB="5" NAME="S_AXI_HP2_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="245" MPD_INDEX="448" MSB="5" NAME="S_AXI_HP2_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="246" MPD_INDEX="449" MSB="63" NAME="S_AXI_HP2_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="247" MPD_INDEX="450" MSB="7" NAME="S_AXI_HP2_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WSTRB" VECFORMULA="[((64/8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="248" MPD_INDEX="275" NAME="S_AXI_ACP_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="249" MPD_INDEX="273" NAME="S_AXI_ACP_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="250" MPD_INDEX="456" NAME="S_AXI_HP3_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="251" MPD_INDEX="459" MSB="1" NAME="S_AXI_HP3_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="252" MPD_INDEX="469" NAME="S_AXI_HP3_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="253" MPD_INDEX="472" NAME="S_AXI_HP3_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="254" MPD_INDEX="460" MSB="5" NAME="S_AXI_HP3_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="255" MPD_INDEX="473" NAME="S_AXI_HP3_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="256" MPD_INDEX="461" MSB="5" NAME="S_AXI_HP3_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="257" MPD_INDEX="462" MSB="63" NAME="S_AXI_HP3_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="258" MPD_INDEX="467" NAME="S_AXI_HP3_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="259" MPD_INDEX="468" NAME="S_AXI_HP3_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="260" MPD_INDEX="470" NAME="S_AXI_HP3_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="261" MPD_INDEX="475" NAME="S_AXI_HP3_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="262" MPD_INDEX="478" MSB="2" NAME="S_AXI_HP3_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="263" MPD_INDEX="476" MSB="1" NAME="S_AXI_HP3_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="264" MPD_INDEX="272" NAME="S_AXI_ACP_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="265" MPD_INDEX="477" MSB="1" NAME="S_AXI_HP3_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="266" MPD_INDEX="479" MSB="1" NAME="S_AXI_HP3_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="267" MPD_INDEX="480" MSB="1" NAME="S_AXI_HP3_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="268" MPD_INDEX="481" MSB="2" NAME="S_AXI_HP3_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="269" MPD_INDEX="482" MSB="2" NAME="S_AXI_HP3_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="270" MPD_INDEX="483" MSB="2" NAME="S_AXI_HP3_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="271" MPD_INDEX="484" MSB="31" NAME="S_AXI_HP3_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="272" MPD_INDEX="485" MSB="31" NAME="S_AXI_HP3_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="273" MPD_INDEX="486" MSB="3" NAME="S_AXI_HP3_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="274" MPD_INDEX="487" MSB="3" NAME="S_AXI_HP3_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="275" MPD_INDEX="488" MSB="3" NAME="S_AXI_HP3_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="276" MPD_INDEX="489" MSB="3" NAME="S_AXI_HP3_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="277" MPD_INDEX="278" MSB="1" NAME="S_AXI_ACP_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="278" MPD_INDEX="491" MSB="3" NAME="S_AXI_HP3_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="279" MPD_INDEX="490" MSB="3" NAME="S_AXI_HP3_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="280" MPD_INDEX="492" MSB="5" NAME="S_AXI_HP3_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="281" MPD_INDEX="274" NAME="S_AXI_ACP_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="282" MPD_INDEX="493" MSB="5" NAME="S_AXI_HP3_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="283" MPD_INDEX="494" MSB="5" NAME="S_AXI_HP3_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="284" MPD_INDEX="495" MSB="63" NAME="S_AXI_HP3_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="285" MPD_INDEX="496" MSB="7" NAME="S_AXI_HP3_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WSTRB" VECFORMULA="[((64/8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="286" MPD_INDEX="276" NAME="S_AXI_ACP_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="287" MPD_INDEX="288" NAME="S_AXI_ACP_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="288" MPD_INDEX="279" MSB="1" NAME="S_AXI_ACP_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="289" MPD_INDEX="280" MSB="2" NAME="S_AXI_ACP_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BID" VECFORMULA="[(3- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="290" MPD_INDEX="285" NAME="S_AXI_ACP_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="291" MPD_INDEX="397" MSB="3" NAME="S_AXI_HP1_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="292" MPD_INDEX="412" MSB="1" NAME="S_AXI_HP2_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="293" MPD_INDEX="399" MSB="3" NAME="S_AXI_HP1_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="294" MPD_INDEX="398" MSB="3" NAME="S_AXI_HP1_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="295" MPD_INDEX="400" MSB="5" NAME="S_AXI_HP1_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="296" MPD_INDEX="408" NAME="S_AXI_HP2_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="297" MPD_INDEX="401" MSB="5" NAME="S_AXI_HP1_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="298" MPD_INDEX="402" MSB="5" NAME="S_AXI_HP1_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="299" MPD_INDEX="403" MSB="63" NAME="S_AXI_HP1_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WDATA" VECFORMULA="[(64 - 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="300" MPD_INDEX="404" MSB="7" NAME="S_AXI_HP1_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WSTRB" VECFORMULA="[((64/8)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="301" MPD_INDEX="455" NAME="S_AXI_HP3_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="302" MPD_INDEX="453" NAME="S_AXI_HP3_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="303" MPD_INDEX="410" NAME="S_AXI_HP2_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="304" MPD_INDEX="413" MSB="1" NAME="S_AXI_HP2_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="305" MPD_INDEX="423" NAME="S_AXI_HP2_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="306" MPD_INDEX="426" NAME="S_AXI_HP2_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="307" MPD_INDEX="414" MSB="5" NAME="S_AXI_HP2_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="308" MPD_INDEX="427" NAME="S_AXI_HP2_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="309" MPD_INDEX="415" MSB="5" NAME="S_AXI_HP2_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RID" VECFORMULA="[(6- 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="310" MPD_INDEX="416" MSB="63" NAME="S_AXI_HP2_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="311" MPD_INDEX="421" NAME="S_AXI_HP2_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="312" MPD_INDEX="422" NAME="S_AXI_HP2_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="313" MPD_INDEX="424" NAME="S_AXI_HP2_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="314" MPD_INDEX="429" NAME="S_AXI_HP2_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="315" MPD_INDEX="432" MSB="2" NAME="S_AXI_HP2_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="316" MPD_INDEX="430" MSB="1" NAME="S_AXI_HP2_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="317" MPD_INDEX="452" NAME="S_AXI_HP3_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="318" MPD_INDEX="431" MSB="1" NAME="S_AXI_HP2_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="319" MPD_INDEX="433" MSB="1" NAME="S_AXI_HP2_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="320" MPD_INDEX="434" MSB="1" NAME="S_AXI_HP2_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="321" MPD_INDEX="321" MSB="1" NAME="S_AXI_HP0_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="322" MPD_INDEX="331" NAME="S_AXI_HP0_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="323" MPD_INDEX="334" NAME="S_AXI_HP0_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="324" MPD_INDEX="322" MSB="5" NAME="S_AXI_HP0_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="325" MPD_INDEX="335" NAME="S_AXI_HP0_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WLAST">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="326" MPD_INDEX="323" MSB="5" NAME="S_AXI_HP0_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="327" MPD_INDEX="324" MSB="63" NAME="S_AXI_HP0_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RDATA" VECFORMULA="[(64- 1) :0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="328" MPD_INDEX="329" NAME="S_AXI_HP0_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ACLK">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="329" MPD_INDEX="330" NAME="S_AXI_HP0_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="330" MPD_INDEX="332" NAME="S_AXI_HP0_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="331" MPD_INDEX="337" NAME="S_AXI_HP0_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="332" MPD_INDEX="340" MSB="2" NAME="S_AXI_HP0_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="333" MPD_INDEX="338" MSB="1" NAME="S_AXI_HP0_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="334" MPD_INDEX="360" NAME="S_AXI_HP1_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARREADY">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="335" MPD_INDEX="339" MSB="1" NAME="S_AXI_HP0_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="336" MPD_INDEX="341" MSB="1" NAME="S_AXI_HP0_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="337" MPD_INDEX="342" MSB="1" NAME="S_AXI_HP0_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWLOCK" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="338" MPD_INDEX="343" MSB="2" NAME="S_AXI_HP0_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="339" MPD_INDEX="344" MSB="2" NAME="S_AXI_HP0_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="340" MPD_INDEX="345" MSB="2" NAME="S_AXI_HP0_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="341" MPD_INDEX="346" MSB="31" NAME="S_AXI_HP0_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="342" MPD_INDEX="347" MSB="31" NAME="S_AXI_HP0_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="343" MPD_INDEX="348" MSB="3" NAME="S_AXI_HP0_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="344" MPD_INDEX="349" MSB="3" NAME="S_AXI_HP0_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="345" MPD_INDEX="350" MSB="3" NAME="S_AXI_HP0_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="346" MPD_INDEX="351" MSB="3" NAME="S_AXI_HP0_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="347" MPD_INDEX="366" MSB="1" NAME="S_AXI_HP1_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="348" MPD_INDEX="353" MSB="3" NAME="S_AXI_HP0_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="349" MPD_INDEX="352" MSB="3" NAME="S_AXI_HP0_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWLEN" VECFORMULA="[3:0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="350" MPD_INDEX="354" MSB="5" NAME="S_AXI_HP0_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARID" VECFORMULA="[(6 - 1) : 0]">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_HP1" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="351" MPD_INDEX="362" NAME="S_AXI_HP1_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BVALID">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI_GP0" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="352" MPD_INDEX="197" NAME="S_AXI_GP0_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WREADY">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="353" MPD_INDEX="111" NAME="M_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="354" MPD_INDEX="336" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WRISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="355" MPD_INDEX="231" NAME="S_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="356" MPD_INDEX="191" NAME="S_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="357" MPD_INDEX="271" NAME="S_AXI_ACP_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="358" MPD_INDEX="313" NAME="S_AXI_HP0_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="359" MPD_INDEX="325" MSB="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="360" MPD_INDEX="326" MSB="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="361" MPD_INDEX="327" MSB="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RACOUNT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="362" MPD_INDEX="328" MSB="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WACOUNT" VECFORMULA="[5:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="363" MPD_INDEX="333" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RDISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="364" MPD_INDEX="359" NAME="S_AXI_HP1_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="365" MPD_INDEX="382" NAME="S_AXI_HP1_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WRISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="366" MPD_INDEX="371" MSB="7" NAME="S_AXI_HP1_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="367" MPD_INDEX="372" MSB="7" NAME="S_AXI_HP1_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="368" MPD_INDEX="373" MSB="2" NAME="S_AXI_HP1_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RACOUNT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="369" MPD_INDEX="374" MSB="5" NAME="S_AXI_HP1_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WACOUNT" VECFORMULA="[5:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="370" MPD_INDEX="379" NAME="S_AXI_HP1_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RDISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="371" MPD_INDEX="405" NAME="S_AXI_HP2_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="372" MPD_INDEX="428" NAME="S_AXI_HP2_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WRISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="373" MPD_INDEX="417" MSB="7" NAME="S_AXI_HP2_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="374" MPD_INDEX="418" MSB="7" NAME="S_AXI_HP2_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="375" MPD_INDEX="419" MSB="2" NAME="S_AXI_HP2_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RACOUNT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="376" MPD_INDEX="420" MSB="5" NAME="S_AXI_HP2_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WACOUNT" VECFORMULA="[5:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="377" MPD_INDEX="425" NAME="S_AXI_HP2_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RDISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="378" MPD_INDEX="451" NAME="S_AXI_HP3_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="379" MPD_INDEX="474" NAME="S_AXI_HP3_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WRISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="380" MPD_INDEX="463" MSB="7" NAME="S_AXI_HP3_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="381" MPD_INDEX="464" MSB="7" NAME="S_AXI_HP3_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WCOUNT" VECFORMULA="[7:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="382" MPD_INDEX="465" MSB="2" NAME="S_AXI_HP3_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RACOUNT" VECFORMULA="[2:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="383" MPD_INDEX="466" MSB="5" NAME="S_AXI_HP3_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WACOUNT" VECFORMULA="[5:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="384" MPD_INDEX="471" NAME="S_AXI_HP3_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RDISSUECAP1_EN">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="385" MPD_INDEX="151" NAME="M_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARESETN">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_ARESETN" VECFORMULA="[(2-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="aresetn"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARESETN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARESETN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_ACLK" VECFORMULA="[(2-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWID" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWADDR" VECFORMULA="[((2*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWADDR"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLEN" VECFORMULA="[((2*8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWLEN"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWLEN"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" VECFORMULA="[((2*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWSIZE"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWSIZE"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWBURST" VECFORMULA="[((2*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWBURST"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWBURST"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" VECFORMULA="[((2*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWLOCK"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWLOCK"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" VECFORMULA="[((2*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWCACHE"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWCACHE"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWPROT" VECFORMULA="[((2*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWPROT"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWPROT"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWQOS" VECFORMULA="[((2*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWQOS"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWQOS"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="15" MSB="1" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWUSER" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWVALID" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWVALID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWREADY" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWREADY"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WDATA" VECFORMULA="[((2*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WDATA"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WSTRB" VECFORMULA="[(((2*32)/8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WSTRB"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WLAST" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WLAST"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WLAST"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WUSER" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WVALID" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WVALID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WREADY" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WREADY"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BID" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BRESP" VECFORMULA="[((2*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BRESP"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BUSER" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BVALID" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BVALID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BREADY" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BREADY"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARID" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARADDR" VECFORMULA="[((2*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARADDR"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLEN" VECFORMULA="[((2*8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARLEN"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" VECFORMULA="[((2*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARSIZE"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARBURST" VECFORMULA="[((2*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARBURST"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" VECFORMULA="[((2*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARLOCK"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" VECFORMULA="[((2*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARCACHE"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARPROT" VECFORMULA="[((2*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARPROT"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARQOS" VECFORMULA="[((2*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARQOS"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARQOS"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARUSER" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARVALID" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARVALID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARREADY" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARREADY"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RID" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RDATA" VECFORMULA="[((2*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RDATA"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RRESP" VECFORMULA="[((2*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RRESP"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RLAST" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RLAST"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RUSER" VECFORMULA="[((2*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RVALID" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RVALID"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RREADY" VECFORMULA="[(2-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RREADY"/>
<CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ACLK" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_M_ACLK" VECFORMULA="[(1-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="ps7_axi_interconnect_0_M_AWID" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[((1*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awaddr"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_awaddr"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_AWADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWLEN" VECFORMULA="[((1*8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWLEN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" VECFORMULA="[((1*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWSIZE"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWBURST" VECFORMULA="[((1*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWBURST"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWLOCK" VECFORMULA="[((1*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWLOCK"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" VECFORMULA="[((1*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWCACHE"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWPROT" VECFORMULA="[((1*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWPROT"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWREGION" VECFORMULA="[((1*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWQOS" VECFORMULA="[((1*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWUSER" DIR="O" MPD_INDEX="59" NAME="M_AXI_AWUSER" SIGNAME="ps7_axi_interconnect_0_M_AWUSER" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_awvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_AWVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_awready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_AWREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_awready"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="ps7_axi_interconnect_0_M_WID" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[((1*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wdata"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_wdata"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[(((1*32)/8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wstrb"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WSTRB"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="ps7_axi_interconnect_0_M_WLAST" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WLAST"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="ps7_axi_interconnect_0_M_WUSER" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_wvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_wready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_wready"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="ps7_axi_interconnect_0_M_BID" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[((1*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bresp"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_bresp"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_BRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="ps7_axi_interconnect_0_M_BUSER" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_bvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_BVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_bready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_BREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_bready"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="ps7_axi_interconnect_0_M_ARID" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[((1*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_araddr"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_araddr"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARADDR"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARLEN" VECFORMULA="[((1*8)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARLEN"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" VECFORMULA="[((1*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARSIZE"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARBURST" VECFORMULA="[((1*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARBURST"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARLOCK" VECFORMULA="[((1*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARLOCK"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" VECFORMULA="[((1*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARCACHE"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARPROT" VECFORMULA="[((1*3)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARPROT"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARREGION" VECFORMULA="[((1*4)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARQOS" VECFORMULA="[((1*4)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARUSER" DIR="O" MPD_INDEX="84" NAME="M_AXI_ARUSER" SIGNAME="ps7_axi_interconnect_0_M_ARUSER" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_arvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_arready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_arready"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="ps7_axi_interconnect_0_M_RID" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[((1*32)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rdata"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rdata"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RDATA"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[((1*2)-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rresp"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rresp"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RRESP"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="ps7_axi_interconnect_0_M_RLAST" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RLAST"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="ps7_axi_interconnect_0_M_RUSER" VECFORMULA="[((1*1)-1):0]">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rvalid"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RVALID"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rready"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RREADY"/>
<CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rready"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="110" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="M_AXI_GP0" TYPE="MASTER">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_BREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WDATA"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_ARREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RLAST"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WLAST"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="M_AXI_GP1" TYPE="MASTER">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_BREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WDATA"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_WREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_ARREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWVALID"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_GP1" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_AWREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="5" NAME="S_AXI_HP0" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARID"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="6" NAME="S_AXI_HP1" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARQOS"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BVALID"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="7" NAME="S_AXI_HP2" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_ARREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWLOCK"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="8" NAME="S_AXI_HP3" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_ARREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="9" NAME="S_AXI_ACP" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_WREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARUSER"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWUSER"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWVALID"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_GP0" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWQOS"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_RREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARLOCK"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_WREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_uart_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="ps7_uart">
<DESCRIPTION TYPE="SHORT">PS7 UART</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0000FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_UART_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_MODEM" TYPE="STRING" VALUE="0"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="20" NAME="RX" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="uart0_0" MPD_INDEX="21" NAME="TX" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data Out</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="22" NAME="CTSN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="uart0_0" MPD_INDEX="23" NAME="RTSN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data Out</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="24" NAME="DSRN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="25" NAME="DCDN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="26" NAME="RIN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="uart0_0" MPD_INDEX="27" NAME="DTRN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data Out</DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="uart0_0" TYPE="XIL_UART_V1_hide">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="RX"/>
<PORTMAP DIR="O" PHYSICAL="TX"/>
<PORTMAP DIR="I" PHYSICAL="CTSN"/>
<PORTMAP DIR="O" PHYSICAL="RTSN"/>
<PORTMAP DIR="I" PHYSICAL="DSRN"/>
<PORTMAP DIR="I" PHYSICAL="DCDN"/>
<PORTMAP DIR="I" PHYSICAL="RIN"/>
<PORTMAP DIR="O" PHYSICAL="DTRN"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0000FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="ps7_uart">
<DESCRIPTION TYPE="SHORT">PS7 UART</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0001000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0001FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_UART_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_MODEM" TYPE="STRING" VALUE="0"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[31:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="20" NAME="RX" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="uart0_0" MPD_INDEX="21" NAME="TX" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data Out</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="22" NAME="CTSN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="uart0_0" MPD_INDEX="23" NAME="RTSN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data Out</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="24" NAME="DSRN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="25" NAME="DCDN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="uart0_0" MPD_INDEX="26" NAME="RIN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data In</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="uart0_0" MPD_INDEX="27" NAME="DTRN" SIGNAME="__NOC__">
<DESCRIPTION>Serial Data Out</DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="uart0_0" TYPE="XIL_UART_V1_hide">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="RX"/>
<PORTMAP DIR="O" PHYSICAL="TX"/>
<PORTMAP DIR="I" PHYSICAL="CTSN"/>
<PORTMAP DIR="O" PHYSICAL="RTSN"/>
<PORTMAP DIR="I" PHYSICAL="DSRN"/>
<PORTMAP DIR="I" PHYSICAL="DCDN"/>
<PORTMAP DIR="I" PHYSICAL="RIN"/>
<PORTMAP DIR="O" PHYSICAL="DTRN"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0001FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_i2c_0" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="PERIPHERAL" MODTYPE="ps7_i2c">
<DESCRIPTION TYPE="SHORT">PS7 i2c Interface</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 Interface to Philips I2C bus v2.1</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0004000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0004FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_I2C_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_INTERRUPT" TYPE="STRING" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_I2C_RESET" VALUE="-1"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" IOS="i2c_0" MPD_INDEX="19" NAME="Sda_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="20" NAME="Sda_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="21" NAME="Sda_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="i2c_0" MPD_INDEX="22" NAME="Scl_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="23" NAME="Scl_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="24" NAME="Scl_T" SIGNAME="__NOC__"/>
<PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="25" NAME="Sda" SIGNAME="__NOC__" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
<DESCRIPTION></DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="26" NAME="Scl" SIGNAME="__NOC__" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
<DESCRIPTION></DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="i2c_0" TYPE="XIL_AXI_IIC_V1">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="Sda_I"/>
<PORTMAP DIR="O" PHYSICAL="Sda_O"/>
<PORTMAP DIR="O" PHYSICAL="Sda_T"/>
<PORTMAP DIR="I" PHYSICAL="Scl_I"/>
<PORTMAP DIR="O" PHYSICAL="Scl_O"/>
<PORTMAP DIR="O" PHYSICAL="Scl_T"/>
<PORTMAP DIR="IO" PHYSICAL="Sda"/>
<PORTMAP DIR="IO" PHYSICAL="Scl"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0004FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_0" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
<DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8008000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8008FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160782336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8008000" HIGHDECIMAL="4160786431" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8008FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_1" IPTYPE="PERIPHERAL" MHS_INDEX="20" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
<DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8009000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8009FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160786432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8009000" HIGHDECIMAL="4160790527" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8009FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_2" IPTYPE="PERIPHERAL" MHS_INDEX="21" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
<DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800A000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800AFFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160790528" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800A000" HIGHDECIMAL="4160794623" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800AFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_3" IPTYPE="PERIPHERAL" MHS_INDEX="22" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
<DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800B000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800BFFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160794624" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800B000" HIGHDECIMAL="4160798719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800BFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_i2c_1" IPTYPE="PERIPHERAL" MHS_INDEX="23" MODCLASS="PERIPHERAL" MODTYPE="ps7_i2c">
<DESCRIPTION TYPE="SHORT">PS7 i2c Interface</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 Interface to Philips I2C bus v2.1</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0005000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0005FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_I2C_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_INTERRUPT" TYPE="STRING" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_I2C_RESET" VALUE="-1"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" IOS="i2c_0" MPD_INDEX="19" NAME="Sda_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="20" NAME="Sda_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="21" NAME="Sda_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="i2c_0" MPD_INDEX="22" NAME="Scl_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="23" NAME="Scl_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="i2c_0" MPD_INDEX="24" NAME="Scl_T" SIGNAME="__NOC__"/>
<PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="25" NAME="Sda" SIGNAME="__NOC__" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
<DESCRIPTION></DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="26" NAME="Scl" SIGNAME="__NOC__" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
<DESCRIPTION></DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="i2c_0" TYPE="XIL_AXI_IIC_V1">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="Sda_I"/>
<PORTMAP DIR="O" PHYSICAL="Sda_O"/>
<PORTMAP DIR="O" PHYSICAL="Sda_T"/>
<PORTMAP DIR="I" PHYSICAL="Scl_I"/>
<PORTMAP DIR="O" PHYSICAL="Scl_O"/>
<PORTMAP DIR="O" PHYSICAL="Scl_T"/>
<PORTMAP DIR="IO" PHYSICAL="Sda"/>
<PORTMAP DIR="IO" PHYSICAL="Scl"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0005FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_sd_0" IPTYPE="PERIPHERAL" MHS_INDEX="24" MODCLASS="PERIPHERAL" MODTYPE="ps7_sdio">
<DESCRIPTION TYPE="SHORT">PS7 SDIO Controller</DESCRIPTION>
<DESCRIPTION TYPE="LONG">SD/SDIO/MMC Controller</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0100000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0100FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_SDIO_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_CD" TYPE="STRING" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_HAS_WP" TYPE="STRING" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_HAS_POWER" TYPE="STRING" VALUE="0"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0100FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_ethernet_0" IPTYPE="PERIPHERAL" MHS_INDEX="25" MODCLASS="PERIPHERAL" MODTYPE="ps7_ethernet">
<DESCRIPTION TYPE="SHORT">PS7 Ethernet Embedded IP</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Embedded Ethernet core that implements a Tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC to support MII/GMII/SGMII/RGMII/1000Base-X PHY types</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000B000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000BFFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_ENET_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="125000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_ENET_SLCR_1000Mbps_DIV0" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_ENET_SLCR_1000Mbps_DIV1" TYPE="INTEGER" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_ENET_SLCR_100Mbps_DIV0" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="6" NAME="C_ENET_SLCR_100Mbps_DIV1" TYPE="INTEGER" VALUE="5"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="7" NAME="C_ENET_SLCR_10Mbps_DIV0" TYPE="INTEGER" VALUE="8"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="8" NAME="C_ENET_SLCR_10Mbps_DIV1" TYPE="INTEGER" VALUE="50"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="9" NAME="C_HAS_MDIO" TYPE="STRING" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="10" NAME="C_ETH_MODE" TYPE="STRING" VALUE="1"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="11" NAME="C_ENET_RESET" VALUE="-1"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="1" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000BFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_usb_0" IPTYPE="PERIPHERAL" MHS_INDEX="26" MODCLASS="PERIPHERAL" MODTYPE="ps7_usb">
<DESCRIPTION TYPE="SHORT">PS7 USB2 Device</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 USB 2.0 Device Controller</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0002000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0002FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_USB_RESET" VALUE="MIO 46"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWID" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="2" MSB="3" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWID" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="4" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWLEN" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="5" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLOCK" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWLOCK" SIGNAME="ps7_axi_interconnect_0_M_AWLOCK">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WLAST" DIR="I" MPD_INDEX="14" NAME="S_AXI_WLAST" SIGNAME="ps7_axi_interconnect_0_M_WLAST">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="15" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="16" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BID" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="17" MSB="3" NAME="S_AXI_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BID" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="18" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="19" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="20" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARID" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARID" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="23" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARLEN" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="24" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="26" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLOCK" DIR="I" MPD_INDEX="27" NAME="S_AXI_ARLOCK" SIGNAME="ps7_axi_interconnect_0_M_ARLOCK">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="28" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="30" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RID" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="31" MSB="3" NAME="S_AXI_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RID" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="32" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RLAST" DIR="O" MPD_INDEX="34" NAME="S_AXI_RLAST" SIGNAME="ps7_axi_interconnect_0_M_RLAST">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="35" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="36" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="37" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="38" NAME="M_AXI_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="39" NAME="M_AXI_AWID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="41" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="42" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="44" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="45" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="46" NAME="M_AXI_AWLOCK" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="47" NAME="M_AXI_AWVALID" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="48" NAME="M_AXI_AWREADY" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="49" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="50" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32/8)-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="51" NAME="M_AXI_WLAST" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="52" NAME="M_AXI_WVALID" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="53" NAME="M_AXI_WREADY" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="54" NAME="M_AXI_BID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="55" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="56" NAME="M_AXI_BVALID" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="57" NAME="M_AXI_BREADY" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="58" NAME="M_AXI_ARID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="59" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="60" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="62" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="63" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="64" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="65" NAME="M_AXI_ARLOCK" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="66" NAME="M_AXI_ARVALID" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="67" NAME="M_AXI_ARREADY" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="68" NAME="M_AXI_RID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="69" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="M_AXI_RLAST" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="72" NAME="M_AXI_RVALID" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="73" NAME="M_AXI_RREADY" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="74" NAME="usb_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="usb_0" MPD_INDEX="75" NAME="ULPI_Clock" SIGIS="CLK" SIGNAME="__NOC__">
<DESCRIPTION>Ulpi input clock</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="76" NAME="ULPI_Reset" SIGNAME="__NOC__">
<DESCRIPTION>Ulpi reset</DESCRIPTION>
</PORT>
<PORT DIR="I" ENDIAN="LITTLE" IOS="usb_0" LEFT="7" LSB="0" MPD_INDEX="77" MSB="7" NAME="ULPI_Data_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
<DESCRIPTION>Ulpi input data</DESCRIPTION>
</PORT>
<PORT DIR="O" ENDIAN="LITTLE" IOS="usb_0" LEFT="7" LSB="0" MPD_INDEX="78" MSB="7" NAME="ULPI_Data_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
<DESCRIPTION>Ulpi output data</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="79" NAME="ULPI_Data_T" SIGNAME="__NOC__">
<DESCRIPTION>Ulpi data toggle</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="80" NAME="ULPI_Stop" SIGNAME="__NOC__">
<DESCRIPTION>Ulpi stop</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="usb_0" MPD_INDEX="81" NAME="ULPI_Next" SIGNAME="__NOC__">
<DESCRIPTION>Ulpi next</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="usb_0" MPD_INDEX="82" NAME="ULPI_Dir" SIGNAME="__NOC__">
<DESCRIPTION>Ulpi direction</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="83" NAME="vbus_detect" SIGNAME="__NOC__">
<DESCRIPTION>vbus detect</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="84" NAME="show_currentspeed" SIGNAME="__NOC__">
<DESCRIPTION>show current speed</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="85" NAME="running" SIGNAME="__NOC__">
<DESCRIPTION>running</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="86" NAME="suspended" SIGNAME="__NOC__">
<DESCRIPTION>suspended</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="87" NAME="disconnected" SIGNAME="__NOC__">
<DESCRIPTION>disconnected</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="88" NAME="configured" SIGNAME="__NOC__">
<DESCRIPTION>test mode 2</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="89" NAME="spare1" SIGNAME="__NOC__">
<DESCRIPTION>test mode 0</DESCRIPTION>
</PORT>
<PORT DIR="O" IOS="usb_0" MPD_INDEX="90" NAME="spare2" SIGNAME="__NOC__">
<DESCRIPTION>test mode 1</DESCRIPTION>
</PORT>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="usb_0" IS_THREE_STATE="TRUE" LEFT="7" LSB="0" MPD_INDEX="91" MSB="7" NAME="ULPI_Data" RIGHT="0" SIGNAME="__NOC__" TRI_I="ULPI_Data_I" TRI_O="ULPI_Data_O" TRI_T="ULPI_Data_T" VECFORMULA="[7:0]">
<DESCRIPTION>Ulpi bi-directional data</DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARPROT"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARLOCK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="M_AXI" TYPE="MASTER">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="M_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_ARESETN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_WDATA"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_WREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_BID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_BRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_BREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_ARREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_RID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_RLAST"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="usb_0" TYPE="XIL_AXI_USB2DEVICE_V1">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="ULPI_Clock"/>
<PORTMAP DIR="O" PHYSICAL="ULPI_Reset"/>
<PORTMAP DIR="I" PHYSICAL="ULPI_Data_I"/>
<PORTMAP DIR="O" PHYSICAL="ULPI_Data_O"/>
<PORTMAP DIR="O" PHYSICAL="ULPI_Data_T"/>
<PORTMAP DIR="O" PHYSICAL="ULPI_Stop"/>
<PORTMAP DIR="I" PHYSICAL="ULPI_Next"/>
<PORTMAP DIR="I" PHYSICAL="ULPI_Dir"/>
<PORTMAP DIR="O" PHYSICAL="vbus_detect"/>
<PORTMAP DIR="O" PHYSICAL="show_currentspeed"/>
<PORTMAP DIR="O" PHYSICAL="running"/>
<PORTMAP DIR="O" PHYSICAL="suspended"/>
<PORTMAP DIR="O" PHYSICAL="disconnected"/>
<PORTMAP DIR="O" PHYSICAL="configured"/>
<PORTMAP DIR="O" PHYSICAL="spare1"/>
<PORTMAP DIR="O" PHYSICAL="spare2"/>
<PORTMAP DIR="IO" PHYSICAL="ULPI_Data"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758104576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0002000" HIGHDECIMAL="3758108671" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0002FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_qspi_0" IPTYPE="PERIPHERAL" MHS_INDEX="27" MODCLASS="PERIPHERAL" MODTYPE="ps7_qspi">
<DESCRIPTION TYPE="SHORT">PS7 Quad SPI Interface</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Connects AXI-Lite to the SPI slaves supporting Standard/Dual/Quad interfaces</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000D000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000DFFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_QSPI_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="200000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_QSPI_MODE" TYPE="STRING" VALUE="0"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_FB_CLK" TYPE="STRING" VALUE="1"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="19" NAME="SCK_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="20" NAME="SCK_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="21" NAME="SCK_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="22" NAME="SS_I" SIGNAME="__NOC__" VECFORMULA="[(1-1):0]"/>
<PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="23" NAME="SS_O" SIGNAME="__NOC__" VECFORMULA="[(1-1):0]"/>
<PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="24" NAME="SS_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="25" NAME="SPISEL" SIGNAME="__NOC__">
<DESCRIPTION>Local QSPI Slave Select Active LOW Input</DESCRIPTION>
</PORT>
<PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="26" NAME="IO0_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="27" NAME="IO0_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="28" NAME="IO0_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="29" NAME="IO1_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="30" NAME="IO1_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="31" NAME="IO1_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="32" NAME="IO2_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="33" NAME="IO2_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="34" NAME="IO2_T" SIGNAME="__NOC__"/>
<PORT DIR="I" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="35" NAME="IO3_I" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="36" NAME="IO3_O" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="37" NAME="IO3_T" SIGNAME="__NOC__"/>
<PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="38" NAME="SCK" SIGNAME="__NOC__" TRI_I="SCK_I" TRI_O="SCK_O" TRI_T="SCK_T">
<DESCRIPTION>QSPI Bus Clock</DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" MPD_INDEX="39" NAME="SS" SIGNAME="__NOC__" TRI_I="SS_I" TRI_O="SS_O" TRI_T="SS_T" VECFORMULA="[(1-1):0]">
<DESCRIPTION>Slave Select Vector</DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" MPD_INDEX="40" NAME="IO0" SIGNAME="__NOC__" TRI_I="IO0_I" TRI_O="IO0_O" TRI_T="IO0_T">
<DESCRIPTION>Similar to Master Out Slave In</DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" MPD_INDEX="41" NAME="IO1" SIGNAME="__NOC__" TRI_I="IO1_I" TRI_O="IO1_O" TRI_T="IO1_T">
<DESCRIPTION>Similar to Master In Slave Out</DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="42" NAME="IO2" SIGNAME="__NOC__" TRI_I="IO2_I" TRI_O="IO2_O" TRI_T="IO2_T">
<DESCRIPTION>3rd Data line in QUAD mode</DESCRIPTION>
</PORT>
<PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="43" NAME="IO3" SIGNAME="__NOC__" TRI_I="IO3_I" TRI_O="IO3_O" TRI_T="IO3_T">
<DESCRIPTION>4th Data line in QUAD mode</DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="ps7_qspi_0" TYPE="XIL_QSPI_V1">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="SCK_I"/>
<PORTMAP DIR="O" PHYSICAL="SCK_O"/>
<PORTMAP DIR="O" PHYSICAL="SCK_T"/>
<PORTMAP DIR="I" PHYSICAL="SS_I"/>
<PORTMAP DIR="O" PHYSICAL="SS_O"/>
<PORTMAP DIR="O" PHYSICAL="SS_T"/>
<PORTMAP DIR="I" PHYSICAL="SPISEL"/>
<PORTMAP DIR="I" PHYSICAL="IO0_I"/>
<PORTMAP DIR="O" PHYSICAL="IO0_O"/>
<PORTMAP DIR="O" PHYSICAL="IO0_T"/>
<PORTMAP DIR="I" PHYSICAL="IO1_I"/>
<PORTMAP DIR="O" PHYSICAL="IO1_O"/>
<PORTMAP DIR="O" PHYSICAL="IO1_T"/>
<PORTMAP DIR="I" PHYSICAL="IO2_I"/>
<PORTMAP DIR="O" PHYSICAL="IO2_O"/>
<PORTMAP DIR="O" PHYSICAL="IO2_T"/>
<PORTMAP DIR="I" PHYSICAL="IO3_I"/>
<PORTMAP DIR="O" PHYSICAL="IO3_O"/>
<PORTMAP DIR="O" PHYSICAL="IO3_T"/>
<PORTMAP DIR="IO" PHYSICAL="SCK"/>
<PORTMAP DIR="IO" PHYSICAL="SS"/>
<PORTMAP DIR="IO" PHYSICAL="IO0"/>
<PORTMAP DIR="IO" PHYSICAL="IO1"/>
<PORTMAP DIR="IO" PHYSICAL="IO2"/>
<PORTMAP DIR="IO" PHYSICAL="IO3"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758149632" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000D000" HIGHDECIMAL="3758153727" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000DFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_qspi_linear_0" IPTYPE="PERIPHERAL" MHS_INDEX="28" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_qspi_linear">
<DESCRIPTION TYPE="SHORT">PS7 QSPI LINEAR</DESCRIPTION>
<DESCRIPTION TYPE="LONG">QSPI LINEAR interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFC000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFCFFFFFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_QSPI_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="15000000"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4227858432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFC000000" HIGHDECIMAL="4244635647" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFCFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_ddr_0" IPTYPE="PERIPHERAL" MHS_INDEX="29" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_ddr">
<DESCRIPTION TYPE="SHORT">PS7 Memory Controller(DDR2/DDR3)</DESCRIPTION>
<DESCRIPTION TYPE="LONG">7-Series memory controller</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00100000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_S_AXI_HP0_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_S_AXI_HP0_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_S_AXI_HP1_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_S_AXI_HP1_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="6" NAME="C_S_AXI_HP2_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="7" NAME="C_S_AXI_HP2_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="8" NAME="C_S_AXI_HP3_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="9" NAME="C_S_AXI_HP3_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="clk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="1" NAME="clk_ref" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="2" NAME="mem_refclk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="3" NAME="freq_refclk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="4" NAME="pll_lock" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="5" NAME="sync_pulse" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_aresetn" DIR="I" MPD_INDEX="6" NAME="aresetn" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" MPD_INDEX="7" NAME="iodelay_ctrl_rdy_i" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="8" NAME="iodelay_ctrl_rdy_o" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="9" NAME="init_calib_complete" SIGNAME="__NOC__"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" LEFT="13" LSB="0" MPD_INDEX="10" MSB="13" NAME="ddr_addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[13:0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="ddr_ba" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3-1:0]"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="12" NAME="ddr_cas_n" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="13" NAME="ddr_ck_p" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="14" NAME="ddr_ck_n" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="15" NAME="ddr_cke" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="16" NAME="ddr_cs_n" SIGNAME="__NOC__" VECFORMULA="[1*1-1:0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" LEFT="3" LSB="0" MPD_INDEX="17" MSB="3" NAME="ddr_dm" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4-1:0]"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="18" NAME="ddr_odt" SIGNAME="__NOC__" VECFORMULA="[1*1-1:0]"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="19" NAME="ddr_ras_n" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="20" NAME="ddr_reset_n" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="21" NAME="ddr_parity" SIGNAME="__NOC__"/>
<PORT DIR="O" IOS="memory_0" MPD_INDEX="22" NAME="ddr_we_n" SIGNAME="__NOC__"/>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" LEFT="30" LSB="0" MPD_INDEX="23" MSB="30" NAME="ddr_dq" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31-1:0]"/>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MPD_INDEX="24" MSB="3" NAME="ddr_dqs_p" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4-1:0]"/>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="ddr_dqs_n" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4-1:0]"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awid" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="s_axi_awid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awid" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="s_axi_awaddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awaddr" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="28" MSB="7" NAME="s_axi_awlen" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awlen" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="29" MSB="2" NAME="s_axi_awsize" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awsize" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="s_axi_awburst" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awburst" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awlock" DIR="I" MPD_INDEX="31" NAME="s_axi_awlock" SIGNAME="ps7_axi_interconnect_0_M_awlock" VECFORMULA="[0:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="32" MSB="3" NAME="s_axi_awcache" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awcache" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="s_axi_awprot" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awprot" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="s_axi_awqos" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awqos" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWQOS"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awvalid" DIR="I" MPD_INDEX="35" NAME="s_axi_awvalid" SIGNAME="ps7_axi_interconnect_0_M_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awready" DIR="O" MPD_INDEX="36" NAME="s_axi_awready" SIGNAME="ps7_axi_interconnect_0_M_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="37" MSB="31" NAME="s_axi_wdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_wdata" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="s_axi_wstrb" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_wstrb" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wlast" DIR="I" MPD_INDEX="39" NAME="s_axi_wlast" SIGNAME="ps7_axi_interconnect_0_M_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wvalid" DIR="I" MPD_INDEX="40" NAME="s_axi_wvalid" SIGNAME="ps7_axi_interconnect_0_M_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wready" DIR="O" MPD_INDEX="41" NAME="s_axi_wready" SIGNAME="ps7_axi_interconnect_0_M_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bid" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s_axi_bid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_bid" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="s_axi_bresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_bresp" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bvalid" DIR="O" MPD_INDEX="44" NAME="s_axi_bvalid" SIGNAME="ps7_axi_interconnect_0_M_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bready" DIR="I" MPD_INDEX="45" NAME="s_axi_bready" SIGNAME="ps7_axi_interconnect_0_M_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arid" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s_axi_arid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arid" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="47" MSB="31" NAME="s_axi_araddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_araddr" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="48" MSB="7" NAME="s_axi_arlen" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arlen" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="49" MSB="2" NAME="s_axi_arsize" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arsize" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="50" MSB="1" NAME="s_axi_arburst" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arburst" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arlock" DIR="I" MPD_INDEX="51" NAME="s_axi_arlock" SIGNAME="ps7_axi_interconnect_0_M_arlock" VECFORMULA="[0:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="52" MSB="3" NAME="s_axi_arcache" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arcache" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="53" MSB="2" NAME="s_axi_arprot" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arprot" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="54" MSB="3" NAME="s_axi_arqos" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arqos" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARQOS"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arvalid" DIR="I" MPD_INDEX="55" NAME="s_axi_arvalid" SIGNAME="ps7_axi_interconnect_0_M_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arready" DIR="O" MPD_INDEX="56" NAME="s_axi_arready" SIGNAME="ps7_axi_interconnect_0_M_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rid" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="s_axi_rid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_rid" VECFORMULA="[(4-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="58" MSB="31" NAME="s_axi_rdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_rdata" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="s_axi_rresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_rresp" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rlast" DIR="O" MPD_INDEX="60" NAME="s_axi_rlast" SIGNAME="ps7_axi_interconnect_0_M_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rvalid" DIR="O" MPD_INDEX="61" NAME="s_axi_rvalid" SIGNAME="ps7_axi_interconnect_0_M_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rready" DIR="I" MPD_INDEX="62" NAME="s_axi_rready" SIGNAME="ps7_axi_interconnect_0_M_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="clk"/>
<PORTMAP DIR="I" PHYSICAL="aresetn"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awaddr"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awlen"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awsize"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awburst"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awlock"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awcache"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awprot"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awqos"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_awvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_awready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_wdata"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_wstrb"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_wlast"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_wvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_wready"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_bid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_bresp"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_bvalid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_bready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_araddr"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arlen"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arsize"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arburst"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arlock"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arcache"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arprot"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arqos"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_arvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_arready"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_rid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_rdata"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_rresp"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_rlast"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_rvalid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_rready"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="1" NAME="S_AXI_HP0" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="S_AXI_HP1" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_HP2" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_HP3" TYPE="SLAVE"/>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
<PORTMAPS>
<PORTMAP DIR="O" PHYSICAL="ddr_addr"/>
<PORTMAP DIR="O" PHYSICAL="ddr_ba"/>
<PORTMAP DIR="O" PHYSICAL="ddr_cas_n"/>
<PORTMAP DIR="O" PHYSICAL="ddr_ck_p"/>
<PORTMAP DIR="O" PHYSICAL="ddr_ck_n"/>
<PORTMAP DIR="O" PHYSICAL="ddr_cke"/>
<PORTMAP DIR="O" PHYSICAL="ddr_cs_n"/>
<PORTMAP DIR="O" PHYSICAL="ddr_dm"/>
<PORTMAP DIR="O" PHYSICAL="ddr_odt"/>
<PORTMAP DIR="O" PHYSICAL="ddr_ras_n"/>
<PORTMAP DIR="O" PHYSICAL="ddr_reset_n"/>
<PORTMAP DIR="O" PHYSICAL="ddr_parity"/>
<PORTMAP DIR="O" PHYSICAL="ddr_we_n"/>
<PORTMAP DIR="IO" PHYSICAL="ddr_dq"/>
<PORTMAP DIR="IO" PHYSICAL="ddr_dqs_p"/>
<PORTMAP DIR="IO" PHYSICAL="ddr_dqs_n"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1048576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00100000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="535822336" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP0_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP0_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP0"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP1_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP1_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP1"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP2_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP2_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP2"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP3_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP3_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP3"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_gpio_0" IPTYPE="PERIPHERAL" MHS_INDEX="30" MODCLASS="PERIPHERAL" MODTYPE="ps7_gpio">
<DESCRIPTION TYPE="SHORT">PS7 General Purpose IO</DESCRIPTION>
<DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PS7.</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000A000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000AFFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_MIO_GPIO_MASK" TYPE="STD_LOGIC_VECTOR" VALUE="0xc00000000c281"/>
<PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_EMIO_GPIO_WIDTH" TYPE="INTEGER" VALUE="64"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="63" LSB="0" MPD_INDEX="19" MSB="63" NAME="GPIO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="63" LSB="0" MPD_INDEX="20" MSB="63" NAME="GPIO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="63" LSB="0" MPD_INDEX="21" MSB="63" NAME="GPIO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="63" LSB="0" MPD_INDEX="22" MSB="63" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[63:0]">
<DESCRIPTION>GPIO Data IO</DESCRIPTION>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="GPIO_I"/>
<PORTMAP DIR="O" PHYSICAL="GPIO_O"/>
<PORTMAP DIR="O" PHYSICAL="GPIO_T"/>
<PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758137344" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000A000" HIGHDECIMAL="3758141439" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000AFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="5.02.a" INSTANCE="ps7_cortexa9_0" IPTYPE="PROCESSOR" MHS_INDEX="31" MODCLASS="PROCESSOR" MODTYPE="ps7_cortexa9">
<DESCRIPTION TYPE="SHORT">Processing System</DESCRIPTION>
<DESCRIPTION TYPE="LONG">ZYNQ Processing System</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_CPU_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="650000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_CPU_1X_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_CPU_REF_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
</PARAMETERS>
<PORTS>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="1" NAME="MB_RESET" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="3" NAME="EXT_BRK" SIGNAME="Ext_BRK">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MPD_INDEX="5" NAME="DBG_STOP" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="6" NAME="MB_Halted" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="7" NAME="MB_Error" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWID" DIR="O" MPD_INDEX="8" NAME="M_AXI_DP_AWID" SIGNAME="ps7_axi_interconnect_0_S_AWID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="10" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLEN" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="12" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" DIR="O" MPD_INDEX="13" NAME="M_AXI_DP_AWLOCK" SIGNAME="ps7_axi_interconnect_0_S_AWLOCK">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="15" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="16" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWQOS"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWVALID" DIR="O" MPD_INDEX="17" NAME="M_AXI_DP_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWREADY" DIR="I" MPD_INDEX="18" NAME="M_AXI_DP_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WLAST" DIR="O" MPD_INDEX="21" NAME="M_AXI_DP_WLAST" SIGNAME="ps7_axi_interconnect_0_S_WLAST">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WVALID" DIR="O" MPD_INDEX="22" NAME="M_AXI_DP_WVALID" SIGNAME="ps7_axi_interconnect_0_S_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WREADY" DIR="I" MPD_INDEX="23" NAME="M_AXI_DP_WREADY" SIGNAME="ps7_axi_interconnect_0_S_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BID" DIR="I" MPD_INDEX="24" NAME="M_AXI_DP_BID" SIGNAME="ps7_axi_interconnect_0_S_BID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BVALID" DIR="I" MPD_INDEX="26" NAME="M_AXI_DP_BVALID" SIGNAME="ps7_axi_interconnect_0_S_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BREADY" DIR="O" MPD_INDEX="27" NAME="M_AXI_DP_BREADY" SIGNAME="ps7_axi_interconnect_0_S_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARID" DIR="O" MPD_INDEX="28" NAME="M_AXI_DP_ARID" SIGNAME="ps7_axi_interconnect_0_S_ARID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="30" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLEN" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="31" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="32" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" DIR="O" MPD_INDEX="33" NAME="M_AXI_DP_ARLOCK" SIGNAME="ps7_axi_interconnect_0_S_ARLOCK">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="35" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARQOS"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARVALID" DIR="O" MPD_INDEX="37" NAME="M_AXI_DP_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARREADY" DIR="I" MPD_INDEX="38" NAME="M_AXI_DP_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RID" DIR="I" MPD_INDEX="39" NAME="M_AXI_DP_RID" SIGNAME="ps7_axi_interconnect_0_S_RID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RLAST" DIR="I" MPD_INDEX="42" NAME="M_AXI_DP_RLAST" SIGNAME="ps7_axi_interconnect_0_S_RLAST">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RVALID" DIR="I" MPD_INDEX="43" NAME="M_AXI_DP_RVALID" SIGNAME="ps7_axi_interconnect_0_S_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RREADY" DIR="O" MPD_INDEX="44" NAME="M_AXI_DP_RREADY" SIGNAME="ps7_axi_interconnect_0_S_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="M_AXI_DP" TYPE="MASTER">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="CLK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0000FFF" INSTANCE="ps7_uart_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0001FFF" INSTANCE="ps7_uart_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0004FFF" INSTANCE="ps7_i2c_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160782336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8008000" HIGHDECIMAL="4160786431" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8008FFF" INSTANCE="ps7_afi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160786432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8009000" HIGHDECIMAL="4160790527" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8009FFF" INSTANCE="ps7_afi_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160790528" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800A000" HIGHDECIMAL="4160794623" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800AFFF" INSTANCE="ps7_afi_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160794624" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800B000" HIGHDECIMAL="4160798719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800BFFF" INSTANCE="ps7_afi_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0005FFF" INSTANCE="ps7_i2c_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0100FFF" INSTANCE="ps7_sd_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000BFFF" INSTANCE="ps7_ethernet_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758104576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0002000" HIGHDECIMAL="3758108671" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0002FFF" INSTANCE="ps7_usb_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758149632" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000D000" HIGHDECIMAL="3758153727" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000DFFF" INSTANCE="ps7_qspi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4227858432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFC000000" HIGHDECIMAL="4244635647" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFCFFFFFF" INSTANCE="ps7_qspi_linear_0" IS_DATA="FALSE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1048576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00100000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="ps7_ddr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="535822336" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3758137344" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000A000" HIGHDECIMAL="3758141439" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000AFFF" INSTANCE="ps7_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160774144" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8006000" HIGHDECIMAL="4160778239" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8006FFF" INSTANCE="ps7_ddrc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160778240" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007000" HIGHDECIMAL="4160778495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF80070FF" INSTANCE="ps7_dev_cfg_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160778496" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007100" HIGHDECIMAL="4160778528" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8007120" INSTANCE="ps7_xadc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="33" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4169138176" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8800000" HIGHDECIMAL="4170186751" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF88FFFFF" INSTANCE="ps7_coresight_comp_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160798720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800C000" HIGHDECIMAL="4160802815" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800CFFF" INSTANCE="ps7_ocmc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4170186752" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8900000" HIGHDECIMAL="4171235327" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF89FFFFF" INSTANCE="ps7_gpv_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176478208" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00000" HIGHDECIMAL="4176478460" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F000FC" INSTANCE="ps7_scuc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="253" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176482304" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F01000" HIGHDECIMAL="4176486399" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F01FFF" INSTANCE="ps7_intc_dist_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176478720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00200" HIGHDECIMAL="4176478975" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F002FF" INSTANCE="ps7_globaltimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176486400" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F02000" HIGHDECIMAL="4176490495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F02FFF" INSTANCE="ps7_l2cachec_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160761856" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8003000" HIGHDECIMAL="4160765951" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8003FFF" INSTANCE="ps7_dma_s" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3760193536" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0200000" HIGHDECIMAL="3760197631" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0200FFF" INSTANCE="ps7_iop_bus_config_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="196607" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x0002FFFF" INSTANCE="ps7_ram_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="196608" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294901760" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFFFF0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFFFFFDFF" INSTANCE="ps7_ram_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65024" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176478464" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00100" HIGHDECIMAL="4176478719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F001FF" INSTANCE="ps7_scugic_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176479744" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00600" HIGHDECIMAL="4176479775" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F0061F" INSTANCE="ps7_scutimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="32" SIZEABRV="32">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176479776" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00620" HIGHDECIMAL="4176479999" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F006FF" INSTANCE="ps7_scuwdt_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="224" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8000000" HIGHDECIMAL="4160753663" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8000FFF" INSTANCE="ps7_slcr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160765952" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8004000" HIGHDECIMAL="4160770047" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8004FFF" INSTANCE="ps7_dma_ns" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" INSTANCE="pwm_recorder_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994915840" BASENAME="C_BASEADDR" BASEVALUE="0x76e80000" HIGHDECIMAL="1994981375" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e8ffff" INSTANCE="pwm_recorder_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994784768" BASENAME="C_BASEADDR" BASEVALUE="0x76e60000" HIGHDECIMAL="1994850303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e6ffff" INSTANCE="pwm_recorder_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994653696" BASENAME="C_BASEADDR" BASEVALUE="0x76e40000" HIGHDECIMAL="1994719231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e4ffff" INSTANCE="pwm_recorder_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994522624" BASENAME="C_BASEADDR" BASEVALUE="0x76e20000" HIGHDECIMAL="1994588159" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e2ffff" INSTANCE="pwm_recorder_4" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994391552" BASENAME="C_BASEADDR" BASEVALUE="0x76e00000" HIGHDECIMAL="1994457087" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e0ffff" INSTANCE="pwm_recorder_5" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="btns_4bits_tri_io" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034630656" BASENAME="C_BASEADDR" BASEVALUE="0x79460000" HIGHDECIMAL="2034696191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7946ffff" INSTANCE="pwm_signal_out_wkillswitch_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034499584" BASENAME="C_BASEADDR" BASEVALUE="0x79440000" HIGHDECIMAL="2034565119" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7944ffff" INSTANCE="pwm_signal_out_wkillswitch_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034368512" BASENAME="C_BASEADDR" BASEVALUE="0x79420000" HIGHDECIMAL="2034434047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7942ffff" INSTANCE="pwm_signal_out_wkillswitch_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034237440" BASENAME="C_BASEADDR" BASEVALUE="0x79400000" HIGHDECIMAL="2034302975" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7940ffff" INSTANCE="pwm_signal_out_wkillswitch_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1115684864" BASENAME="C_BASEADDR" BASEVALUE="0x42800000" HIGHDECIMAL="1115750399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4280ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
</MEMORYMAP>
<PERIPHERALS>
<PERIPHERAL INSTANCE="ps7_uart_0"/>
<PERIPHERAL INSTANCE="ps7_uart_1"/>
<PERIPHERAL INSTANCE="ps7_i2c_0"/>
<PERIPHERAL INSTANCE="ps7_afi_0"/>
<PERIPHERAL INSTANCE="ps7_afi_1"/>
<PERIPHERAL INSTANCE="ps7_afi_2"/>
<PERIPHERAL INSTANCE="ps7_afi_3"/>
<PERIPHERAL INSTANCE="ps7_i2c_1"/>
<PERIPHERAL INSTANCE="ps7_sd_0"/>
<PERIPHERAL INSTANCE="ps7_ethernet_0"/>
<PERIPHERAL INSTANCE="ps7_usb_0"/>
<PERIPHERAL INSTANCE="ps7_qspi_0"/>
<PERIPHERAL INSTANCE="ps7_qspi_linear_0"/>
<PERIPHERAL INSTANCE="ps7_ddr_0"/>
<PERIPHERAL INSTANCE="ps7_gpio_0"/>
<PERIPHERAL INSTANCE="ps7_ddrc_0"/>
<PERIPHERAL INSTANCE="ps7_dev_cfg_0"/>
<PERIPHERAL INSTANCE="ps7_xadc_0"/>
<PERIPHERAL INSTANCE="ps7_coresight_comp_0"/>
<PERIPHERAL INSTANCE="ps7_ocmc_0"/>
<PERIPHERAL INSTANCE="ps7_gpv_0"/>
<PERIPHERAL INSTANCE="ps7_scuc_0"/>
<PERIPHERAL INSTANCE="ps7_intc_dist_0"/>
<PERIPHERAL INSTANCE="ps7_globaltimer_0"/>
<PERIPHERAL INSTANCE="ps7_l2cachec_0"/>
<PERIPHERAL INSTANCE="ps7_dma_s"/>
<PERIPHERAL INSTANCE="ps7_iop_bus_config_0"/>
<PERIPHERAL INSTANCE="ps7_ram_0"/>
<PERIPHERAL INSTANCE="ps7_ram_1"/>
<PERIPHERAL INSTANCE="ps7_scugic_0"/>
<PERIPHERAL INSTANCE="ps7_scutimer_0"/>
<PERIPHERAL INSTANCE="ps7_scuwdt_0"/>
<PERIPHERAL INSTANCE="ps7_slcr_0"/>
<PERIPHERAL INSTANCE="ps7_dma_ns"/>
<PERIPHERAL INSTANCE="pwm_recorder_0"/>
<PERIPHERAL INSTANCE="pwm_recorder_1"/>
<PERIPHERAL INSTANCE="pwm_recorder_2"/>
<PERIPHERAL INSTANCE="pwm_recorder_3"/>
<PERIPHERAL INSTANCE="pwm_recorder_4"/>
<PERIPHERAL INSTANCE="pwm_recorder_5"/>
<PERIPHERAL INSTANCE="btns_4bits_tri_io"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_0"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_1"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_2"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_3"/>
<PERIPHERAL INSTANCE="axi_timer_0"/>
</PERIPHERALS>
</MODULE>
<MODULE HWVERSION="5.02.a" INSTANCE="ps7_cortexa9_1" IPTYPE="PROCESSOR" MHS_INDEX="32" MODCLASS="PROCESSOR" MODTYPE="ps7_cortexa9">
<DESCRIPTION TYPE="SHORT">Processing System</DESCRIPTION>
<DESCRIPTION TYPE="LONG">ZYNQ Processing System</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_CPU_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="650000000"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_CPU_1X_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_CPU_REF_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
</PARAMETERS>
<PORTS>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="1" NAME="MB_RESET" SIGIS="RST" SIGNAME="__NOC__"/>
<PORT DIR="I" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="3" NAME="EXT_BRK" SIGNAME="Ext_BRK">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" MPD_INDEX="5" NAME="DBG_STOP" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="6" NAME="MB_Halted" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="7" NAME="MB_Error" SIGNAME="__NOC__"/>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWID" DIR="O" MPD_INDEX="8" NAME="M_AXI_DP_AWID" SIGNAME="ps7_axi_interconnect_0_S_AWID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="10" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLEN" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="12" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWBURST" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" DIR="O" MPD_INDEX="13" NAME="M_AXI_DP_AWLOCK" SIGNAME="ps7_axi_interconnect_0_S_AWLOCK">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="15" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWPROT" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="16" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWQOS" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWQOS"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWVALID" DIR="O" MPD_INDEX="17" NAME="M_AXI_DP_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWREADY" DIR="I" MPD_INDEX="18" NAME="M_AXI_DP_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WLAST" DIR="O" MPD_INDEX="21" NAME="M_AXI_DP_WLAST" SIGNAME="ps7_axi_interconnect_0_S_WLAST">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WVALID" DIR="O" MPD_INDEX="22" NAME="M_AXI_DP_WVALID" SIGNAME="ps7_axi_interconnect_0_S_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WREADY" DIR="I" MPD_INDEX="23" NAME="M_AXI_DP_WREADY" SIGNAME="ps7_axi_interconnect_0_S_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BID" DIR="I" MPD_INDEX="24" NAME="M_AXI_DP_BID" SIGNAME="ps7_axi_interconnect_0_S_BID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BVALID" DIR="I" MPD_INDEX="26" NAME="M_AXI_DP_BVALID" SIGNAME="ps7_axi_interconnect_0_S_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BREADY" DIR="O" MPD_INDEX="27" NAME="M_AXI_DP_BREADY" SIGNAME="ps7_axi_interconnect_0_S_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARID" DIR="O" MPD_INDEX="28" NAME="M_AXI_DP_ARID" SIGNAME="ps7_axi_interconnect_0_S_ARID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="30" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLEN" VECFORMULA="[7:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLEN"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="31" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARSIZE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="32" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARBURST" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARBURST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" DIR="O" MPD_INDEX="33" NAME="M_AXI_DP_ARLOCK" SIGNAME="ps7_axi_interconnect_0_S_ARLOCK">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLOCK"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARCACHE"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="35" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARPROT" VECFORMULA="[2:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARPROT"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARQOS" VECFORMULA="[3:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARQOS"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARVALID" DIR="O" MPD_INDEX="37" NAME="M_AXI_DP_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARREADY" DIR="I" MPD_INDEX="38" NAME="M_AXI_DP_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RID" DIR="I" MPD_INDEX="39" NAME="M_AXI_DP_RID" SIGNAME="ps7_axi_interconnect_0_S_RID" VECFORMULA="[(1-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RLAST" DIR="I" MPD_INDEX="42" NAME="M_AXI_DP_RLAST" SIGNAME="ps7_axi_interconnect_0_S_RLAST">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RLAST"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RVALID" DIR="I" MPD_INDEX="43" NAME="M_AXI_DP_RVALID" SIGNAME="ps7_axi_interconnect_0_S_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RREADY" DIR="O" MPD_INDEX="44" NAME="M_AXI_DP_RREADY" SIGNAME="ps7_axi_interconnect_0_S_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="M_AXI_DP" TYPE="MASTER">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="CLK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0000FFF" INSTANCE="ps7_uart_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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<MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0001FFF" INSTANCE="ps7_uart_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
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<MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0004FFF" INSTANCE="ps7_i2c_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
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<MEMRANGE BASEDECIMAL="4160782336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8008000" HIGHDECIMAL="4160786431" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8008FFF" INSTANCE="ps7_afi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
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<MEMRANGE BASEDECIMAL="4160786432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8009000" HIGHDECIMAL="4160790527" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8009FFF" INSTANCE="ps7_afi_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
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<MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0005FFF" INSTANCE="ps7_i2c_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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<MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0100FFF" INSTANCE="ps7_sd_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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<MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000BFFF" INSTANCE="ps7_ethernet_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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<MEMRANGE BASEDECIMAL="3758104576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0002000" HIGHDECIMAL="3758108671" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0002FFF" INSTANCE="ps7_usb_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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<ACCESSROUTE>
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<MEMRANGE BASEDECIMAL="4227858432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFC000000" HIGHDECIMAL="4244635647" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFCFFFFFF" INSTANCE="ps7_qspi_linear_0" IS_DATA="FALSE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
<ACCESSROUTE>
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<MEMRANGE BASEDECIMAL="1048576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00100000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="ps7_ddr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="535822336" SIZEABRV="U">
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<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
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</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160774144" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8006000" HIGHDECIMAL="4160778239" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8006FFF" INSTANCE="ps7_ddrc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
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</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160778496" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007100" HIGHDECIMAL="4160778528" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8007120" INSTANCE="ps7_xadc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="33" SIZEABRV="U">
<ACCESSROUTE>
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</MEMRANGE>
<MEMRANGE BASEDECIMAL="4169138176" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8800000" HIGHDECIMAL="4170186751" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF88FFFFF" INSTANCE="ps7_coresight_comp_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
<ACCESSROUTE>
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</MEMRANGE>
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<ACCESSROUTE>
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</MEMRANGE>
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<ACCESSROUTE>
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</MEMRANGE>
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<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176482304" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F01000" HIGHDECIMAL="4176486399" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F01FFF" INSTANCE="ps7_intc_dist_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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</ACCESSROUTE>
</MEMRANGE>
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<ACCESSROUTE>
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</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176486400" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F02000" HIGHDECIMAL="4176490495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F02FFF" INSTANCE="ps7_l2cachec_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160761856" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8003000" HIGHDECIMAL="4160765951" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8003FFF" INSTANCE="ps7_dma_s" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="3760193536" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0200000" HIGHDECIMAL="3760197631" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0200FFF" INSTANCE="ps7_iop_bus_config_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
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</ACCESSROUTE>
</MEMRANGE>
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<ACCESSROUTE>
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</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294901760" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFFFF0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFFFFFDFF" INSTANCE="ps7_ram_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65024" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176478464" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00100" HIGHDECIMAL="4176478719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F001FF" INSTANCE="ps7_scugic_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176479744" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00600" HIGHDECIMAL="4176479775" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F0061F" INSTANCE="ps7_scutimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="32" SIZEABRV="32">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4176479776" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00620" HIGHDECIMAL="4176479999" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F006FF" INSTANCE="ps7_scuwdt_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="224" SIZEABRV="U">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8000000" HIGHDECIMAL="4160753663" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8000FFF" INSTANCE="ps7_slcr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4160765952" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8004000" HIGHDECIMAL="4160770047" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8004FFF" INSTANCE="ps7_dma_ns" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" INSTANCE="pwm_recorder_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994915840" BASENAME="C_BASEADDR" BASEVALUE="0x76e80000" HIGHDECIMAL="1994981375" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e8ffff" INSTANCE="pwm_recorder_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994784768" BASENAME="C_BASEADDR" BASEVALUE="0x76e60000" HIGHDECIMAL="1994850303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e6ffff" INSTANCE="pwm_recorder_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994653696" BASENAME="C_BASEADDR" BASEVALUE="0x76e40000" HIGHDECIMAL="1994719231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e4ffff" INSTANCE="pwm_recorder_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994522624" BASENAME="C_BASEADDR" BASEVALUE="0x76e20000" HIGHDECIMAL="1994588159" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e2ffff" INSTANCE="pwm_recorder_4" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1994391552" BASENAME="C_BASEADDR" BASEVALUE="0x76e00000" HIGHDECIMAL="1994457087" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e0ffff" INSTANCE="pwm_recorder_5" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="btns_4bits_tri_io" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034630656" BASENAME="C_BASEADDR" BASEVALUE="0x79460000" HIGHDECIMAL="2034696191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7946ffff" INSTANCE="pwm_signal_out_wkillswitch_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034499584" BASENAME="C_BASEADDR" BASEVALUE="0x79440000" HIGHDECIMAL="2034565119" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7944ffff" INSTANCE="pwm_signal_out_wkillswitch_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034368512" BASENAME="C_BASEADDR" BASEVALUE="0x79420000" HIGHDECIMAL="2034434047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7942ffff" INSTANCE="pwm_signal_out_wkillswitch_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2034237440" BASENAME="C_BASEADDR" BASEVALUE="0x79400000" HIGHDECIMAL="2034302975" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7940ffff" INSTANCE="pwm_signal_out_wkillswitch_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="1115684864" BASENAME="C_BASEADDR" BASEVALUE="0x42800000" HIGHDECIMAL="1115750399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4280ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
<ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
</ACCESSROUTE>
</MEMRANGE>
</MEMORYMAP>
<PERIPHERALS>
<PERIPHERAL INSTANCE="ps7_uart_0"/>
<PERIPHERAL INSTANCE="ps7_uart_1"/>
<PERIPHERAL INSTANCE="ps7_i2c_0"/>
<PERIPHERAL INSTANCE="ps7_afi_0"/>
<PERIPHERAL INSTANCE="ps7_afi_1"/>
<PERIPHERAL INSTANCE="ps7_afi_2"/>
<PERIPHERAL INSTANCE="ps7_afi_3"/>
<PERIPHERAL INSTANCE="ps7_i2c_1"/>
<PERIPHERAL INSTANCE="ps7_sd_0"/>
<PERIPHERAL INSTANCE="ps7_ethernet_0"/>
<PERIPHERAL INSTANCE="ps7_usb_0"/>
<PERIPHERAL INSTANCE="ps7_qspi_0"/>
<PERIPHERAL INSTANCE="ps7_qspi_linear_0"/>
<PERIPHERAL INSTANCE="ps7_ddr_0"/>
<PERIPHERAL INSTANCE="ps7_gpio_0"/>
<PERIPHERAL INSTANCE="ps7_ddrc_0"/>
<PERIPHERAL INSTANCE="ps7_dev_cfg_0"/>
<PERIPHERAL INSTANCE="ps7_xadc_0"/>
<PERIPHERAL INSTANCE="ps7_coresight_comp_0"/>
<PERIPHERAL INSTANCE="ps7_ocmc_0"/>
<PERIPHERAL INSTANCE="ps7_gpv_0"/>
<PERIPHERAL INSTANCE="ps7_scuc_0"/>
<PERIPHERAL INSTANCE="ps7_intc_dist_0"/>
<PERIPHERAL INSTANCE="ps7_globaltimer_0"/>
<PERIPHERAL INSTANCE="ps7_l2cachec_0"/>
<PERIPHERAL INSTANCE="ps7_dma_s"/>
<PERIPHERAL INSTANCE="ps7_iop_bus_config_0"/>
<PERIPHERAL INSTANCE="ps7_ram_0"/>
<PERIPHERAL INSTANCE="ps7_ram_1"/>
<PERIPHERAL INSTANCE="ps7_scugic_0"/>
<PERIPHERAL INSTANCE="ps7_scutimer_0"/>
<PERIPHERAL INSTANCE="ps7_scuwdt_0"/>
<PERIPHERAL INSTANCE="ps7_slcr_0"/>
<PERIPHERAL INSTANCE="ps7_dma_ns"/>
<PERIPHERAL INSTANCE="pwm_recorder_0"/>
<PERIPHERAL INSTANCE="pwm_recorder_1"/>
<PERIPHERAL INSTANCE="pwm_recorder_2"/>
<PERIPHERAL INSTANCE="pwm_recorder_3"/>
<PERIPHERAL INSTANCE="pwm_recorder_4"/>
<PERIPHERAL INSTANCE="pwm_recorder_5"/>
<PERIPHERAL INSTANCE="btns_4bits_tri_io"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_0"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_1"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_2"/>
<PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_3"/>
<PERIPHERAL INSTANCE="axi_timer_0"/>
</PERIPHERALS>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_ddrc_0" IPTYPE="PERIPHERAL" MHS_INDEX="33" MODCLASS="PERIPHERAL" MODTYPE="ps7_ddrc">
<DESCRIPTION TYPE="SHORT">PS7 DDRC</DESCRIPTION>
<DESCRIPTION TYPE="LONG">DDRC interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8006000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8006FFF"/>
<PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_HAS_ECC" TYPE="STRING" VALUE="0"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160774144" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8006000" HIGHDECIMAL="4160778239" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8006FFF" IS_CACHEABLE="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_dev_cfg_0" IPTYPE="PERIPHERAL" MHS_INDEX="34" MODCLASS="PERIPHERAL" MODTYPE="ps7_dev_cfg">
<DESCRIPTION TYPE="SHORT">PS7 DEV CFG</DESCRIPTION>
<DESCRIPTION TYPE="LONG">DEV CFG interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8007000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF80070FF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160778240" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007000" HIGHDECIMAL="4160778495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF80070FF" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_xadc_0" IPTYPE="PERIPHERAL" MHS_INDEX="35" MODCLASS="PERIPHERAL" MODTYPE="ps7_xadc">
<DESCRIPTION TYPE="SHORT">PS7 XADC</DESCRIPTION>
<DESCRIPTION TYPE="LONG">XADC interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8007100"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8007120"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160778496" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007100" HIGHDECIMAL="4160778528" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8007120" MEMTYPE="REGISTER" SIZE="33" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_coresight_comp_0" IPTYPE="PERIPHERAL" MHS_INDEX="36" MODCLASS="PERIPHERAL" MODTYPE="ps7_coresight_comp">
<DESCRIPTION TYPE="SHORT">PS7 coresight component</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 core sight component</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8800000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF88FFFFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4169138176" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8800000" HIGHDECIMAL="4170186751" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF88FFFFF" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_ocmc_0" IPTYPE="PERIPHERAL" MHS_INDEX="37" MODCLASS="PERIPHERAL" MODTYPE="ps7_ocmc">
<DESCRIPTION TYPE="SHORT">PS7 OCMC</DESCRIPTION>
<DESCRIPTION TYPE="LONG">On-chip memory (OCM) interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800C000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800CFFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160798720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800C000" HIGHDECIMAL="4160802815" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800CFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_gpv_0" IPTYPE="PERIPHERAL" MHS_INDEX="38" MODCLASS="PERIPHERAL" MODTYPE="ps7_gpv">
<DESCRIPTION TYPE="SHORT">PS7 GPV</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Top-level interconnect configuration and Global Programmers View (GPV) interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8900000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF89FFFFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4170186752" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8900000" HIGHDECIMAL="4171235327" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF89FFFFF" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_scuc_0" IPTYPE="PERIPHERAL" MHS_INDEX="39" MODCLASS="PERIPHERAL" MODTYPE="ps7_scuc">
<DESCRIPTION TYPE="SHORT">PS7 SCU controler</DESCRIPTION>
<DESCRIPTION TYPE="LONG">SCU control and status</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F000FC"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176478208" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00000" HIGHDECIMAL="4176478460" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F000FC" MEMTYPE="REGISTER" SIZE="253" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_intc_dist_0" IPTYPE="PERIPHERAL" MHS_INDEX="40" MODCLASS="PERIPHERAL" MODTYPE="ps7_intc_dist">
<DESCRIPTION TYPE="SHORT">PS7 intc</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Interrupt controller distributor</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F01000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F01FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176482304" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F01000" HIGHDECIMAL="4176486399" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F01FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_globaltimer_0" IPTYPE="PERIPHERAL" MHS_INDEX="41" MODCLASS="PERIPHERAL" MODTYPE="ps7_globaltimer">
<DESCRIPTION TYPE="SHORT">PS7 global timer</DESCRIPTION>
<DESCRIPTION TYPE="LONG">Global timer</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00200"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F002FF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176478720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00200" HIGHDECIMAL="4176478975" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F002FF" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_l2cachec_0" IPTYPE="PERIPHERAL" MHS_INDEX="42" MODCLASS="PERIPHERAL" MODTYPE="ps7_l2cachec">
<DESCRIPTION TYPE="SHORT">PS7 l2 chache</DESCRIPTION>
<DESCRIPTION TYPE="LONG">L2-cache controller</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F02000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F02FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176486400" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F02000" HIGHDECIMAL="4176490495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F02FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_dma_s" IPTYPE="PERIPHERAL" MHS_INDEX="43" MODCLASS="PERIPHERAL" MODTYPE="ps7_dma">
<DESCRIPTION TYPE="SHORT">PS7 DMA Engine</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8003000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8003FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_LITE_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="1" NAME="s_axi_lite_awvalid" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="2" NAME="s_axi_lite_awready" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="4" NAME="s_axi_lite_wvalid" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="5" NAME="s_axi_lite_wready" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="8" NAME="s_axi_lite_bvalid" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="9" NAME="s_axi_lite_bready" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="10" NAME="s_axi_lite_arvalid" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="s_axi_lite_arready" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="13" NAME="s_axi_lite_rvalid" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_rready" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="17" NAME="mm2s_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="18" NAME="mm2s_cntrl_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="19" NAME="s2mm_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="20" NAME="s2mm_sts_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" MPD_INDEX="21" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="22" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160761856" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8003000" HIGHDECIMAL="4160765951" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8003FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_LITE"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_iop_bus_config_0" IPTYPE="PERIPHERAL" MHS_INDEX="44" MODCLASS="PERIPHERAL" MODTYPE="ps7_iop_bus_config">
<DESCRIPTION TYPE="SHORT">PS7 IOP BUS CONFIG</DESCRIPTION>
<DESCRIPTION TYPE="LONG">IOP BUS CONFIG interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0200000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0200FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="3760193536" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0200000" HIGHDECIMAL="3760197631" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0200FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_ram_0" IPTYPE="PERIPHERAL" MHS_INDEX="45" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_ram">
<DESCRIPTION TYPE="SHORT">PS7 RAM</DESCRIPTION>
<DESCRIPTION TYPE="LONG">RAM interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0002FFFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="1" NAME="S_AXI_HP0" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="S_AXI_HP1" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_HP2" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_HP3" TYPE="SLAVE"/>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="196607" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x0002FFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="196608" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP0"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP1"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP2"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP3"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_ram_1" IPTYPE="PERIPHERAL" MHS_INDEX="46" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_ram">
<DESCRIPTION TYPE="SHORT">PS7 RAM</DESCRIPTION>
<DESCRIPTION TYPE="LONG">RAM interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFF0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="1" NAME="S_AXI_HP0" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="S_AXI_HP1" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_HP2" TYPE="SLAVE"/>
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_HP3" TYPE="SLAVE"/>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4294901760" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFFFF0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="65024" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP0"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP1"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP2"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_HP3"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_scugic_0" IPTYPE="PERIPHERAL" MHS_INDEX="47" MODCLASS="INTERRUPT_CNTLR" MODTYPE="ps7_scugic">
<DESCRIPTION TYPE="SHORT">PS7 SCUGIC0</DESCRIPTION>
<DESCRIPTION TYPE="LONG">SCUGIC0 interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00100"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F001FF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="15" LSB="0" MHS_INDEX="0" MPD_INDEX="19" MSB="15" NAME="IRQ_F2P" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_IRQ_F2P" VECFORMULA="[15:0]">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="Core0_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core0_nFIQ">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="21" NAME="Core0_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core0_nIRQ">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="22" NAME="Core1_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core1_nFIQ">
<CONNECTIONS/>
</PORT>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="23" NAME="Core1_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core1_nIRQ">
<CONNECTIONS/>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176478464" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00100" HIGHDECIMAL="4176478719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F001FF" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_scutimer_0" IPTYPE="PERIPHERAL" MHS_INDEX="48" MODCLASS="PERIPHERAL" MODTYPE="ps7_scutimer">
<DESCRIPTION TYPE="SHORT">PS7 SCU Timer/Counter</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 SCU Timer counter with AXI interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00600"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F0061F"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_1.M_AXI_DP & ps7_cortexa9_0.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176479744" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00600" HIGHDECIMAL="4176479775" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F0061F" MEMTYPE="REGISTER" SIZE="32" SIZEABRV="32">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_scuwdt_0" IPTYPE="PERIPHERAL" MHS_INDEX="49" MODCLASS="PERIPHERAL" MODTYPE="ps7_scuwdt">
<DESCRIPTION TYPE="SHORT">PS7 SCU Watchdog Timer</DESCRIPTION>
<DESCRIPTION TYPE="LONG">PS7 SCU Watchdog Timer with AXI interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00620"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F006FF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4176479776" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00620" HIGHDECIMAL="4176479999" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F006FF" MEMTYPE="REGISTER" SIZE="224" SIZEABRV="U">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_slcr_0" IPTYPE="PERIPHERAL" MHS_INDEX="50" MODCLASS="PERIPHERAL" MODTYPE="ps7_slcr">
<DESCRIPTION TYPE="SHORT">PS7 SLCR</DESCRIPTION>
<DESCRIPTION TYPE="LONG">SLCR interface</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8000FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8000000" HIGHDECIMAL="4160753663" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8000FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="ps7_dma_ns" IPTYPE="PERIPHERAL" MHS_INDEX="51" MODCLASS="PERIPHERAL" MODTYPE="ps7_dma">
<DESCRIPTION TYPE="SHORT">PS7 DMA Engine</DESCRIPTION>
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8004000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8004FFF"/>
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_LITE_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP"/>
</PARAMETERS>
<PORTS>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="1" NAME="s_axi_lite_awvalid" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="2" NAME="s_axi_lite_awready" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="4" NAME="s_axi_lite_wvalid" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="5" NAME="s_axi_lite_wready" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="8" NAME="s_axi_lite_bvalid" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="9" NAME="s_axi_lite_bready" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="10" NAME="s_axi_lite_arvalid" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="s_axi_lite_arready" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="13" NAME="s_axi_lite_rvalid" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_rready" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[32-1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
<CONNECTIONS>
<CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
</CONNECTIONS>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="17" NAME="mm2s_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="18" NAME="mm2s_cntrl_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="19" NAME="s2mm_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="20" NAME="s2mm_sts_reset_out_n" SIGNAME="RESET_OUT_N">
<CONNECTIONS/>
</PORT>
<PORT DIR="O" MPD_INDEX="21" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="O" MPD_INDEX="22" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
</PORTMAPS>
<MASTERS>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
<MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
</MASTERS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="4160765952" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8004000" HIGHDECIMAL="4160770047" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8004FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="S_AXI_LITE"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
</MODULES>
</EDKSYSTEM>