Added clock stop button BTN0

README.md

@@ -56,6 +56,15 @@ fpgagen template  # Set up the transform template for adding a new transform to
 See the configuration file `fpga_config.ini` generated when running `fpgagen` for more information on configuration options
 including changing the default board and Vivado path.
 
+## HELP! I turned off the housekeeping SPI and can't program the board!
+
+On the Arty, hold BTN0, briefly click the RESET button, and while still holding BTN0, you will have access to the housekeeping SPI to reprogram the board.
+Release BTN0 to start your program.
+
+BTN0 is a clock disable button, while it is held, the 10MHz clock will be stopped. The RESET button is the POR reset for the board.
+
+Holding BTN0 while resetting the board will prevent the clock from starting and the MGMT core from disabling the SPI until it is released.
+
 ## Development
 
 To run fpgagen in development mode, from this repository run `python3 -m fpgagen -C path/to/caravel_user_project`.

fpgagen/fpga/arty/fpga_wrapper.v

@@ -60,7 +60,7 @@ module fpga_wrapper(
             reset_delay <= 0;
         else
             reset_delay <= {reset_delay[6:0], por_in};
-    assign resetb = reset_delay[7] & ~reset_in;
+    assign resetb = reset_delay[7];
 
     assign debug = { 4'b1111, 4'b1111, 4'b1111, 4'b1111 };
     
@@ -92,7 +92,7 @@ module fpga_wrapper(
 
         .gpio(gpio),
         .mprj_io(mprj_io),
-        .clock(clock),
+        .clock(clock & ~reset_in),
         .resetb(resetb),
         .flash_csb(flash_csb),
         .flash_clk(flash_clk),

pyproject.toml

 [tool.poetry]
 name = "fpgagen"
-version = "1.1.0"
+version = "1.2.0"
 description = "Generate Vivado FPGA projects for caravel_user_project"
 repository = "https://git.ece.iastate.edu/isu-chip-fab/fpgagen.git"
 authors = ["Gregory Ling"]