Split POR and EXT resets to RESET and BTN0

fpgagen/fpga/arty/Arty-A7-100.xdc

@@ -34,7 +34,7 @@ set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { gpio }
 #set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
 
 ## Buttons
-#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { reset_in }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
 #set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
 #set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
 #set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
@@ -175,7 +175,7 @@ set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { debug[
 
 ## Misc. ChipKit Ports
 #set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
-set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L16P_T2_35 Sch=ck_rst
+set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { por_in }]; #IO_L16P_T2_35 Sch=ck_rst
 
 ## SMSC Ethernet PHY
 #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col

fpgagen/fpga/arty/fpga_wrapper.v

@@ -29,7 +29,8 @@ module fpga_wrapper(
     inout gpio,
     inout [`MPRJ_IO_PADS-1:0] mprj_io,
     input fast_clk100MHz,
-    input resetn,
+    input por_in,
+    input reset_in,
 
     // Note that only two flash data pins are dedicated to the
     // management SoC wrapper.  The management SoC exports the
@@ -51,20 +52,20 @@ module fpga_wrapper(
     wire clock;
     wire resetb;
         
-    assign caravel.chip_core.por.porb_h = resetn;
+    assign caravel.chip_core.por.porb_h = por_in;
 
     reg [7:0] reset_delay;
-    always @(posedge clock or negedge resetn)
-        if (~resetn)
+    always @(posedge clock or negedge por_in)
+        if (~por_in)
             reset_delay <= 0;
         else
-            reset_delay <= {reset_delay[6:0], resetn};
-    assign resetb = reset_delay[7];
+            reset_delay <= {reset_delay[6:0], por_in};
+    assign resetb = reset_delay[7] & ~reset_in;
 
     assign debug = { 4'b1111, 4'b1111, 4'b1111, 4'b1111 };
     
     fpga_clock_divider divider(
-        .RESETn(resetn),
+        .RESETn(por_in),
         .FAST(fast_clk100MHz),
         .SLOW(clock)
     );

pyproject.toml

 [tool.poetry]
 name = "fpgagen"
-version = "1.0.0"
+version = "1.1.0"
 description = "Generate Vivado FPGA projects for caravel_user_project"
 repository = "https://git.ece.iastate.edu/isu-chip-fab/fpgagen.git"
 authors = ["Gregory Ling"]