From e0f9ce98c86674815716107c0d7475f5972e794f Mon Sep 17 00:00:00 2001
From: gling <gling@linux-4.ece.iastate.edu>
Date: Sun, 25 Feb 2024 08:42:26 -0600
Subject: [PATCH] Added clock stop button BTN0
---
README.md | 9 +++++++++
fpgagen/fpga/arty/fpga_wrapper.v | 4 ++--
pyproject.toml | 2 +-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/README.md b/README.md
index e8d94b8..f1232b9 100644
--- a/README.md
+++ b/README.md
@@ -56,6 +56,15 @@ fpgagen template # Set up the transform template for adding a new transform to
See the configuration file `fpga_config.ini` generated when running `fpgagen` for more information on configuration options
including changing the default board and Vivado path.
+## HELP! I turned off the housekeeping SPI and can't program the board!
+
+On the Arty, hold BTN0, briefly click the RESET button, and while still holding BTN0, you will have access to the housekeeping SPI to reprogram the board.
+Release BTN0 to start your program.
+
+BTN0 is a clock disable button, while it is held, the 10MHz clock will be stopped. The RESET button is the POR reset for the board.
+
+Holding BTN0 while resetting the board will prevent the clock from starting and the MGMT core from disabling the SPI until it is released.
+
## Development
To run fpgagen in development mode, from this repository run `python3 -m fpgagen -C path/to/caravel_user_project`.
diff --git a/fpgagen/fpga/arty/fpga_wrapper.v b/fpgagen/fpga/arty/fpga_wrapper.v
index 7a89ed2..35ceec1 100644
--- a/fpgagen/fpga/arty/fpga_wrapper.v
+++ b/fpgagen/fpga/arty/fpga_wrapper.v
@@ -60,7 +60,7 @@ module fpga_wrapper(
reset_delay <= 0;
else
reset_delay <= {reset_delay[6:0], por_in};
- assign resetb = reset_delay[7] & ~reset_in;
+ assign resetb = reset_delay[7];
assign debug = { 4'b1111, 4'b1111, 4'b1111, 4'b1111 };
@@ -92,7 +92,7 @@ module fpga_wrapper(
.gpio(gpio),
.mprj_io(mprj_io),
- .clock(clock),
+ .clock(clock & ~reset_in),
.resetb(resetb),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
diff --git a/pyproject.toml b/pyproject.toml
index 644bc41..75d2d90 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
[tool.poetry]
name = "fpgagen"
-version = "1.1.0"
+version = "1.2.0"
description = "Generate Vivado FPGA projects for caravel_user_project"
repository = "https://git.ece.iastate.edu/isu-chip-fab/fpgagen.git"
authors = ["Gregory Ling"]
--
GitLab