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Commit fe35cc9c authored by James Talbert's avatar James Talbert
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Add PWM Recorder kernel module test 

This exposed a bug that was causing a pulse-width measurement error for clean signals. It now only does a phase shift (for the debounce filter)
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quad/ip_repo/pwm_recorder_1.0/component.xml
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− 13
View file @ fe35cc9c
...@@ -247,7 +247,7 @@ ...@@ -247,7 +247,7 @@
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...@@ -366,6 +366,20 @@ ...@@ -366,6 +366,20 @@
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<spirit:name>xilinx_testbench</spirit:name>
<spirit:displayName>Test Bench</spirit:displayName>
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...@@ -712,7 +726,7 @@ ...@@ -712,7 +726,7 @@
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...@@ -753,6 +767,12 @@ ...@@ -753,6 +767,12 @@
<spirit:name>hdl/pwm_recorder_v1_0.vhd</spirit:name> <spirit:name>hdl/pwm_recorder_v1_0.vhd</spirit:name>
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<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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...@@ -802,6 +822,15 @@ ...@@ -802,6 +822,15 @@
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<spirit:description>Records the incoming pwm signal and assigns to a register</spirit:description> <spirit:description>Records the incoming pwm signal and assigns to a register</spirit:description>
<spirit:parameters> <spirit:parameters>
...@@ -869,20 +898,20 @@ ...@@ -869,20 +898,20 @@
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<xilinx:displayName>pwm_recorder_v1.0</xilinx:displayName> <xilinx:displayName>pwm_recorder_v1.0</xilinx:displayName>
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<xilinx:tags> <xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:pwm_recorder:1.0_ARCHIVE_LOCATION">/local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0</xilinx:tag> <xilinx:tag xilinx:name="user.org:user:pwm_recorder:1.0_ARCHIVE_LOCATION">/local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0</xilinx:tag>
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<xilinx:packagingInfo> <xilinx:packagingInfo>
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quad/ip_repo/pwm_recorder_1.0/hdl/kernel_tester.vhd 0 → 100644
+ 148
− 0
View file @ fe35cc9c
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/27/2018 12:05:17 PM
-- Design Name:
-- Module Name: kernel_tester - testbench
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kernel_tester is
-- Port ( );
end kernel_tester;
architecture testbench of kernel_tester is
component pwm_rec is
port(
clk : in std_logic;
reset_n : in std_logic;
input_signal : in std_logic;
write_o : out std_logic;
count_out : out std_logic_vector(31 downto 0));
end component;
constant CLK_HPER : time := 20 ns;
signal clk : std_logic;
signal pwm : std_logic;
signal reset_n : std_logic;
signal count : std_logic_vector(31 downto 0);
signal write : std_logic;
signal done : std_logic := '0';
begin
UUT: pwm_rec
port map(
clk => clk,
reset_n => reset_n,
input_signal => pwm,
write_o => write,
count_out => count);
test_process: process
variable period : integer;
begin
reset_n <='0';
wait for 2*CLK_HPER;
reset_n <='1';
period := 100;
pwm <= '0';
wait for CLK_HPER*2*20;
pwm <= '1';
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
period := 200;
pwm <= '0';
wait for CLK_HPER*2*20;
pwm <= '1';
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
period := 300;
pwm <= '0';
wait for CLK_HPER*2*20;
pwm <= '1';
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
period := 400;
pwm <= '0';
wait for CLK_HPER*2*20;
pwm <= '1';
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
period := 10;
pwm <= '0';
wait for CLK_HPER*2*20;
pwm <= '1';
wait for period*2*CLK_HPER;
pwm <= '0';
for t in 0 to 100 loop
wait for 2*CLK_HPER;
ASSERT write='0' REPORT "Glitch not Ignored" SEVERITY FAILURE;
end loop;
-- Run for 45, glitch for 10, then run for 45, expect a result of 100
period := 100;
pwm <= '0';
wait for CLK_HPER*2*20;
pwm <= '1';
wait for 45*2*CLK_HPER;
pwm <= '0';
wait for 10*2*CLK_HPER;
pwm <= '1';
wait for 45*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
done <='1';
wait;
end process;
clock_proc: process
begin
clk <= '0';
wait for CLK_HPER;
clk <= '1';
wait for CLK_HPER;
if (done = '1') then wait; end if;
end process;
end testbench;
quad/ip_repo/pwm_recorder_1.0/src/pwm_rec.vhd
+ 8
− 0
View file @ fe35cc9c
...@@ -62,6 +62,14 @@ begin ...@@ -62,6 +62,14 @@ begin
counter <= x"00000000"; counter <= x"00000000";
current <= '0'; current <= '0';
write_o <= '0'; write_o <= '0';
-- Neither all high or all low
elsif (current = '1') then
current <= '1';
counter <= counter + 1;
write_o <= '0';
end if; end if;
end if; end if;
end process; end process;
......
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