Integrate hw simulation into the unit tests

ci/ci-build.sh

@@ -2,9 +2,13 @@
 
 set -e
 
+# Quad Hardware Tests
+source /remote/Xilinx/2018.2/Vivado/2018.2/settings64.sh
+(cd quad/ip_repo && make build-tests)
+
 # Quad Libraries and Boot image
-(cd quad && make deep-clean && make)
+#(cd quad && make deep-clean && make)
 
 # Ground station
-git submodule update --init --recursive
+#git submodule update --init --recursive
 #(cd groundStation && make vrpn && make) # QT is breaking things right now

ci/ci-test.sh

@@ -2,5 +2,8 @@
 
 set -e
 
+# Quad HW
+(cd quad/ip_repo && make run-tests)
+
 # Quad
-(cd quad && make test)
+#(cd quad && make test)

quad/ip_repo/Makefile

+build-tests: 
+	(cd pwm_recorder_1.0/ && make build-tests)
+
+run-tests:
+	(cd pwm_recorder_1.0/ && make run-tests)
\ No newline at end of file

quad/ip_repo/pwm_recorder_1.0/Makefile

+build-tests:
+	xelab --debug wave -prj kernel_test.prj -s run_kernel_test work.kernel_tester
+
+run-tests:
+	xsim run_kernel_test -wdb pwm_record_kernel_test.wdb --t get_simulation_result.tcl
+	echo 1 > result.exp
+	cmp result.log result.exp
+	rm result.exp
\ No newline at end of file

quad/ip_repo/pwm_recorder_1.0/get_simulation_result.tcl

@@ -3,4 +3,5 @@ set signal [get_objects /*_tester/passing]
 set fd [open "result.log" "w"]
 run all
 puts $fd [get_value $signal]
+flush $fd
 quit
\ No newline at end of file

quad/ip_repo/pwm_recorder_1.0/hdl/kernel_tester.vhd

@@ -154,7 +154,7 @@ begin
         end if;
         
         done <='1';
-        
+                        
         if (passing = '0') then
             -- output test faulure?
         end if;