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Commit 171fda11 authored by James Talbert's avatar James Talbert
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Setup vivado scripts for automated testing

parent f4b890b9
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#!/bin/bash
set signal [get_objects /*_tester/passing]
set fd [open "result.log" "w"]
run all
puts $fd [get_value $signal]
quit
\ No newline at end of file
......@@ -53,6 +53,7 @@ architecture testbench of kernel_tester is
signal count : std_logic_vector(31 downto 0);
signal write : std_logic;
signal done : std_logic := '0';
signal passing : std_logic := '0';
begin
UUT: pwm_rec
......@@ -67,6 +68,8 @@ begin
variable period : integer;
begin
passing <='1';
reset_n <='0';
wait for 2*CLK_HPER;
reset_n <='1';
......@@ -78,7 +81,10 @@ begin
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
if (count /= std_logic_vector(to_unsigned(period, 32))) then
REPORT "Incorrect COUNT result" SEVERITY FAILURE;
passing <='0';
end if;
period := 200;
pwm <= '0';
......@@ -87,8 +93,11 @@ begin
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
if (count /= std_logic_vector(to_unsigned(period, 32))) then
REPORT "Incorrect COUNT result" SEVERITY FAILURE;
passing <='0';
end if;
period := 300;
pwm <= '0';
wait for CLK_HPER*2*20;
......@@ -96,7 +105,10 @@ begin
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
if (count /= std_logic_vector(to_unsigned(period, 32))) then
REPORT "Incorrect COUNT result" SEVERITY FAILURE;
passing <='0';
end if;
period := 400;
pwm <= '0';
......@@ -105,7 +117,10 @@ begin
wait for period*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
if (count /= std_logic_vector(to_unsigned(period, 32))) then
REPORT "Incorrect COUNT result" SEVERITY FAILURE;
passing <='0';
end if;
period := 10;
pwm <= '0';
......@@ -115,7 +130,10 @@ begin
pwm <= '0';
for t in 0 to 100 loop
wait for 2*CLK_HPER;
ASSERT write='0' REPORT "Glitch not Ignored" SEVERITY FAILURE;
if (write /= '0') then
REPORT "Glitch not Ignored" SEVERITY FAILURE;
passing <='0';
end if;
end loop;
-- Run for 45, glitch for 10, then run for 45, expect a result of 100
......@@ -130,12 +148,20 @@ begin
wait for 45*2*CLK_HPER;
pwm <= '0';
wait until write='1';
ASSERT count=std_logic_vector(to_unsigned(period, 32)) REPORT "Incorrect COUNT result" SEVERITY FAILURE;
if (count /= std_logic_vector(to_unsigned(period, 32))) then
REPORT "Incorrect COUNT result" SEVERITY FAILURE;
passing <='0';
end if;
done <='1';
if (passing = '0') then
-- output test faulure?
end if;
wait;
end process;
clock_proc: process
begin
clk <= '0';
......
vhdl work src/pwm_rec.vhd
vhdl work hdl/kernel_tester.vhd
#!/bin/bash
xelab --debug wave -prj kernel_test.prj -s run_kernel_test work.kernel_tester
xsim run_kernel_test -wdb pwm_record_kernel_test.wdb --t get_simulation_result.tcl
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