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Commit 4c6fe832 authored by mkelly2's avatar mkelly2
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Added project tcl for a simple zybo project

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quad/vivado_workspace/Zybo-Z7-Master.xdc 0 → 100644
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View file @ 4c6fe832
## This file is a general .xdc for the Zybo Z7 Rev. B
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
##Clock signal
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
##Switches
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
##Buttons
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
##LEDs
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
##RGB LED 5 (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
##RGB LED 6
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
##Audio Codec
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
##Additional Ethernet signals
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
##USB-OTG over-current detect pin
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
##Fan (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
##HDMI RX
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
##HDMI RX CEC (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
##HDMI TX
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
##HDMI TX CEC
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
##Pmod Header JA (XADC)
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
##Pmod Header JB (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
##Pmod Header JC
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
##Pmod Header JD
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
##Pcam MIPI CSI-2 Connector
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
##Unloaded Crypto Chip SWI (for future use)
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
##Unconnected Pins (Zybo Z7-20 only)
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
quad/vivado_workspace/vivado-boards-master/README.md 0 → 100644
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# vivado-boards
This repository contains the board files used by Vivado to add support for Digilent system boards.
The old folder is for use with Vivado versions 14.4 and below. The new folder covers Vivado 15.x and above
For instructions on how to install these files, the following wiki page can be used.
https://reference.digilentinc.com/vivado:boardfiles
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/mig.prj 0 → 100644
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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>design_1_mig_7series_0_0</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
<Version>2.3</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3000</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>166.666</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>666</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.35V</MemoryVoltage>
<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >5</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/part0_pins.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7a100tcsg324-1L">
<pins>
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
</pins>
</part_info>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/preset.xml 0 → 100644
+ 385
− 0
View file @ 4c6fe832
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ip_presets schema="1.0">
<ip_preset preset_proc_name="ddr3_sdram_preset">
<ip vendor="xilinx.com" library="ip" name="mig_7series">
<user_parameters>
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="qspi_preset">
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
<user_parameters>
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="spi_preset">
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
<user_parameters>
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="output_2bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="dip_switches_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="push_buttons_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="output_12bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="led_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="mii_preset">
<ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
<user_parameters>
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
<user_parameters>
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="uart_preset">
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="sys_clock_preset">
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
<user_parameters>
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
<user_parameters>
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
</ip_preset>
</ip_presets>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/mig.prj 0 → 100644
+ 134
− 0
View file @ 4c6fe832
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>design_1_mig_7series_0_0</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
<Version>2.3</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3000</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>166.666</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>666</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.35V</MemoryVoltage>
<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >5</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/part0_pins.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7a35tcsg324-1L">
<pins>
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
</pins>
</part_info>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/preset.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ip_presets schema="1.0">
<ip_preset preset_proc_name="ddr3_sdram_preset">
<ip vendor="xilinx.com" library="ip" name="mig_7series">
<user_parameters>
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="qspi_preset">
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
<user_parameters>
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="spi_preset">
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
<user_parameters>
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="output_2bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="dip_switches_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="push_buttons_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="output_12bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="led_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="mii_preset">
<ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
<user_parameters>
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
<user_parameters>
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="uart_preset">
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="sys_clock_preset">
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
<user_parameters>
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
<user_parameters>
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
</ip_preset>
</ip_presets>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/mig.prj 0 → 100644
+ 138
− 0
View file @ 4c6fe832
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>system_mig_7series_0_2</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7s25-csga324/-1</TargetFPGA>
<Version>4.0</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3077</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>99.997</InputClkFreq>
<UIExtraClocks>1</UIExtraClocks>
<MMCM_VCO>649</MMCM_VCO>
<MMCMClkOut0> 3.250</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.35V</MemoryVoltage>
<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R4" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V2" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V3" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="T4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="R5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T2" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P1" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L5" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="L1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="K1" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N3" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="J6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P7" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="R2" Bank="34" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >5</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7s25csga324-1">
<pins>
<pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
<pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
<pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
<pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
<pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
<pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
<pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
<pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
<pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
<pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
<pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
<pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
<pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
<pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
<pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
<pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
<pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
<pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
<pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
<pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
<pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
<pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
<pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
<pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
<pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
<pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
<pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
<pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
<pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
<pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
<pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
<pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
<pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
<pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
<pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
<pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
<pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
<pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
<pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
<pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
<pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
<pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
<pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
<pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
<pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
<pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
<pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
<pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
<pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
<pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
<pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
<pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
<pin index="52" name ="JA1" iostandard="LVCMOS33" loc="L17"/>
<pin index="53" name ="JA2" iostandard="LVCMOS33" loc="L18"/>
<pin index="54" name ="JA3" iostandard="LVCMOS33" loc="M14"/>
<pin index="55" name ="JA4" iostandard="LVCMOS33" loc="N14"/>
<pin index="56" name ="JA7" iostandard="LVCMOS33" loc="M16"/>
<pin index="57" name ="JA8" iostandard="LVCMOS33" loc="M17"/>
<pin index="58" name ="JA9" iostandard="LVCMOS33" loc="M18"/>
<pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
<pin index="60" name ="JB1" iostandard="LVCMOS33" loc="P17"/>
<pin index="61" name ="JB2" iostandard="LVCMOS33" loc="P18"/>
<pin index="62" name ="JB3" iostandard="LVCMOS33" loc="R18"/>
<pin index="63" name ="JB4" iostandard="LVCMOS33" loc="T18"/>
<pin index="64" name ="JB7" iostandard="LVCMOS33" loc="P14"/>
<pin index="65" name ="JB8" iostandard="LVCMOS33" loc="P15"/>
<pin index="66" name ="JB9" iostandard="LVCMOS33" loc="N15"/>
<pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
<pin index="68" name ="JC1" iostandard="LVCMOS33" loc="U15"/>
<pin index="69" name ="JC2" iostandard="LVCMOS33" loc="V16"/>
<pin index="70" name ="JC3" iostandard="LVCMOS33" loc="U17"/>
<pin index="71" name ="JC4" iostandard="LVCMOS33" loc="U18"/>
<pin index="72" name ="JC7" iostandard="LVCMOS33" loc="U16"/>
<pin index="73" name ="JC8" iostandard="LVCMOS33" loc="P13"/>
<pin index="74" name ="JC9" iostandard="LVCMOS33" loc="R13"/>
<pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
<pin index="76" name ="JD1" iostandard="LVCMOS33" loc="V15"/>
<pin index="77" name ="JD2" iostandard="LVCMOS33" loc="U12"/>
<pin index="78" name ="JD3" iostandard="LVCMOS33" loc="V13"/>
<pin index="79" name ="JD4" iostandard="LVCMOS33" loc="T12"/>
<pin index="80" name ="JD7" iostandard="LVCMOS33" loc="T13"/>
<pin index="81" name ="JD8" iostandard="LVCMOS33" loc="R11"/>
<pin index="82" name ="JD9" iostandard="LVCMOS33" loc="T11"/>
<pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
</pins>
</part_info>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ip_presets schema="1.0">
<ip_preset preset_proc_name="ddr3_sdram_preset">
<ip vendor="xilinx.com" library="ip" name="mig_7series">
<user_parameters>
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="qspi_preset">
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
<user_parameters>
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="spi_preset">
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
<user_parameters>
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="dip_switches_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="push_buttons_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="output_6bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="led_4bits_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
<user_parameters>
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_dp0_dp9_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_a0_a5_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="shield_a10_a11_preset">
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
<user_parameters>
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="uart_preset">
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
<user_parameters>
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="ddr_clock_preset">
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
<user_parameters>
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
<user_parameters>
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
</ip_preset>
<ip_preset preset_proc_name="sys_clock_preset">
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
<user_parameters>
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
<user_parameters>
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
</user_parameters>
</ip>
</ip_preset>
</ip_presets>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/mig.prj 0 → 100644
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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>system_mig_7series_0_2</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7s50-csga324/-1</TargetFPGA>
<Version>4.0</Version>
<SystemClock>Single-Ended</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3077</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>99.997</InputClkFreq>
<UIExtraClocks>1</UIExtraClocks>
<MMCM_VCO>649</MMCM_VCO>
<MMCMClkOut0> 3.250</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.35V</MemoryVoltage>
<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R4" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V2" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V3" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="T4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="R5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T2" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P1" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L5" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="L1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="K1" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N3" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="J6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P7" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="R2" Bank="34" name="sys_clk_i" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >5</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml 0 → 100644
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− 0
View file @ 4c6fe832
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7s50csga324-1">
<pins>
<pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
<pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
<pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
<pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
<pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
<pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
<pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
<pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
<pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
<pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
<pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
<pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
<pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
<pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
<pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
<pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
<pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
<pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
<pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
<pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
<pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
<pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
<pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
<pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
<pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
<pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
<pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
<pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
<pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
<pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
<pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
<pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
<pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
<pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
<pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
<pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
<pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
<pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
<pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
<pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
<pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
<pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
<pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
<pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
<pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
<pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
<pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
<pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
<pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
<pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
<pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
<pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
<pin index="52" name ="JA1" iostandard="LVCMOS33" loc="L17"/>
<pin index="53" name ="JA2" iostandard="LVCMOS33" loc="L18"/>
<pin index="54" name ="JA3" iostandard="LVCMOS33" loc="M14"/>
<pin index="55" name ="JA4" iostandard="LVCMOS33" loc="N14"/>
<pin index="56" name ="JA7" iostandard="LVCMOS33" loc="M16"/>
<pin index="57" name ="JA8" iostandard="LVCMOS33" loc="M17"/>
<pin index="58" name ="JA9" iostandard="LVCMOS33" loc="M18"/>
<pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
<pin index="60" name ="JB1" iostandard="LVCMOS33" loc="P17"/>
<pin index="61" name ="JB2" iostandard="LVCMOS33" loc="P18"/>
<pin index="62" name ="JB3" iostandard="LVCMOS33" loc="R18"/>
<pin index="63" name ="JB4" iostandard="LVCMOS33" loc="T18"/>
<pin index="64" name ="JB7" iostandard="LVCMOS33" loc="P14"/>
<pin index="65" name ="JB8" iostandard="LVCMOS33" loc="P15"/>
<pin index="66" name ="JB9" iostandard="LVCMOS33" loc="N15"/>
<pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
<pin index="68" name ="JC1" iostandard="LVCMOS33" loc="U15"/>
<pin index="69" name ="JC2" iostandard="LVCMOS33" loc="V16"/>
<pin index="70" name ="JC3" iostandard="LVCMOS33" loc="U17"/>
<pin index="71" name ="JC4" iostandard="LVCMOS33" loc="U18"/>
<pin index="72" name ="JC7" iostandard="LVCMOS33" loc="U16"/>
<pin index="73" name ="JC8" iostandard="LVCMOS33" loc="P13"/>
<pin index="74" name ="JC9" iostandard="LVCMOS33" loc="R13"/>
<pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
<pin index="76" name ="JD1" iostandard="LVCMOS33" loc="V15"/>
<pin index="77" name ="JD2" iostandard="LVCMOS33" loc="U12"/>
<pin index="78" name ="JD3" iostandard="LVCMOS33" loc="V13"/>
<pin index="79" name ="JD4" iostandard="LVCMOS33" loc="T12"/>
<pin index="80" name ="JD7" iostandard="LVCMOS33" loc="T13"/>
<pin index="81" name ="JD8" iostandard="LVCMOS33" loc="R11"/>
<pin index="82" name ="JD9" iostandard="LVCMOS33" loc="T11"/>
<pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
</pins>
</part_info>
quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<part_info part_name="xc7z010clg400-1">
<pins>
<pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
<pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
<pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
<pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
<pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
<pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
<pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
<pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
<pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
<pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
<pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
<pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
<pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
<pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
<pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
<pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
<pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
<pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
<pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
<pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
<pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
<pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
<pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
<pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
<pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
<pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
<pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
<pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
<pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
<pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
<pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
<pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
<pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
<pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
<pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
<pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
<pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
<pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
<pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
<pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
<pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
<pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
<pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
<pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
<pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
<pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
<pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
<pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
<pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
<pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
<pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
<pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
<pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
</pins>
</part_info>
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