From 4c6fe8327c7728d5458a05aa9a6923e99219b716 Mon Sep 17 00:00:00 2001
From: Matthew Kelly <mkelly2@iastate.edu>
Date: Thu, 20 Sep 2018 14:25:38 -0500
Subject: [PATCH] Added project tcl for a simple zybo project
---
quad/vivado_workspace/Zybo-Z7-Master.xdc | 198 ++
.../vivado-boards-master/README.md | 8 +
.../new/board_files/arty-a7-100/E.0/board.xml | 1287 +++++++++++++
.../new/board_files/arty-a7-100/E.0/mig.prj | 134 ++
.../arty-a7-100/E.0/part0_pins.xml | 133 ++
.../board_files/arty-a7-100/E.0/preset.xml | 385 ++++
.../new/board_files/arty-a7-35/E.0/board.xml | 1287 +++++++++++++
.../new/board_files/arty-a7-35/E.0/mig.prj | 134 ++
.../board_files/arty-a7-35/E.0/part0_pins.xml | 133 ++
.../new/board_files/arty-a7-35/E.0/preset.xml | 385 ++++
.../new/board_files/arty-s7-25/E.0/board.xml | 1113 +++++++++++
.../new/board_files/arty-s7-25/E.0/mig.prj | 138 ++
.../board_files/arty-s7-25/E.0/part0_pins.xml | 89 +
.../new/board_files/arty-s7-25/E.0/preset.xml | 394 ++++
.../new/board_files/arty-s7-50/B.0/board.xml | 1113 +++++++++++
.../new/board_files/arty-s7-50/B.0/mig.prj | 138 ++
.../board_files/arty-s7-50/B.0/part0_pins.xml | 89 +
.../new/board_files/arty-s7-50/B.0/preset.xml | 394 ++++
.../new/board_files/arty-z7-10/A.0/board.xml | 601 ++++++
.../board_files/arty-z7-10/A.0/part0_pins.xml | 58 +
.../new/board_files/arty-z7-10/A.0/preset.xml | 1080 +++++++++++
.../new/board_files/arty-z7-20/A.0/board.xml | 674 +++++++
.../board_files/arty-z7-20/A.0/part0_pins.xml | 74 +
.../new/board_files/arty-z7-20/A.0/preset.xml | 1098 +++++++++++
.../new/board_files/arty/C.0/board.xml | 1287 +++++++++++++
.../new/board_files/arty/C.0/mig.prj | 134 ++
.../new/board_files/arty/C.0/part0_pins.xml | 133 ++
.../new/board_files/arty/C.0/preset.xml | 385 ++++
.../new/board_files/basys3/C.0/board.xml | 844 +++++++++
.../new/board_files/basys3/C.0/part0_pins.xml | 94 +
.../new/board_files/basys3/C.0/preset.xml | 313 ++++
.../new/board_files/cmod-s7-25/B.0/board.xml | 426 +++++
.../board_files/cmod-s7-25/B.0/part0_pins.xml | 37 +
.../new/board_files/cmod-s7-25/B.0/preset.xml | 307 +++
.../new/board_files/cmod_a7-15t/B.0/board.xml | 481 +++++
.../cmod_a7-15t/B.0/part0_pins.xml | 58 +
.../board_files/cmod_a7-15t/B.0/preset.xml | 270 +++
.../new/board_files/cmod_a7-35t/B.0/board.xml | 481 +++++
.../cmod_a7-35t/B.0/part0_pins.xml | 58 +
.../board_files/cmod_a7-35t/B.0/preset.xml | 270 +++
.../new/board_files/cora-z7-07s/B.0/board.xml | 688 +++++++
.../cora-z7-07s/B.0/part0_pins.xml | 90 +
.../board_files/cora-z7-07s/B.0/preset.xml | 590 ++++++
.../new/board_files/cora-z7-10/B.0/board.xml | 688 +++++++
.../board_files/cora-z7-10/B.0/part0_pins.xml | 90 +
.../new/board_files/cora-z7-10/B.0/preset.xml | 590 ++++++
.../new/board_files/genesys2/H/board.xml | 1643 +++++++++++++++++
.../new/board_files/genesys2/H/mig.prj | 160 ++
.../new/board_files/genesys2/H/part0_pins.xml | 141 ++
.../new/board_files/genesys2/H/preset.xml | 312 ++++
.../new/board_files/nexys4/B.1/board.xml | 1563 ++++++++++++++++
.../new/board_files/nexys4/B.1/part0_pins.xml | 184 ++
.../new/board_files/nexys4/B.1/preset.xml | 373 ++++
.../new/board_files/nexys4_ddr/C.1/board.xml | 1455 +++++++++++++++
.../new/board_files/nexys4_ddr/C.1/mig.prj | 128 ++
.../board_files/nexys4_ddr/C.1/part0_pins.xml | 139 ++
.../new/board_files/nexys4_ddr/C.1/preset.xml | 363 ++++
.../new/board_files/nexys_video/A.0/board.xml | 1332 +++++++++++++
.../new/board_files/nexys_video/A.0/mig.prj | 133 ++
.../nexys_video/A.0/part0_pins.xml | 116 ++
.../board_files/nexys_video/A.0/preset.xml | 322 ++++
.../new/board_files/sword/C.0/board.xml | 1057 +++++++++++
.../new/board_files/sword/C.0/mig.prj | 159 ++
.../new/board_files/sword/C.0/part0_pins.xml | 126 ++
.../new/board_files/sword/C.0/preset.xml | 408 ++++
.../new/board_files/zedboard/1.3/board.xml | 812 ++++++++
.../board_files/zedboard/1.3/part0_pins.xml | 67 +
.../new/board_files/zedboard/1.3/preset.xml | 295 +++
.../board_files/zedboard/1.3/zed_board.jpg | Bin 0 -> 69596 bytes
.../new/board_files/zybo-z7-10/A.0/board.xml | 861 +++++++++
.../board_files/zybo-z7-10/A.0/part0_pins.xml | 83 +
.../new/board_files/zybo-z7-10/A.0/preset.xml | 667 +++++++
.../new/board_files/zybo-z7-20/A.0/board.xml | 994 ++++++++++
.../board_files/zybo-z7-20/A.0/part0_pins.xml | 99 +
.../new/board_files/zybo-z7-20/A.0/preset.xml | 667 +++++++
.../new/board_files/zybo/B.3/board.xml | 937 ++++++++++
.../new/board_files/zybo/B.3/part0_pins.xml | 70 +
.../new/board_files/zybo/B.3/preset.xml | 414 +++++
.../artix7/arty/C.0/board_part.xml | 704 +++++++
.../old/board_parts/artix7/arty/C.0/mig.prj | 134 ++
.../old/board_parts/artix7/arty/desktop.ini | 4 +
.../artix7/basys3/1.1/board_part.xml | 295 +++
.../artix7/nexys4/1.1/board_part.xml | 654 +++++++
.../artix7/nexys4_ddr/1.1/board_part.xml | 539 ++++++
.../board_parts/artix7/nexys4_ddr/1.1/mig.prj | 127 ++
.../kintex7/genesys2/H/board_part.xml | 766 ++++++++
.../board_parts/kintex7/genesys2/H/mig.prj | 160 ++
.../board_parts/zynq/zybo/1.0/board_part.xml | 69 +
.../old/board_parts/zynq/zybo/1.0/ps7.tcl | 4 +
.../utility/Vivado_init.tcl | 1 +
.../vivado-boards-master/utility/init.tcl | 1 +
.../vivado_workspace/Zybo-Z7-Master.xdc | 198 ++
.../bd/design_1/hdl/design_1_wrapper.vhd | 256 +++
93 files changed, 39443 insertions(+)
create mode 100644 quad/vivado_workspace/Zybo-Z7-Master.xdc
create mode 100644 quad/vivado_workspace/vivado-boards-master/README.md
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/zed_board.jpg
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/board.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/preset.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/mig.prj
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml
create mode 100644 quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl
create mode 100644 quad/vivado_workspace/vivado-boards-master/utility/Vivado_init.tcl
create mode 100644 quad/vivado_workspace/vivado-boards-master/utility/init.tcl
create mode 100644 quad/vivado_workspace/zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc
create mode 100644 quad/vivado_workspace/zybo_blank/zybo_blank.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
diff --git a/quad/vivado_workspace/Zybo-Z7-Master.xdc b/quad/vivado_workspace/Zybo-Z7-Master.xdc
new file mode 100644
index 000000000..9e6546e42
--- /dev/null
+++ b/quad/vivado_workspace/Zybo-Z7-Master.xdc
@@ -0,0 +1,198 @@
+## This file is a general .xdc for the Zybo Z7 Rev. B
+## It is compatible with the Zybo Z7-20 and Zybo Z7-10
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+##Clock signal
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
+
+
+##LEDs
+#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
+#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
+#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
+#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
+
+
+##RGB LED 5 (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
+#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
+#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
+
+##RGB LED 6
+#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
+#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
+#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
+
+
+##Audio Codec
+#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
+#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
+#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
+#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
+#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
+#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
+#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
+#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
+#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
+
+
+##USB-OTG over-current detect pin
+#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
+
+
+##Fan (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
+
+
+##HDMI RX
+#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
+#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
+
+##HDMI RX CEC (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
+
+
+##HDMI TX
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
+
+##HDMI TX CEC
+#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+
+
+##Pmod Header JB (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
+#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
+#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
+#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
+#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
+#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
+#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
+#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
+#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
+#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
+#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
+#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
+
+
+##Pcam MIPI CSI-2 Connector
+## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
+#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
+#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
+#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
+#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
+#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
+#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
+#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
+#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
+#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
+#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
+#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
+#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
+#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
+#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
+#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
+#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
+
+
+##Unloaded Crypto Chip SWI (for future use)
+#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
+
+
+##Unconnected Pins (Zybo Z7-20 only)
+#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
+#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
+#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
+#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
+#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
+#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
+#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
+#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
+#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
+#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
+#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
+#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
+
+
diff --git a/quad/vivado_workspace/vivado-boards-master/README.md b/quad/vivado_workspace/vivado-boards-master/README.md
new file mode 100644
index 000000000..a53defd62
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/README.md
@@ -0,0 +1,8 @@
+# vivado-boards
+
+This repository contains the board files used by Vivado to add support for Digilent system boards.
+The old folder is for use with Vivado versions 14.4 and below. The new folder covers Vivado 15.x and above
+
+For instructions on how to install these files, the following wiki page can be used.
+
+https://reference.digilentinc.com/vivado:boardfiles
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/board.xml
new file mode 100644
index 000000000..e05a096ce
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/board.xml
@@ -0,0 +1,1287 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-100" display_name="Arty A7-100" url="www.digilentinc.com/Arty-A7-100" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty A7-100</description>
+<components>
+ <component name="part0" display_name="Arty A7-100" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/Arty-A7-100"> <!--CONFIRM URL-->
+ <interfaces>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+ <description>4-position user DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+ <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_txd_0"/>
+ <pin_map port_index="1" component_pin="eth_txd_1"/>
+ <pin_map port_index="2" component_pin="eth_txd_2"/>
+ <pin_map port_index="3" component_pin="eth_txd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rxd_0"/>
+ <pin_map port_index="1" component_pin="eth_rxd_1"/>
+ <pin_map port_index="2" component_pin="eth_rxd_2"/>
+ <pin_map port_index="3" component_pin="eth_rxd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_dv"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_er"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_crs"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="COL" physical_port="eth_col" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_col"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rstn"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+ <description>I2C Pullups to enable shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+ <description>4 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_4bits_tri_t" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+ <description>4 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <parameters>
+ <parameter name="rst_polarity" value="0"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+ <description>4 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_i" dir="in" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_t" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>256 MB DDR3L memory SODIMM </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="256MB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>PHY Ethernet on the board</description>
+ <component_modes>
+ <component_mode name="mii" display_name="MII mode">
+ <interfaces>
+ <interface name="eth_mii" order="0"/>
+ <interface name="eth_mdio_mdc" order="1" optional="true"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+ <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+ </component>
+ <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 3 to 0</description>
+ </component>
+ <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+ <description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+ </component>
+ <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+ <description>CPU Reset Push Button, active low</description>
+ </component>
+ <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 12 to 0 (3 per LED)</description>
+ </component>
+ <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 0 through 19</description>
+ </component>
+ <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 26 through 41</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+</components>
+
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+ <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+ <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+ <connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+ <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+ <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+ <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+ <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+ </connection>
+ <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+ <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/mig.prj
new file mode 100644
index 000000000..1bff709e8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/mig.prj
@@ -0,0 +1,134 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
+ <Version>2.3</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>No Buffer</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+ <TimePeriod>3000</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>166.666</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>666</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.35V</MemoryVoltage>
+ <C0_MEM_SIZE>268435456</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/part0_pins.xml
new file mode 100644
index 000000000..5b5580d3b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/part0_pins.xml
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a100tcsg324-1L">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+ <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+ <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+ <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+ <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+ <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+ <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+ <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+ <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+ <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+ <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+ <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+ <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+ <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+ <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+ <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+ <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+ <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+ <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+ <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+ <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+ <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+ <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+ <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+ <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+ <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+ <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+ <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+ <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+ <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+ <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+ <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+ <pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
+ <pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
+ <pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
+ <pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
+ <pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
+ <pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
+ <pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
+ <pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
+ <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
+ <pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
+ <pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
+ <pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
+ <pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
+ <pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
+ <pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
+ <pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
+ <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/preset.xml
new file mode 100644
index 000000000..df58104e8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-100/E.0/preset.xml
@@ -0,0 +1,385 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_12bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="mii_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.Physical_Interface" value="MII"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/board.xml
new file mode 100644
index 000000000..12eb9ac66
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/board.xml
@@ -0,0 +1,1287 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-35" display_name="Arty A7-35" url="www.digilentinc.com/Arty-A7-35" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty A7-35</description>
+<components>
+ <component name="part0" display_name="Arty A7-35" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/Arty-A7-35"> <!--CONFIRM URL-->
+ <interfaces>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+ <description>4-position user DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+ <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_txd_0"/>
+ <pin_map port_index="1" component_pin="eth_txd_1"/>
+ <pin_map port_index="2" component_pin="eth_txd_2"/>
+ <pin_map port_index="3" component_pin="eth_txd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rxd_0"/>
+ <pin_map port_index="1" component_pin="eth_rxd_1"/>
+ <pin_map port_index="2" component_pin="eth_rxd_2"/>
+ <pin_map port_index="3" component_pin="eth_rxd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_dv"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_er"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_crs"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="COL" physical_port="eth_col" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_col"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rstn"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+ <description>I2C Pullups to enable shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+ <description>4 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_4bits_tri_t" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+ <description>4 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <parameters>
+ <parameter name="rst_polarity" value="0"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+ <description>4 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_i" dir="in" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_t" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>256 MB DDR3L memory SODIMM </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="256MB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>PHY Ethernet on the board</description>
+ <component_modes>
+ <component_mode name="mii" display_name="MII mode">
+ <interfaces>
+ <interface name="eth_mii" order="0"/>
+ <interface name="eth_mdio_mdc" order="1" optional="true"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+ <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+ </component>
+ <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 3 to 0</description>
+ </component>
+ <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+ <description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+ </component>
+ <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+ <description>CPU Reset Push Button, active low</description>
+ </component>
+ <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 12 to 0 (3 per LED)</description>
+ </component>
+ <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 0 through 19</description>
+ </component>
+ <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 26 through 41</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+</components>
+
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+ <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+ <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+ <connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+ <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+ <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+ <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+ <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+ </connection>
+ <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+ <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/mig.prj
new file mode 100644
index 000000000..9b31d7bc8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/mig.prj
@@ -0,0 +1,134 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
+ <Version>2.3</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>No Buffer</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+ <TimePeriod>3000</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>166.666</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>666</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.35V</MemoryVoltage>
+ <C0_MEM_SIZE>268435456</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/part0_pins.xml
new file mode 100644
index 000000000..ffe0dd45b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/part0_pins.xml
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a35tcsg324-1L">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+ <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+ <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+ <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+ <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+ <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+ <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+ <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+ <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+ <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+ <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+ <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+ <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+ <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+ <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+ <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+ <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+ <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+ <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+ <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+ <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+ <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+ <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+ <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+ <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+ <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+ <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+ <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+ <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+ <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+ <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+ <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+ <pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
+ <pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
+ <pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
+ <pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
+ <pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
+ <pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
+ <pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
+ <pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
+ <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
+ <pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
+ <pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
+ <pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
+ <pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
+ <pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
+ <pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
+ <pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
+ <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/preset.xml
new file mode 100644
index 000000000..df58104e8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-a7-35/E.0/preset.xml
@@ -0,0 +1,385 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_12bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="mii_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.Physical_Interface" value="MII"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml
new file mode 100644
index 000000000..cdfc612ad
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/board.xml
@@ -0,0 +1,1113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-25" display_name="Arty S7-25" url="http://store.digilentinc.com/preview-arty-s7-spartan-7-fpga-for-makers-and-hobbyists/" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">E.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty S7-25</description>
+<components>
+ <component name="part0" display_name="Arty S7-25" type="fpga" part_name="xc7s25csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://store.digilentinc.com/preview-arty-s7-spartan-7-fpga-for-makers-and-hobbyists/">
+ <interfaces>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+ <description>4-position user DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+ <description>4 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_4bits_tri_t" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+ <description>4 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <parameters>
+ <parameter name="rst_polarity" value="0"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_i" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_t" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp9" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp9" preset_proc="shield_dp0_dp9_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp9_tri_i" dir="in" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp9_tri_o" dir="out" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp9_tri_t" dir="out" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_a0_a5" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a0_a5" preset_proc="shield_a0_a5_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_a0_a5_tri_i" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_a0_a5_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_a0_a5_tri_t" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_a10_a11" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a10_a11" preset_proc="shield_a10_a11_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_a10_a11_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_a10_a11_tri_o" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_a10_a11_tri_t" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="ddr_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="ddr_clock" preset_proc="ddr_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="ddr_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="ddr_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="12000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="12000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>256 MB DDR3L memory SODIMM </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="256MB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 3 to 0</description>
+ </component>
+ <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+ <description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+ </component>
+ <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+ <description>CPU Reset Push Button, active low</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB LEDs 1 through 0 (3 per LED)</description>
+ </component>
+ <component name="shield_dp0_dp9" display_name="Shield Pins 0 through 9" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 0 through 9</description>
+ </component>
+ <component name="shield_a0_a5" display_name="Shield Pins A0 through A5 (digital)" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins A0 through A5 for digital use</description>
+ </component>
+ <component name="shield_a10_a11" display_name="Shield Pins A10 through A11 (digital)" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins A10 through A11 for digital use</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="ddr_clock" display_name="DDR Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>1.35V Single-Ended 100MHz oscillator used as DDR clock on the board</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 12MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+</components>
+
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+ <connection_map name="part0_dip_switches_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+ <connection_map name="part0_push_buttons_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+ <connection_map name="part0_led_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="18" c1_end_index="19" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="20" c1_end_index="24" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="25" c1_end_index="25" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ddr_clock" component1="part0" component2="ddr_clock">
+ <connection_map name="part0_ddr_clock_1" c1_st_index="26" c1_end_index="26" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_ddr_clock_1" c1_st_index="27" c1_end_index="27" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp9" component1="part0" component2="shield_dp0_dp9">
+ <connection_map name="part0_shield_dp0_dp9_1" c1_st_index="28" c1_end_index="37" c2_st_index="0" c2_end_index="9"/>
+ </connection>
+ <connection name="part0_shield_a0_a5" component1="part0" component2="shield_a0_a5">
+ <connection_map name="part0_shield_a0_a5_1" c1_st_index="38" c1_end_index="43" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_shield_a10_a11" component1="part0" component2="shield_a10_a11">
+ <connection_map name="part0_shield_a10_a11_1" c1_st_index="44" c1_end_index="45" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="46" c1_end_index="49" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="50" c1_end_index="51" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="52" c1_end_index="59" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="60" c1_end_index="67" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="68" c1_end_index="75" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="76" c1_end_index="83" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/mig.prj
new file mode 100644
index 000000000..ac6b4d600
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/mig.prj
@@ -0,0 +1,138 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>system_mig_7series_0_2</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Disabled</XADC_En>
+ <TargetFPGA>xc7s25-csga324/-1</TargetFPGA>
+ <Version>4.0</Version>
+ <SystemClock>Single-Ended</SystemClock>
+ <ReferenceClock>No Buffer</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+ <TimePeriod>3077</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>99.997</InputClkFreq>
+ <UIExtraClocks>1</UIExtraClocks>
+ <MMCM_VCO>649</MMCM_VCO>
+ <MMCMClkOut0> 3.250</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <BankMachineCnt>4</BankMachineCnt>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.35V</MemoryVoltage>
+ <C0_MEM_SIZE>268435456</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R4" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V2" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V3" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="T4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="R5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T2" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P1" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L5" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="L1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="K1" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N3" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="J6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P7" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Clock>
+ <Pin PADName="R2" Bank="34" name="sys_clk_i" />
+ </System_Clock>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml
new file mode 100644
index 000000000..e737bc76e
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/part0_pins.xml
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7s25csga324-1">
+<pins>
+ <pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
+ <pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
+ <pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
+ <pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
+ <pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
+ <pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
+ <pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
+ <pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
+ <pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
+ <pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
+ <pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
+ <pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
+ <pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
+ <pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
+ <pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
+ <pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
+ <pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="52" name ="JA1" iostandard="LVCMOS33" loc="L17"/>
+ <pin index="53" name ="JA2" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="54" name ="JA3" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="55" name ="JA4" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="56" name ="JA7" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="57" name ="JA8" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="58" name ="JA9" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
+ <pin index="60" name ="JB1" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="61" name ="JB2" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="62" name ="JB3" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="63" name ="JB4" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="64" name ="JB7" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="65" name ="JB8" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="66" name ="JB9" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="68" name ="JC1" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="69" name ="JC2" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="70" name ="JC3" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="71" name ="JC4" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="72" name ="JC7" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="73" name ="JC8" iostandard="LVCMOS33" loc="P13"/>
+ <pin index="74" name ="JC9" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="76" name ="JD1" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="77" name ="JD2" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="78" name ="JD3" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="79" name ="JD4" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="80" name ="JD7" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="81" name ="JD8" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="82" name ="JD9" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml
new file mode 100644
index 000000000..f5447f3dd
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-25/E.0/preset.xml
@@ -0,0 +1,394 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp9_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_a0_a5_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_a10_a11_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="ddr_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml
new file mode 100644
index 000000000..377ae4f9e
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/board.xml
@@ -0,0 +1,1113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-50" display_name="Arty S7-50" url="http://store.digilentinc.com/preview-arty-s7-spartan-7-fpga-for-makers-and-hobbyists/" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty S7-50</description>
+<components>
+ <component name="part0" display_name="Arty S7-50" type="fpga" part_name="xc7s50csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://store.digilentinc.com/preview-arty-s7-spartan-7-fpga-for-makers-and-hobbyists/">
+ <interfaces>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+ <description>4-position user DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+ <description>4 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_4bits_tri_t" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+ <description>4 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <parameters>
+ <parameter name="rst_polarity" value="0"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_i" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_t" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp9" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp9" preset_proc="shield_dp0_dp9_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp9_tri_i" dir="in" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp9_tri_o" dir="out" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp9_tri_t" dir="out" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp9_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp9_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp9_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp9_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp9_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp9_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp9_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp9_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp9_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp9_tri_i_9"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_a0_a5" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a0_a5" preset_proc="shield_a0_a5_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_a0_a5_tri_i" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_a0_a5_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_a0_a5_tri_t" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a0_a5_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a0_a5_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_a0_a5_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_a0_a5_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_a0_a5_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_a0_a5_tri_i_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_a10_a11" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_a10_a11" preset_proc="shield_a10_a11_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_a10_a11_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_a10_a11_tri_o" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_a10_a11_tri_t" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_a10_a11_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_a10_a11_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="ddr_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="ddr_clock" preset_proc="ddr_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="ddr_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="ddr_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="12000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="12000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>256 MB DDR3L memory SODIMM </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="256MB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 3 to 0</description>
+ </component>
+ <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+ <description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+ </component>
+ <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+ <description>CPU Reset Push Button, active low</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB LEDs 1 through 0 (3 per LED)</description>
+ </component>
+ <component name="shield_dp0_dp9" display_name="Shield Pins 0 through 9" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 0 through 9</description>
+ </component>
+ <component name="shield_a0_a5" display_name="Shield Pins A0 through A5 (digital)" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins A0 through A5 for digital use</description>
+ </component>
+ <component name="shield_a10_a11" display_name="Shield Pins A10 through A11 (digital)" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins A10 through A11 for digital use</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="ddr_clock" display_name="DDR Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>1.35V Single-Ended 100MHz oscillator used as DDR clock on the board</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 12MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+</components>
+
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+ <connection_map name="part0_dip_switches_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+ <connection_map name="part0_push_buttons_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+ <connection_map name="part0_led_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="18" c1_end_index="19" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="20" c1_end_index="24" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="25" c1_end_index="25" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ddr_clock" component1="part0" component2="ddr_clock">
+ <connection_map name="part0_ddr_clock_1" c1_st_index="26" c1_end_index="26" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_ddr_clock_1" c1_st_index="27" c1_end_index="27" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp9" component1="part0" component2="shield_dp0_dp9">
+ <connection_map name="part0_shield_dp0_dp9_1" c1_st_index="28" c1_end_index="37" c2_st_index="0" c2_end_index="9"/>
+ </connection>
+ <connection name="part0_shield_a0_a5" component1="part0" component2="shield_a0_a5">
+ <connection_map name="part0_shield_a0_a5_1" c1_st_index="38" c1_end_index="43" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_shield_a10_a11" component1="part0" component2="shield_a10_a11">
+ <connection_map name="part0_shield_a10_a11_1" c1_st_index="44" c1_end_index="45" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="46" c1_end_index="49" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="50" c1_end_index="51" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="52" c1_end_index="59" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="60" c1_end_index="67" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="68" c1_end_index="75" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="76" c1_end_index="83" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/mig.prj
new file mode 100644
index 000000000..e4f4a6959
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/mig.prj
@@ -0,0 +1,138 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>system_mig_7series_0_2</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Disabled</XADC_En>
+ <TargetFPGA>xc7s50-csga324/-1</TargetFPGA>
+ <Version>4.0</Version>
+ <SystemClock>Single-Ended</SystemClock>
+ <ReferenceClock>No Buffer</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+ <TimePeriod>3077</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>99.997</InputClkFreq>
+ <UIExtraClocks>1</UIExtraClocks>
+ <MMCM_VCO>649</MMCM_VCO>
+ <MMCMClkOut0> 3.250</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <BankMachineCnt>4</BankMachineCnt>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.35V</MemoryVoltage>
+ <C0_MEM_SIZE>268435456</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R4" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V2" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V3" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="T4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="R5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T2" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P1" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L5" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="L1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="K1" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N3" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="J6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P7" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Clock>
+ <Pin PADName="R2" Bank="34" name="sys_clk_i" />
+ </System_Clock>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml
new file mode 100644
index 000000000..b4e58e7a2
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/part0_pins.xml
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7s50csga324-1">
+<pins>
+ <pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
+ <pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
+ <pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
+ <pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
+ <pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
+ <pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
+ <pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
+ <pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
+ <pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
+ <pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
+ <pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
+ <pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
+ <pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
+ <pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
+ <pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
+ <pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
+ <pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="52" name ="JA1" iostandard="LVCMOS33" loc="L17"/>
+ <pin index="53" name ="JA2" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="54" name ="JA3" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="55" name ="JA4" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="56" name ="JA7" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="57" name ="JA8" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="58" name ="JA9" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
+ <pin index="60" name ="JB1" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="61" name ="JB2" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="62" name ="JB3" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="63" name ="JB4" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="64" name ="JB7" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="65" name ="JB8" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="66" name ="JB9" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="68" name ="JC1" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="69" name ="JC2" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="70" name ="JC3" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="71" name ="JC4" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="72" name ="JC7" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="73" name ="JC8" iostandard="LVCMOS33" loc="P13"/>
+ <pin index="74" name ="JC9" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="76" name ="JD1" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="77" name ="JD2" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="78" name ="JD3" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="79" name ="JD4" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="80" name ="JD7" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="81" name ="JD8" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="82" name ="JD9" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml
new file mode 100644
index 000000000..f5447f3dd
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-s7-50/B.0/preset.xml
@@ -0,0 +1,394 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp9_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_a0_a5_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_a10_a11_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="ddr_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml
new file mode 100644
index 000000000..37451dd99
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/board.xml
@@ -0,0 +1,601 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-10" display_name="Arty Z7-10" url="http://www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty Z7-10 </description>
+<components>
+ <component name="part0" display_name="Arty Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 3 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 1 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+ </component>
+
+ <component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+ </component>
+ <component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP0 through DP13</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+ <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+ <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">
+ <connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+ <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml
new file mode 100644
index 000000000..4ec634644
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/part0_pins.xml
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z010clg400-1">
+<pins>
+ <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
+ <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
+ <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
+ <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
+ <pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
+ <pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
+ <pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
+ <pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
+ <pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
+ <pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
+ <pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
+ <pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
+ <pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml
new file mode 100644
index 000000000..216b7ea31
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-10/A.0/preset.xml
@@ -0,0 +1,1080 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_UART0_BASEADDR" value="0xE0000000"/>
+ <user_parameter name="CONFIG.PCW_UART0_HIGHADDR" value="0xE0000FFF"/>
+ <user_parameter name="CONFIG.PCW_UART1_BASEADDR" value="0xE0001000"/>
+ <user_parameter name="CONFIG.PCW_UART1_HIGHADDR" value="0xE0001FFF"/>
+ <user_parameter name="CONFIG.PCW_I2C0_BASEADDR" value="0xE0004000"/>
+ <user_parameter name="CONFIG.PCW_I2C0_HIGHADDR" value="0xE0004FFF"/>
+ <user_parameter name="CONFIG.PCW_I2C1_BASEADDR" value="0xE0005000"/>
+ <user_parameter name="CONFIG.PCW_I2C1_HIGHADDR" value="0xE0005FFF"/>
+ <user_parameter name="CONFIG.PCW_SPI0_BASEADDR" value="0xE0006000"/>
+ <user_parameter name="CONFIG.PCW_SPI0_HIGHADDR" value="0xE0006FFF"/>
+ <user_parameter name="CONFIG.PCW_SPI1_BASEADDR" value="0xE0007000"/>
+ <user_parameter name="CONFIG.PCW_SPI1_HIGHADDR" value="0xE0007FFF"/>
+ <user_parameter name="CONFIG.PCW_CAN0_BASEADDR" value="0xE0008000"/>
+ <user_parameter name="CONFIG.PCW_CAN0_HIGHADDR" value="0xE0008FFF"/>
+ <user_parameter name="CONFIG.PCW_CAN1_BASEADDR" value="0xE0009000"/>
+ <user_parameter name="CONFIG.PCW_CAN1_HIGHADDR" value="0xE0009FFF"/>
+ <user_parameter name="CONFIG.PCW_GPIO_BASEADDR" value="0xE000A000"/>
+ <user_parameter name="CONFIG.PCW_GPIO_HIGHADDR" value="0xE000AFFF"/>
+ <user_parameter name="CONFIG.PCW_ENET0_BASEADDR" value="0xE000B000"/>
+ <user_parameter name="CONFIG.PCW_ENET0_HIGHADDR" value="0xE000BFFF"/>
+ <user_parameter name="CONFIG.PCW_ENET1_BASEADDR" value="0xE000C000"/>
+ <user_parameter name="CONFIG.PCW_ENET1_HIGHADDR" value="0xE000CFFF"/>
+ <user_parameter name="CONFIG.PCW_SDIO0_BASEADDR" value="0xE0100000"/>
+ <user_parameter name="CONFIG.PCW_SDIO0_HIGHADDR" value="0xE0100FFF"/>
+ <user_parameter name="CONFIG.PCW_SDIO1_BASEADDR" value="0xE0101000"/>
+ <user_parameter name="CONFIG.PCW_SDIO1_HIGHADDR" value="0xE0101FFF"/>
+ <user_parameter name="CONFIG.PCW_USB0_BASEADDR" value="0xE0102000"/>
+ <user_parameter name="CONFIG.PCW_USB0_HIGHADDR" value="0xE0102fff"/>
+ <user_parameter name="CONFIG.PCW_USB1_BASEADDR" value="0xE0103000"/>
+ <user_parameter name="CONFIG.PCW_USB1_HIGHADDR" value="0xE0103fff"/>
+ <user_parameter name="CONFIG.PCW_TTC0_BASEADDR" value="0xE0104000"/>
+ <user_parameter name="CONFIG.PCW_TTC0_HIGHADDR" value="0xE0104fff"/>
+ <user_parameter name="CONFIG.PCW_TTC1_BASEADDR" value="0xE0105000"/>
+ <user_parameter name="CONFIG.PCW_TTC1_HIGHADDR" value="0xE0105fff"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK0_BUF" value="true"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK1_BUF" value="false"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK2_BUF" value="false"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK3_BUF" value="false"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.91"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="25.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="25.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.223"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.212"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.085"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.092"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ" value="166.666666"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ" value="-1"/>
+ <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ" value="-1"/>
+ <user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ" value="25"/>
+ <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="650.000000"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="525.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.096154"/>
+ <user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" value="23.8095"/>
+ <user_parameter name="CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" value="23.8095"/>
+ <user_parameter name="CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000"/>
+ <user_parameter name="CONFIG.PCW_CLK1_FREQ" value="50000000"/>
+ <user_parameter name="CONFIG.PCW_CLK2_FREQ" value="50000000"/>
+ <user_parameter name="CONFIG.PCW_CLK3_FREQ" value="50000000"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_VALID" value="0"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_VALID" value="0"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_VALID" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CAN0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CAN1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_ENET1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_PTP_ENET0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_PTP_ENET1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_GPIO" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_I2C0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_PJTAG" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SPI0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SPI1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_TTC0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_TTC1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_WDT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_TRACE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_GP0" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_GP1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_ACP" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP0" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP2" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP3" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP0_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP1_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP0_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP1_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP2_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP3_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA0" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA2" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA3" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_TRACE" value="0"/>
+ <user_parameter name="CONFIG.PCW_TRACE_PIPELINE_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.PCW_INCLUDE_TRACE_BUFFER" value="0"/>
+ <user_parameter name="CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE" value="128"/>
+ <user_parameter name="CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR" value="0"/>
+ <user_parameter name="CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY" value="12"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DEBUG" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CR_FABRIC" value="1"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_FABRIC_IDLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DDR_BYPASS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_FABRIC_INTERRUPT" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_PROC_EVENT_BUS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_EXPANDED_IOP" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_HIGH_OCM" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_PS_SLCR_REGISTERS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CORESIGHT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SRAM_INT" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP0_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP1_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_ID_WIDTH" value="3"/>
+ <user_parameter name="CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL" value="0"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_ARUSER_VAL" value="31"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_AWUSER_VAL" value="31"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP0_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP0_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP1_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP1_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP2_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP2_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP3_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP3_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_EN_DDR" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_SMC" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_QSPI" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_CAN0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CAN1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_ENET0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_ENET1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_GPIO" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_I2C0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_I2C1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_PJTAG" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_SDIO0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_SPI0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_SPI1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_UART0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_MODEM_UART0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_MODEM_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_TTC0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_TTC1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_WDT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_TRACE" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_USB0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_USB1" value="0"/>
+ <user_parameter name="CONFIG.PCW_DQ_WIDTH" value="32"/>
+ <user_parameter name="CONFIG.PCW_DQS_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.PCW_DM_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.PCW_MIO_PRIMITIVE" value="54"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK0_PORT" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK1_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK2_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK3_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_RST0_PORT" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_RST1_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_RST2_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_RST3_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG0_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG1_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG2_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG3_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC_ABORT_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC2_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC3_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC4_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC5_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC6_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC7_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SMC_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_QSPI_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_CTI_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_GPIO_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_USB0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_ENET0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SDIO0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_I2C0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SPI0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_UART0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_CAN0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_USB1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_ENET1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SDIO1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_I2C1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SPI1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_UART1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_CAN1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_CORE0_FIQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_CORE0_IRQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_CORE1_FIQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_CORE1_IRQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_VALUE_SILVERSION" value="3"/>
+ <user_parameter name="CONFIG.PCW_IMPORT_BOARD_PRESET" value="None"/>
+ <user_parameter name="CONFIG.PCW_PERIPHERAL_BOARD_PRESET" value="None"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT0_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT1_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT2_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT3_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+ <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_GRP_MDIO_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_GRP_CD_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+ <user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_GRP_SS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_GRP_SS2_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI1_GRP_SS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI1_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_I2C_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_GENERATE_SUMMARY" value="NA"/>
+ <user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+ <user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+ <user_parameter name="CONFIG.PCW_PS7_SI_REV" value="PRODUCTION"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_AR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_CLR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_REA" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T0" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T1" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T2" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T3" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T4" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T5" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T6" value="NA"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_NAME" value="clg400"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_dp0_dp13_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml
new file mode 100644
index 000000000..5e2c0be5d
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/board.xml
@@ -0,0 +1,674 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="http://www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Arty Z7-20 </description>
+<components>
+ <component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 3 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 1 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+ </component>
+
+ <component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+ </component>
+ <component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP0 through DP13</description>
+ </component>
+ <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP26 through DP41</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+ <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+ <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">
+ <connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+ <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>
+ </connection>
+ <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+ <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="49" c1_end_index="64" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml
new file mode 100644
index 000000000..39c17d831
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/part0_pins.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z020clg400-1">
+<pins>
+ <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
+ <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
+ <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
+ <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
+ <pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
+ <pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
+ <pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
+ <pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
+ <pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
+ <pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
+ <pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
+ <pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
+ <pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="49" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U5"/>
+ <pin index="50" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V5"/>
+ <pin index="51" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="V6"/>
+ <pin index="52" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="53" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="54" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U8"/>
+ <pin index="55" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="56" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="57" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="W10"/>
+ <pin index="58" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="W6"/>
+ <pin index="59" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="Y6"/>
+ <pin index="60" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="Y7"/>
+ <pin index="61" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="W8"/>
+ <pin index="62" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="Y8"/>
+ <pin index="63" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="W9"/>
+ <pin index="64" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="Y9"/>
+ <pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml
new file mode 100644
index 000000000..76f050962
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty-z7-20/A.0/preset.xml
@@ -0,0 +1,1098 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_UART0_BASEADDR" value="0xE0000000"/>
+ <user_parameter name="CONFIG.PCW_UART0_HIGHADDR" value="0xE0000FFF"/>
+ <user_parameter name="CONFIG.PCW_UART1_BASEADDR" value="0xE0001000"/>
+ <user_parameter name="CONFIG.PCW_UART1_HIGHADDR" value="0xE0001FFF"/>
+ <user_parameter name="CONFIG.PCW_I2C0_BASEADDR" value="0xE0004000"/>
+ <user_parameter name="CONFIG.PCW_I2C0_HIGHADDR" value="0xE0004FFF"/>
+ <user_parameter name="CONFIG.PCW_I2C1_BASEADDR" value="0xE0005000"/>
+ <user_parameter name="CONFIG.PCW_I2C1_HIGHADDR" value="0xE0005FFF"/>
+ <user_parameter name="CONFIG.PCW_SPI0_BASEADDR" value="0xE0006000"/>
+ <user_parameter name="CONFIG.PCW_SPI0_HIGHADDR" value="0xE0006FFF"/>
+ <user_parameter name="CONFIG.PCW_SPI1_BASEADDR" value="0xE0007000"/>
+ <user_parameter name="CONFIG.PCW_SPI1_HIGHADDR" value="0xE0007FFF"/>
+ <user_parameter name="CONFIG.PCW_CAN0_BASEADDR" value="0xE0008000"/>
+ <user_parameter name="CONFIG.PCW_CAN0_HIGHADDR" value="0xE0008FFF"/>
+ <user_parameter name="CONFIG.PCW_CAN1_BASEADDR" value="0xE0009000"/>
+ <user_parameter name="CONFIG.PCW_CAN1_HIGHADDR" value="0xE0009FFF"/>
+ <user_parameter name="CONFIG.PCW_GPIO_BASEADDR" value="0xE000A000"/>
+ <user_parameter name="CONFIG.PCW_GPIO_HIGHADDR" value="0xE000AFFF"/>
+ <user_parameter name="CONFIG.PCW_ENET0_BASEADDR" value="0xE000B000"/>
+ <user_parameter name="CONFIG.PCW_ENET0_HIGHADDR" value="0xE000BFFF"/>
+ <user_parameter name="CONFIG.PCW_ENET1_BASEADDR" value="0xE000C000"/>
+ <user_parameter name="CONFIG.PCW_ENET1_HIGHADDR" value="0xE000CFFF"/>
+ <user_parameter name="CONFIG.PCW_SDIO0_BASEADDR" value="0xE0100000"/>
+ <user_parameter name="CONFIG.PCW_SDIO0_HIGHADDR" value="0xE0100FFF"/>
+ <user_parameter name="CONFIG.PCW_SDIO1_BASEADDR" value="0xE0101000"/>
+ <user_parameter name="CONFIG.PCW_SDIO1_HIGHADDR" value="0xE0101FFF"/>
+ <user_parameter name="CONFIG.PCW_USB0_BASEADDR" value="0xE0102000"/>
+ <user_parameter name="CONFIG.PCW_USB0_HIGHADDR" value="0xE0102fff"/>
+ <user_parameter name="CONFIG.PCW_USB1_BASEADDR" value="0xE0103000"/>
+ <user_parameter name="CONFIG.PCW_USB1_HIGHADDR" value="0xE0103fff"/>
+ <user_parameter name="CONFIG.PCW_TTC0_BASEADDR" value="0xE0104000"/>
+ <user_parameter name="CONFIG.PCW_TTC0_HIGHADDR" value="0xE0104fff"/>
+ <user_parameter name="CONFIG.PCW_TTC1_BASEADDR" value="0xE0105000"/>
+ <user_parameter name="CONFIG.PCW_TTC1_HIGHADDR" value="0xE0105fff"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK0_BUF" value="true"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK1_BUF" value="false"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK2_BUF" value="false"/>
+ <user_parameter name="CONFIG.PCW_FCLK_CLK3_BUF" value="false"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.91"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="25.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="25.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.223"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.212"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.085"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.092"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ" value="166.666666"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ" value="-1"/>
+ <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ" value="-1"/>
+ <user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ" value="25"/>
+ <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="133.333333"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="650.000000"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="525.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.096154"/>
+ <user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" value="23.8095"/>
+ <user_parameter name="CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" value="23.8095"/>
+ <user_parameter name="CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="108.333336"/>
+ <user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000"/>
+ <user_parameter name="CONFIG.PCW_CLK1_FREQ" value="50000000"/>
+ <user_parameter name="CONFIG.PCW_CLK2_FREQ" value="50000000"/>
+ <user_parameter name="CONFIG.PCW_CLK3_FREQ" value="50000000"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_VALID" value="0"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_VALID" value="0"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_VALID" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CAN0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CAN1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_ENET1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_PTP_ENET0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_PTP_ENET1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_GPIO" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_I2C0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_PJTAG" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_WP_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SPI0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SPI1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_MODEM_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_TTC0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_TTC1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_WDT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_TRACE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_GP0" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_GP1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_ACP" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP0" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP2" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_S_AXI_HP3" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP0_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP1_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP0_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP1_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP2_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP3_FREQMHZ" value="10"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA0" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA1" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA2" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DMA3" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_TRACE" value="0"/>
+ <user_parameter name="CONFIG.PCW_TRACE_PIPELINE_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.PCW_INCLUDE_TRACE_BUFFER" value="0"/>
+ <user_parameter name="CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE" value="128"/>
+ <user_parameter name="CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR" value="0"/>
+ <user_parameter name="CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY" value="12"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DEBUG" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CR_FABRIC" value="1"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_FABRIC_IDLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DDR_BYPASS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_FABRIC_INTERRUPT" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_PROC_EVENT_BUS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_EXPANDED_IOP" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_HIGH_OCM" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_PS_SLCR_REGISTERS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CORESIGHT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_EMIO_SRAM_INT" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" value="0"/>
+ <user_parameter name="CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP0_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_GP1_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_ID_WIDTH" value="3"/>
+ <user_parameter name="CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL" value="0"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_ARUSER_VAL" value="31"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_ACP_AWUSER_VAL" value="31"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP0_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP0_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP1_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP1_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP2_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP2_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP3_ID_WIDTH" value="6"/>
+ <user_parameter name="CONFIG.PCW_S_AXI_HP3_DATA_WIDTH" value="64"/>
+ <user_parameter name="CONFIG.PCW_EN_DDR" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_SMC" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_QSPI" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_CAN0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CAN1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_ENET0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_ENET1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_GPIO" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_I2C0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_I2C1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_PJTAG" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_SDIO0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_SDIO1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_SPI0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_SPI1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_UART0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_MODEM_UART0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_MODEM_UART1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_TTC0" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_TTC1" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_WDT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_TRACE" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_USB0" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_USB1" value="0"/>
+ <user_parameter name="CONFIG.PCW_DQ_WIDTH" value="32"/>
+ <user_parameter name="CONFIG.PCW_DQS_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.PCW_DM_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.PCW_MIO_PRIMITIVE" value="54"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK0_PORT" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK1_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK2_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLK3_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_RST0_PORT" value="1"/>
+ <user_parameter name="CONFIG.PCW_EN_RST1_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_RST2_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_RST3_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG0_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG1_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG2_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_EN_CLKTRIG3_PORT" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC_ABORT_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC2_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC3_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC4_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC5_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC6_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_DMAC7_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SMC_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_QSPI_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_CTI_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_GPIO_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_USB0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_ENET0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SDIO0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_I2C0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SPI0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_UART0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_CAN0_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_USB1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_ENET1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SDIO1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_I2C1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_SPI1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_UART1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_P2F_CAN1_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_CORE0_FIQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_CORE0_IRQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_CORE1_FIQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_CORE1_IRQ_INTR" value="0"/>
+ <user_parameter name="CONFIG.PCW_VALUE_SILVERSION" value="3"/>
+ <user_parameter name="CONFIG.PCW_IMPORT_BOARD_PRESET" value="None"/>
+ <user_parameter name="CONFIG.PCW_PERIPHERAL_BOARD_PRESET" value="None"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT0_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT1_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT2_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_PORT3_HPR_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+ <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_GRP_MDIO_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_GRP_CD_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD1_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+ <user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_GRP_SS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI0_GRP_SS2_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI1_GRP_SS0_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SPI1_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_WDT_PERIPHERAL_CLKSRC" value="CPU_1X"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_I2C_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_GENERATE_SUMMARY" value="NA"/>
+ <user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+ <user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+ <user_parameter name="CONFIG.PCW_PS7_SI_REV" value="PRODUCTION"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS0_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_SRAM_CS1_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS0_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_TR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_PC" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_CEOE" value="1"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NOR_CS1_WE_TIME" value="0"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_AR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_CLR" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WP" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_REA" value="1"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_WC" value="11"/>
+ <user_parameter name="CONFIG.PCW_NAND_CYCLES_T_RC" value="11"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T0" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T1" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T2" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T3" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T4" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T5" value="NA"/>
+ <user_parameter name="CONFIG.PCW_SMC_CYCLE_T6" value="NA"/>
+ <user_parameter name="CONFIG.PCW_PACKAGE_NAME" value="clg400"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_dp0_dp13_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/board.xml
new file mode 100644
index 000000000..8a93718b1
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/board.xml
@@ -0,0 +1,1287 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="arty" display_name="Arty" url="www.digilentinc.com/Arty" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Arty</description>
+<components>
+ <component name="part0" display_name="Arty" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/Arty">
+ <interfaces>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_4bits" preset_proc="dip_switches_4bits_preset">
+ <description>4-position user DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mii" type="xilinx.com:interface:mii_rtl:1.0" of_component="phy_onboard" preset_proc="mii_preset">
+ <description>Primary interface to communicate with ethernet phy in MII mode. </description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="eth_txd" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_txd_0"/>
+ <pin_map port_index="1" component_pin="eth_txd_1"/>
+ <pin_map port_index="2" component_pin="eth_txd_2"/>
+ <pin_map port_index="3" component_pin="eth_txd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_EN" physical_port="eth_tx_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXD" physical_port="eth_rxd" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rxd_0"/>
+ <pin_map port_index="1" component_pin="eth_rxd_1"/>
+ <pin_map port_index="2" component_pin="eth_rxd_2"/>
+ <pin_map port_index="3" component_pin="eth_rxd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_DV" physical_port="eth_rx_dv" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_dv"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_ER" physical_port="eth_rx_er" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_er"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CRS" physical_port="eth_crs" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_crs"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="COL" physical_port="eth_col" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_col"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_CLK" physical_port="eth_tx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_CLK" physical_port="eth_rx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RST_N" physical_port="eth_rstn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rstn"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="i2c_pullups" type="xilinx.com:interface:gpio_rtl:1.0" of_component="i2c_pullups" preset_proc="output_2bits_preset">
+ <description>I2C Pullups to enable shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="i2c_pullup" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="i2c_pullup_0"/>
+ <pin_map port_index="1" component_pin="i2c_pullup_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
+ <description>4 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_4bits_tri_t" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+ <description>4 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="qspi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="qspi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="qspi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <parameters>
+ <parameter name="rst_polarity" value="0"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_12bits_preset">
+ <description>4 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_i" dir="in" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_t" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ <pin_map port_index="6" component_pin="rgb_led_tri_o_6"/>
+ <pin_map port_index="7" component_pin="rgb_led_tri_o_7"/>
+ <pin_map port_index="8" component_pin="rgb_led_tri_o_8"/>
+ <pin_map port_index="9" component_pin="rgb_led_tri_o_9"/>
+ <pin_map port_index="10" component_pin="rgb_led_tri_o_10"/>
+ <pin_map port_index="11" component_pin="rgb_led_tri_o_11"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp19" preset_proc="shield_dp0_dp19_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp19_tri_i" dir="in" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp19_tri_o" dir="out" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp19_tri_t" dir="out" left="19" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp19_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp19_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp19_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp19_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp19_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp19_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp19_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp19_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp19_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp19_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp19_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp19_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp19_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp19_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp0_dp19_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp0_dp19_tri_i_15"/>
+ <pin_map port_index="16" component_pin="shield_dp0_dp19_tri_i_16"/>
+ <pin_map port_index="17" component_pin="shield_dp0_dp19_tri_i_17"/>
+ <pin_map port_index="18" component_pin="shield_dp0_dp19_tri_i_18"/>
+ <pin_map port_index="19" component_pin="shield_dp0_dp19_tri_i_19"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>256 MB DDR3L memory SODIMM </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="256MB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="phy_onboard" display_name="Ethernet MII" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>PHY Ethernet on the board</description>
+ <component_modes>
+ <component_mode name="mii" display_name="MII mode">
+ <interfaces>
+ <interface name="eth_mii" order="0"/>
+ <interface name="eth_mdio_mdc" order="1" optional="true"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="i2c" display_name="I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield i2c</description>
+ </component>
+ <component name="i2c_pullups" display_name="I2C Pullups" type="chip" sub_type="chip" major_group="I2C">
+ <description>Shield i2c pullups, must pull high if using the shield I2C on J3</description>
+ </component>
+ <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 3 to 0</description>
+ </component>
+ <component name="qspi_flash" display_name="Quad SPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESF40" vendor="Micron" spec_url="www.micron.com/memory">
+ <description>16 MB of nonvolatile storage that can be used for configuration or data storage</description>
+ </component>
+ <component name="reset" display_name="System Reset" type="chip" sub_type="system_reset" major_group="Reset">
+ <description>CPU Reset Push Button, active low</description>
+ </component>
+ <component name="rgb_led" display_name="4 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 12 to 0 (3 per LED)</description>
+ </component>
+ <component name="shield_dp0_dp19" display_name="Shield Pins 0 through 19" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 0 through 19</description>
+ </component>
+ <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+ <description>Shield pins 26 through 41</description>
+ </component>
+ <component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+ </preferred_ips>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+</components>
+
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_4bits" component1="part0" component2="dip_switches_4bits">
+ <connection_map name="part0_dip_switches_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+ <connection_map name="part0_phy_onboard_1" c1_st_index="5" c1_end_index="22" c2_st_index="0" c2_end_index="17"/>
+ <connection_map name="part0_phy_onboard_2" c1_st_index="7" c1_end_index="8" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_i2c" component1="part0" component2="i2c">
+ <connection_map name="part0_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_i2cpullups" component1="part0" component2="i2c_pullups">
+ <connection_map name="part0_i2c_pullups" c1_st_index="23" c1_end_index="24" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+ <connection_map name="part0_led_4bits_1" c1_st_index="27" c1_end_index="30" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_push_buttons_4bits" component1="part0" component2="push_buttons_4bits">
+ <connection_map name="part0_push_buttons_4bits_1" c1_st_index="31" c1_end_index="34" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="42" c1_end_index="53" c2_st_index="0" c2_end_index="11"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp19" component1="part0" component2="shield_dp0_dp19">
+ <connection_map name="part0_shield_dp0_dp19_1" c1_st_index="54" c1_end_index="73" c2_st_index="0" c2_end_index="19"/>
+ </connection>
+ <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+ <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="74" c1_end_index="89" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_spi" component1="part0" component2="spi">
+ <connection_map name="part0_spi_1" c1_st_index="90" c1_end_index="93" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="94" c1_end_index="95" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/mig.prj
new file mode 100644
index 000000000..9b31d7bc8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/mig.prj
@@ -0,0 +1,134 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
+ <Version>2.3</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>No Buffer</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+ <TimePeriod>3000</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>166.666</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>666</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.35V</MemoryVoltage>
+ <C0_MEM_SIZE>268435456</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml
new file mode 100644
index 000000000..ffe0dd45b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/part0_pins.xml
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a35tcsg324-1L">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+ <pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
+ <pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
+ <pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
+ <pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
+ <pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
+ <pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
+ <pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
+ <pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
+ <pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
+ <pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
+ <pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
+ <pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
+ <pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
+ <pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
+ <pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
+ <pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
+ <pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
+ <pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
+ <pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
+ <pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
+ <pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
+ <pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
+ <pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
+ <pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
+ <pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
+ <pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
+ <pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
+ <pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
+ <pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
+ <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
+ <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
+ <pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
+ <pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
+ <pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
+ <pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
+ <pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
+ <pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
+ <pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
+ <pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
+ <pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
+ <pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
+ <pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
+ <pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
+ <pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
+ <pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
+ <pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
+ <pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
+ <pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/preset.xml
new file mode 100644
index 000000000..df58104e8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/arty/C.0/preset.xml
@@ -0,0 +1,385 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_12bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="mii_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.Physical_Interface" value="MII"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp19_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/board.xml
new file mode 100644
index 000000000..8b81b1327
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/board.xml
@@ -0,0 +1,844 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+ <board schema_version="2.0" vendor="digilentinc.com" name="basys3" display_name="Basys3" url="www.digilentinc.com/basys3" preset_file="preset.xml">
+<compatible_board_revisions>
+ <revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Basys3</description>
+<components>
+ <component name="part0" display_name="Basys3" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/basys3">
+ <interfaces>
+ <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/>
+ <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/>
+ <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/>
+ <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/>
+ <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/>
+ <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/>
+ <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/>
+ <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/>
+ <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="led_16bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_16bits_tri_o" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="1" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="seven_seg_led_an_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_disp" preset_proc="seven_seg_led_seg_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="seven_seg_led_disp_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>Switches 15 to 0</description>
+ </component>
+ <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 15 to 0</description>
+ </component>
+ <component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 3 to 0 [Down Right Left Up]</description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset Signal (BTNC)" type="chip" sub_type="reset" major_group="Reset">
+ <description>Reset button (BTNC)</description>
+ </component>
+ <component name="seven_seg_led_an" display_name="7 Segment Display - Anodes" type="chip" sub_type="led" major_group="GPIO">
+ <description>Seven Segment Anodes</description>
+ </component>
+ <component name="seven_seg_led_disp" display_name="7 Segment Display - Segments" type="chip" sub_type="led" major_group="GPIO">
+ <description>Seven Segment display segments</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>100 MHz System Clock</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB UART</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JXADC</description>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+ <connection_map name="part0_dip_switches_16bits_1" c1_st_index="1" c1_end_index="16" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+ <connection_map name="part0_led_16bits_1" c1_st_index="17" c1_end_index="32" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+ <connection_map name="part0_push_buttons_5bits_1" c1_st_index="33" c1_end_index="36" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="37" c1_end_index="41" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="42" c1_end_index="42" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+ <connection_map name="part0_seven_seg_led_an_1" c1_st_index="43" c1_end_index="46" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_seven_seg_led_disp" component1="part0" component2="seven_seg_led_disp">
+ <connection_map name="part0_seven_seg_led_disp_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="55" c1_end_index="56" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="57" c1_end_index="64" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="65" c1_end_index="72" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="73" c1_end_index="80" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jxadc" component1="part0" component2="jxadc">
+ <connection_map name="part0_jxadc_1" c1_st_index="81" c1_end_index="88" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml
new file mode 100644
index 000000000..3ef61d56e
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/part0_pins.xml
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a35tcpg236-1">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="W5"/>
+ <pin index="1" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="2" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="3" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="4" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="W17"/>
+ <pin index="5" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="6" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="7" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="8" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="9" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS33" loc="V2"/>
+ <pin index="10" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS33" loc="T3"/>
+ <pin index="11" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="T2"/>
+ <pin index="12" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="R3"/>
+ <pin index="13" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="W2"/>
+ <pin index="14" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U1"/>
+ <pin index="15" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="T1"/>
+ <pin index="16" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="R2"/>
+ <pin index="17" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="18" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="E19"/>
+ <pin index="19" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="20" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="21" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="22" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="23" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="24" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="25" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="26" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="V3"/>
+ <pin index="27" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="W3"/>
+ <pin index="28" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="U3"/>
+ <pin index="29" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="P3"/>
+ <pin index="30" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="N3"/>
+ <pin index="31" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="P1"/>
+ <pin index="32" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="L1"/>
+ <pin index="33" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="34" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="35" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="36" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="37" name ="qspi_csn_i" iostandard="LVCMOS33" loc="K19"/>
+ <pin index="38" name ="qspi_db0_i" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="39" name ="qspi_db1_i" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="40" name ="qspi_db2_i" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="41" name ="qspi_db3_i" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="42" name ="reset" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="43" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="U2"/>
+ <pin index="44" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="U4"/>
+ <pin index="45" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="V4"/>
+ <pin index="46" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="W4"/>
+ <pin index="47" name ="seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="W7"/>
+ <pin index="48" name ="seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="W6"/>
+ <pin index="49" name ="seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="U8"/>
+ <pin index="50" name ="seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="51" name ="seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="U5"/>
+ <pin index="52" name ="seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="V5"/>
+ <pin index="53" name ="seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="54" name ="seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="55" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="56" name ="usb_uart_txd" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="57" name ="JA1" iostandard="LVCMOS33" loc="J1"/>
+ <pin index="58" name ="JA2" iostandard="LVCMOS33" loc="L2"/>
+ <pin index="59" name ="JA3" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="60" name ="JA4" iostandard="LVCMOS33" loc="G2"/>
+ <pin index="61" name ="JA7" iostandard="LVCMOS33" loc="H1"/>
+ <pin index="62" name ="JA8" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="63" name ="JA9" iostandard="LVCMOS33" loc="H2"/>
+ <pin index="64" name ="JA10" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="65" name ="JB1" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="66" name ="JB2" iostandard="LVCMOS33" loc="A16"/>
+ <pin index="67" name ="JB3" iostandard="LVCMOS33" loc="B15"/>
+ <pin index="68" name ="JB4" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="69" name ="JB7" iostandard="LVCMOS33" loc="A15"/>
+ <pin index="70" name ="JB8" iostandard="LVCMOS33" loc="A17"/>
+ <pin index="71" name ="JB9" iostandard="LVCMOS33" loc="C15"/>
+ <pin index="72" name ="JB10" iostandard="LVCMOS33" loc="C16"/>
+ <pin index="73" name ="JC1" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="74" name ="JC2" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="75" name ="JC3" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="76" name ="JC4" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="77" name ="JC7" iostandard="LVCMOS33" loc="L17"/>
+ <pin index="78" name ="JC8" iostandard="LVCMOS33" loc="M19"/>
+ <pin index="79" name ="JC9" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="80" name ="JC10" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="81" name ="JXADC1" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="82" name ="JXADC2" iostandard="LVCMOS33" loc="L3"/>
+ <pin index="83" name ="JXADC3" iostandard="LVCMOS33" loc="M2"/>
+ <pin index="84" name ="JXADC4" iostandard="LVCMOS33" loc="N2"/>
+ <pin index="85" name ="JXADC7" iostandard="LVCMOS33" loc="K3"/>
+ <pin index="86" name ="JXADC8" iostandard="LVCMOS33" loc="M3"/>
+ <pin index="87" name ="JXADC9" iostandard="LVCMOS33" loc="M1"/>
+ <pin index="88" name ="JXADC10" iostandard="LVCMOS33" loc="N1"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/preset.xml
new file mode 100644
index 000000000..139a22f46
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/basys3/C.0/preset.xml
@@ -0,0 +1,313 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="mii_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.Physical_Interface" value="MII"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="seven_seg_led_an_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="seven_seg_led_seg_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ <user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml
new file mode 100644
index 000000000..c5a89660a
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/board.xml
@@ -0,0 +1,426 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod-s7-25" display_name="Cmod S7-25" url="https://reference.digilentinc.com/programmable-logic/cmod-s7/start" preset_file="preset.xml">
+ <compatible_board_revisions>
+ <revision id="0">B.0</revision>
+ </compatible_board_revisions>
+ <file_version>1.0</file_version>
+ <description>Cmod S7-25</description>
+ <components>
+ <component name="part0" display_name="Cmod S7-25" type="fpga" part_name="xc7s25csga225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://store.digilentinc.com/">
+ <interfaces>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <description>12 MHz Single-Ended System Clock</description>
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="12000000"/>
+ </parameters>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>BTN0 used as Active High System Reset</description>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="1"/>
+ </parameters>
+ </interface>
+ <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="output_4bits_preset">
+ <description>4 LEDs</description>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_4bits_tri_io" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_io_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_io_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_io_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_io_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_4bits_tri_io" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_io_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_io_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_io_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_io_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_4bits_tri_io" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_4bits_tri_io_0"/>
+ <pin_map port_index="1" component_pin="led_4bits_tri_io_1"/>
+ <pin_map port_index="2" component_pin="led_4bits_tri_io_2"/>
+ <pin_map port_index="3" component_pin="led_4bits_tri_io_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led_3bits" preset_proc="rgb_led_3bits_preset">
+ <description>RGB LED</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="IP" name="PWM" version="2.0" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_3bits_tri_io" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_3bits_tri_io_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_3bits_tri_io_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_3bits_tri_io_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_3bits_tri_io" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_3bits_tri_io_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_3bits_tri_io_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_3bits_tri_io_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_3bits_tri_io" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_3bits_tri_io_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_3bits_tri_io_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_3bits_tri_io_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="input_2bits_preset">
+ <description>2 Push Buttons</description>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="input_1bit_preset">
+ <description>Only BTN1</description>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Add "pio_32bits" ? -->
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="usb_uart_preset">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_flash_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="qspi_sck" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sck"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="qspi_sck" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sck"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="qspi_sck" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_sck"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <description>Pmod Connector JA</description>
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>12 MHz System Clock</description>
+ </component>
+ <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
+ <description>Configure BTN0 as System Reset button, active high</description>
+ </component>
+ <component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="rgb_led_3bits" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB LED 2 downto 0 (ordered RGB)</description>
+ </component>
+
+ <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push Buttons 1 to 0</description>
+ <component_modes>
+ <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+ <interfaces>
+ <interface name="push_buttons_2bits" order="0"/>
+ </interfaces>
+ </component_mode>
+ <component_mode name="1_btn" display_name="Only BTN1">
+ <interfaces>
+ <interface name="push_buttons_1bit" order="0"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB UART</description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ </components>
+ <jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+ </jtag_chains>
+ <connections>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="8" c1_end_index="8" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_led_4bits" component1="part0" component2="led_4bits">
+ <connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_rgb_led_3bits" component1="part0" component2="rgb_led_3bits">
+ <connection_map name="part0_rgb_led_3bits_1" c1_st_index="5" c1_end_index="7" c2_st_index="0" c2_end_index="2"/>
+ </connection>
+ <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
+ <connection_map name="part0_push_buttons_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="10" c1_end_index="11" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="18" c1_end_index="25" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ </connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml
new file mode 100644
index 000000000..ec304151c
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/part0_pins.xml
@@ -0,0 +1,37 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7s25csga225-1">
+ <pins>
+ <pin index="0" name="clk" iostandard="LVCMOS33" loc="M9"/> <!-- Schematic Name: GCLK -->
+
+ <pin index="1" name="led_4bits_tri_io_0" iostandard="LVCMOS33" loc="E2"/> <!-- Schematic Name: LED1 -->
+ <pin index="2" name="led_4bits_tri_io_1" iostandard="LVCMOS33" loc="K1"/> <!-- Schematic Name: LED2 -->
+ <pin index="3" name="led_4bits_tri_io_2" iostandard="LVCMOS33" loc="J1"/> <!-- Schematic Name: LED3 -->
+ <pin index="4" name="led_4bits_tri_io_3" iostandard="LVCMOS33" loc="E1"/> <!-- Schematic Name: LED4 -->
+
+ <pin index="5" name="rgb_led_3bits_tri_io_0" iostandard="LVCMOS33" loc="F1"/> <!-- Schematic Name: LED0_B -->
+ <pin index="6" name="rgb_led_3bits_tri_io_1" iostandard="LVCMOS33" loc="D3"/> <!-- Schematic Name: LED0_G -->
+ <pin index="7" name="rgb_led_3bits_tri_io_2" iostandard="LVCMOS33" loc="F2"/> <!-- Schematic Name: LED0_R -->
+
+ <pin index="8" name="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="D2"/> <!-- Schematic Name: BTN0 -->
+ <pin index="9" name="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="D1"/> <!-- Schematic Name: BTN1 -->
+
+ <pin index="10" name="usb_uart_txd" iostandard="LVCMOS33" loc="L12"/> <!-- Schematic Name: UART_RXD_OUT -->
+ <pin index="11" name="usb_uart_rxd" iostandard="LVCMOS33" loc="K15"/> <!-- Schematic Name: UART_TXD_IN -->
+
+ <pin index="12" name="qspi_db0" iostandard="LVCMOS33" loc="H14"/> <!-- Schematic Name: QSPI_DQ0 -->
+ <pin index="13" name="qspi_db1" iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: QSPI_DQ1 -->
+ <pin index="14" name="qspi_db2" iostandard="LVCMOS33" loc="J12"/> <!-- Schematic Name: QSPI_DQ2 -->
+ <pin index="15" name="qspi_db3" iostandard="LVCMOS33" loc="K13"/> <!-- Schematic Name: QSPI_DQ3 -->
+ <pin index="16" name="qspi_csn" iostandard="LVCMOS33" loc="L11"/> <!-- Schematic Name: QSPI_CS -->
+ <pin index="17" name="qspi_sck" iostandard="LVCMOS33" loc="K12"/> <!-- Schematic Name: QSPI_CS -->
+
+ <pin index="18" name="JA1" iostandard="LVCMOS33" loc="J2"/> <!-- Schematic Name: JA1 -->
+ <pin index="19" name="JA2" iostandard="LVCMOS33" loc="H2"/> <!-- Schematic Name: JA2 -->
+ <pin index="20" name="JA3" iostandard="LVCMOS33" loc="H4"/> <!-- Schematic Name: JA3 -->
+ <pin index="21" name="JA4" iostandard="LVCMOS33" loc="F3"/> <!-- Schematic Name: JA4 -->
+ <pin index="22" name="JA7" iostandard="LVCMOS33" loc="H3"/> <!-- Schematic Name: JA7 -->
+ <pin index="23" name="JA8" iostandard="LVCMOS33" loc="H1"/> <!-- Schematic Name: JA8 -->
+ <pin index="24" name="JA9" iostandard="LVCMOS33" loc="G1"/> <!-- Schematic Name: JA9 -->
+ <pin index="25" name="JA10" iostandard="LVCMOS33" loc="F4"/> <!-- Schematic Name: JA10 -->
+ </pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml
new file mode 100644
index 000000000..48d2ff04c
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod-s7-25/B.0/preset.xml
@@ -0,0 +1,307 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_4bits_preset">
+ <ip vendor="digilentinc.com" library="IP" name="PWM" version="2.0" ip_interface="PWM_GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.NUM_PWMS" value="4"/>
+ <user_parameter name="CONFIG.POLARITY" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="rgb_led_3bits_preset">
+ <ip vendor="digilentinc.com" library="IP" name="PWM" version="2.0" ip_interface="PWM_GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.NUM_PWMS" value="3"/>
+ <user_parameter name="CONFIG.POLARITY" value="\"0\""/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="input_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="input_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="usb_uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_flash_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml
new file mode 100644
index 000000000..dda21c75e
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/board.xml
@@ -0,0 +1,481 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+ <board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-15t" display_name="Cmod A7-15t" url="https://reference.digilentinc.com/cmod_a7" preset_file="preset.xml">
+<compatible_board_revisions>
+ <revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Cmod A7-15t</description>
+<components>
+ <component name="part0" display_name="Cmod A7-15t" type="fpga" part_name="xc7a15tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/cmod_a7">
+ <interfaces>
+ <interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
+ <description>512KB SRAM</description>
+ <port_maps>
+ <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_addr_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_addr_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_addr_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_addr_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_addr_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_addr_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_addr_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_addr_7"/>
+ <pin_map port_index="8" component_pin="cellular_ram_addr_8"/>
+ <pin_map port_index="9" component_pin="cellular_ram_addr_9"/>
+ <pin_map port_index="10" component_pin="cellular_ram_addr_10"/>
+ <pin_map port_index="11" component_pin="cellular_ram_addr_11"/>
+ <pin_map port_index="12" component_pin="cellular_ram_addr_12"/>
+ <pin_map port_index="13" component_pin="cellular_ram_addr_13"/>
+ <pin_map port_index="14" component_pin="cellular_ram_addr_14"/>
+ <pin_map port_index="15" component_pin="cellular_ram_addr_15"/>
+ <pin_map port_index="16" component_pin="cellular_ram_addr_16"/>
+ <pin_map port_index="17" component_pin="cellular_ram_addr_17"/>
+ <pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_oen"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_wen"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_ce_n"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_2bits_tri_o" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_2bits_tri_o" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">
+ <description>RGB LED</description>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Use BTN0 as System Reset, active high</description>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="1" />
+ </parameters>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <description>12 MHz Single-Ended System Clock</description>
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="12000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
+ <description>512KB SRAM</description>
+ </component>
+ <component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 1 to 0</description>
+ </component>
+ <component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB led 2 downto 0 [R G B]</description>
+ </component>
+ <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 1 to 0</description>
+ <component_modes>
+ <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+ <interfaces>
+ <interface name="push_buttons_2bits" order="0"/>
+ </interfaces>
+ </component_mode>
+ <component_mode name="1_btn" display_name="Just use BTN1">
+ <interfaces>
+ <interface name="push_buttons_1bit" order="0"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
+ <description>Configure BTN0 as System Reset button, active high</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>12 MHz System Clock</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB UART</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
+ <connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>
+ </connection>
+ <connection name="part0_led_2bits" component1="part0" component2="led_2bits">
+ <connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>
+ </connection>
+ <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
+ <connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml
new file mode 100644
index 000000000..02a3f5837
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/part0_pins.xml
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a15tcpg236-1">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
+ <pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
+ <pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
+ <pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
+ <pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
+ <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
+ <pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
+ <pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
+ <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
+ <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
+ <pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="45" name ="JA1" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="46" name ="JA2" iostandard="LVCMOS33" loc="G19"/>
+ <pin index="47" name ="JA3" iostandard="LVCMOS33" loc="N18"/>
+ <pin index="48" name ="JA4" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="49" name ="JA7" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="50" name ="JA8" iostandard="LVCMOS33" loc="H19"/>
+ <pin index="51" name ="JA9" iostandard="LVCMOS33" loc="J19"/>
+ <pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml
new file mode 100644
index 000000000..f37d2ecb4
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-15t/B.0/preset.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="sram_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_emc">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
+ <user_parameter name="CONFIG.C_MEM0_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="3000"/>
+ <user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="8000"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_3bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml
new file mode 100644
index 000000000..075e89767
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/board.xml
@@ -0,0 +1,481 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+ <board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-35t" display_name="Cmod A7-35t" url="https://reference.digilentinc.com/cmod_a7" preset_file="preset.xml">
+<compatible_board_revisions>
+ <revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Cmod A7-35t</description>
+<components>
+ <component name="part0" display_name="Cmod A7-35t" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/cmod_a7">
+ <interfaces>
+ <interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
+ <description>512KB SRAM</description>
+ <port_maps>
+ <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_addr_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_addr_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_addr_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_addr_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_addr_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_addr_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_addr_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_addr_7"/>
+ <pin_map port_index="8" component_pin="cellular_ram_addr_8"/>
+ <pin_map port_index="9" component_pin="cellular_ram_addr_9"/>
+ <pin_map port_index="10" component_pin="cellular_ram_addr_10"/>
+ <pin_map port_index="11" component_pin="cellular_ram_addr_11"/>
+ <pin_map port_index="12" component_pin="cellular_ram_addr_12"/>
+ <pin_map port_index="13" component_pin="cellular_ram_addr_13"/>
+ <pin_map port_index="14" component_pin="cellular_ram_addr_14"/>
+ <pin_map port_index="15" component_pin="cellular_ram_addr_15"/>
+ <pin_map port_index="16" component_pin="cellular_ram_addr_16"/>
+ <pin_map port_index="17" component_pin="cellular_ram_addr_17"/>
+ <pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_oen"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_wen"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_ce_n"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_2bits_tri_o" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_2bits_tri_o" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">
+ <description>RGB LED</description>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Use BTN0 as System Reset, active high</description>
+ <port_maps>
+ <port_map logical_port="RST" physical_port="reset_btn0" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="1" />
+ </parameters>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <description>12 MHz Single-Ended System Clock</description>
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="12000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
+ <description>512KB SRAM</description>
+ </component>
+ <component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 1 to 0</description>
+ </component>
+ <component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB led 2 downto 0 [R G B]</description>
+ </component>
+ <component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push buttons 1 to 0</description>
+ <component_modes>
+ <component_mode name="2_btns" display_name="2 Buttons (No Reset)">
+ <interfaces>
+ <interface name="push_buttons_2bits" order="0"/>
+ </interfaces>
+ </component_mode>
+ <component_mode name="1_btn" display_name="Just use BTN1">
+ <interfaces>
+ <interface name="push_buttons_1bit" order="0"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
+ <description>Configure BTN0 as System Reset button, active high</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>12 MHz System Clock</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB UART</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
+ <connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>
+ </connection>
+ <connection name="part0_led_2bits" component1="part0" component2="led_2bits">
+ <connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>
+ </connection>
+ <connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
+ <connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml
new file mode 100644
index 000000000..e4a2fead3
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/part0_pins.xml
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a35tcpg236-1">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
+ <pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
+ <pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
+ <pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
+ <pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
+ <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
+ <pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
+ <pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
+ <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
+ <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
+ <pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="45" name ="JA1" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="46" name ="JA2" iostandard="LVCMOS33" loc="G19"/>
+ <pin index="47" name ="JA3" iostandard="LVCMOS33" loc="N18"/>
+ <pin index="48" name ="JA4" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="49" name ="JA7" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="50" name ="JA8" iostandard="LVCMOS33" loc="H19"/>
+ <pin index="51" name ="JA9" iostandard="LVCMOS33" loc="J19"/>
+ <pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml
new file mode 100644
index 000000000..bb869c522
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cmod_a7-35t/B.0/preset.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="sram_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_emc">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
+ <user_parameter name="CONFIG.C_MEM0_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="3000"/>
+ <user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="8000"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_3bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml
new file mode 100644
index 000000000..325875efe
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/board.xml
@@ -0,0 +1,688 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-07s" display_name="Cora Z7-07S" url="http://www.digilentinc.com" preset_file="preset.xml" >
+ <compatible_board_revisions>
+ <revision id="0">B.0</revision>
+ </compatible_board_revisions>
+ <file_version>1.0</file_version>
+ <description>Cora Z7-07S</description>
+ <components>
+ <component name="part0" display_name="Cora Z7-07S" type="fpga" part_name="xc7z007sclg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="btns_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_2bits" preset_proc="input_2bits_preset">
+ <description>2 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_leds" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_leds" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_leds_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="shield_i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="shield_i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="shield_i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="shield_i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="shield_i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="shield_i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="shield_i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="shield_spi" preset_proc="shield_spi_preset">
+ <description>Shield SPI</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="shield_spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="shield_spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="shield_spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="shield_spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="shield_spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="shield_spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="shield_spi_sck_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_sck_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="shield_spi_sck_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_sck_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="shield_spi_sck_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_sck_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="shield_spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="shield_spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="shield_spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="user_dio" type="xilinx.com:interface:gpio_rtl:1.0" of_component="user_dio" preset_proc="user_dio_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="user_dio_tri_i" dir="in" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
+ <pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
+ <pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
+ <pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
+ <pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
+ <pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
+ <pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
+ <pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
+ <pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
+ <pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
+ <pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
+ <pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="user_dio_tri_o" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
+ <pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
+ <pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
+ <pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
+ <pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
+ <pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
+ <pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
+ <pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
+ <pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
+ <pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
+ <pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
+ <pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="user_dio_tri_t" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
+ <pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
+ <pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
+ <pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
+ <pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
+ <pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
+ <pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
+ <pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
+ <pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
+ <pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
+ <pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
+ <pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="btns_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 1 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="rgb_leds" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB LEDs 5 to 0 (3 bits per LED, ordered "RGBRGB")</description>
+ </component>
+ <component name="shield_i2c" display_name="Shield I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield I2C</description>
+ </component>
+ <component name="shield_spi" display_name="Shield SPI on J7" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="shield_dp0_dp13" display_name="Shield Pins 0 to 13" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP0 through DP13</description>
+ </component>
+ <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP26 through DP41</description>
+ </component>
+ <component name="user_dio" display_name="User Digital I/O on J1" type="chip" sub_type="led" major_group="GPIO">
+ <description>User Digital I/O pins 1 through 12</description>
+ </component>
+
+ </components>
+
+ <jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+ </jtag_chains>
+
+ <connections>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_btns_2bits" component1="part0" component2="btns_2bits">
+ <connection_map name="part0_btns_2bits_1" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_rgb_leds" component1="part0" component2="rgb_leds">
+ <connection_map name="part0_rgb_leds_1" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_shield_i2c" component1="part0" component2="shield_i2c">
+ <connection_map name="part0_shield_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+ <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="27" c1_end_index="40" c2_st_index="0" c2_end_index="13"/>
+ </connection>
+ <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+ <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="41" c1_end_index="56" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_shield_spi" component1="part0" component2="shield_spi">
+ <connection_map name="part0_shield_spi_1" c1_st_index="57" c1_end_index="60" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_user_dio" component1="part0" component2="user_dio">
+ <connection_map name="part0_user_dio_1" c1_st_index="61" c1_end_index="72" c2_st_index="0" c2_end_index="11"/>
+ </connection>
+ </connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml
new file mode 100644
index 000000000..b8156767d
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/part0_pins.xml
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z007sclg400-1">
+ <pins>
+ <pin index="0" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/> <!-- Schematic Name: SYSCLK -->
+
+ <pin index="1" name ="btns_2bits_tri_i_0" iostandard="LVCMOS33" loc="D20"/> <!-- Schematic Name: BTN0 -->
+ <pin index="2" name ="btns_2bits_tri_i_1" iostandard="LVCMOS33" loc="D19"/> <!-- Schematic Name: BTN1 -->
+
+ <pin index="3" name ="rgb_leds_tri_o_0" iostandard="LVCMOS33" loc="N15"/> <!-- Schematic Name: LED0_R -->
+ <pin index="4" name ="rgb_leds_tri_o_1" iostandard="LVCMOS33" loc="G17"/> <!-- Schematic Name: LED0_G -->
+ <pin index="5" name ="rgb_leds_tri_o_2" iostandard="LVCMOS33" loc="L15"/> <!-- Schematic Name: LED0_B -->
+ <pin index="6" name ="rgb_leds_tri_o_3" iostandard="LVCMOS33" loc="M15"/> <!-- Schematic Name: LED1_R -->
+ <pin index="7" name ="rgb_leds_tri_o_4" iostandard="LVCMOS33" loc="L14"/> <!-- Schematic Name: LED1_G -->
+ <pin index="8" name ="rgb_leds_tri_o_5" iostandard="LVCMOS33" loc="G14"/> <!-- Schematic Name: LED1_B -->
+
+ <pin index="9" name ="JA1" iostandard="LVCMOS33" loc="Y18"/> <!-- Schematic Name: JA1_P -->
+ <pin index="10" name ="JA2" iostandard="LVCMOS33" loc="Y19"/> <!-- Schematic Name: JA1_N -->
+ <pin index="11" name ="JA3" iostandard="LVCMOS33" loc="Y16"/> <!-- Schematic Name: JA2_P -->
+ <pin index="12" name ="JA4" iostandard="LVCMOS33" loc="Y17"/> <!-- Schematic Name: JA2_N -->
+ <pin index="13" name ="JA7" iostandard="LVCMOS33" loc="U18"/> <!-- Schematic Name: JA3_P -->
+ <pin index="14" name ="JA8" iostandard="LVCMOS33" loc="U19"/> <!-- Schematic Name: JA3_N -->
+ <pin index="15" name ="JA9" iostandard="LVCMOS33" loc="W18"/> <!-- Schematic Name: JA4_P -->
+ <pin index="16" name ="JA10" iostandard="LVCMOS33" loc="W19"/> <!-- Schematic Name: JA4_N -->
+
+ <pin index="17" name ="JB1" iostandard="LVCMOS33" loc="W14"/> <!-- Schematic Name: JB1_P -->
+ <pin index="18" name ="JB2" iostandard="LVCMOS33" loc="Y14"/> <!-- Schematic Name: JB1_N -->
+ <pin index="19" name ="JB3" iostandard="LVCMOS33" loc="T11"/> <!-- Schematic Name: JB2_P -->
+ <pin index="20" name ="JB4" iostandard="LVCMOS33" loc="T10"/> <!-- Schematic Name: JB2_N -->
+ <pin index="21" name ="JB7" iostandard="LVCMOS33" loc="V16"/> <!-- Schematic Name: JB3_P -->
+ <pin index="22" name ="JB8" iostandard="LVCMOS33" loc="W16"/> <!-- Schematic Name: JB3_N -->
+ <pin index="23" name ="JB9" iostandard="LVCMOS33" loc="V12"/> <!-- Schematic Name: JB4_P -->
+ <pin index="24" name ="JB10" iostandard="LVCMOS33" loc="W13"/> <!-- Schematic Name: JB4_N -->
+
+ <pin index="25" name ="shield_i2c_sda_i" iostandard="LVCMOS33" loc="P15"/> <!-- Schematic Name: CK_SDA -->
+ <pin index="26" name ="shield_i2c_scl_i" iostandard="LVCMOS33" loc="P16"/> <!-- Schematic Name: CK_SCL -->
+
+ <pin index="27" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="U14"/> <!-- Schematic Name: CK_IO0 -->
+ <pin index="28" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="V13"/> <!-- Schematic Name: CK_IO1 -->
+ <pin index="29" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="T14"/> <!-- Schematic Name: CK_IO2 -->
+ <pin index="30" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="T15"/> <!-- Schematic Name: CK_IO3 -->
+ <pin index="31" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V17"/> <!-- Schematic Name: CK_IO4 -->
+ <pin index="33" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="V18"/> <!-- Schematic Name: CK_IO5 -->
+ <pin index="33" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R17"/> <!-- Schematic Name: CK_IO6 -->
+ <pin index="34" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="R14"/> <!-- Schematic Name: CK_IO7 -->
+ <pin index="35" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="N18"/> <!-- Schematic Name: CK_IO8 -->
+ <pin index="36" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="M18"/> <!-- Schematic Name: CK_IO9 -->
+ <pin index="37" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="U15"/> <!-- Schematic Name: CK_IO10 -->
+ <pin index="38" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="K18"/> <!-- Schematic Name: CK_IO11 -->
+ <pin index="39" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="J18"/> <!-- Schematic Name: CK_IO12 -->
+ <pin index="40" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="G15"/> <!-- Schematic Name: CK_IO13 -->
+
+ <pin index="41" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="R16"/> <!-- Schematic Name: CK_IO26 -->
+ <pin index="42" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="U12"/> <!-- Schematic Name: CK_IO27 -->
+ <pin index="43" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="U13"/> <!-- Schematic Name: CK_IO28 -->
+ <pin index="44" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="V15"/> <!-- Schematic Name: CK_IO29 -->
+ <pin index="45" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="T16"/> <!-- Schematic Name: CK_IO30 -->
+ <pin index="46" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U17"/> <!-- Schematic Name: CK_IO31 -->
+ <pin index="47" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="T17"/> <!-- Schematic Name: CK_IO32 -->
+ <pin index="48" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="R18"/> <!-- Schematic Name: CK_IO33 -->
+ <pin index="49" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="P18"/> <!-- Schematic Name: CK_IO34 -->
+ <pin index="50" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N17"/> <!-- Schematic Name: CK_IO35 -->
+ <pin index="51" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="M17"/> <!-- Schematic Name: CK_IO36 -->
+ <pin index="52" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="L17"/> <!-- Schematic Name: CK_IO37 -->
+ <pin index="53" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="H17"/> <!-- Schematic Name: CK_IO38 -->
+ <pin index="54" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="H18"/> <!-- Schematic Name: CK_IO39 -->
+ <pin index="55" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="G18"/> <!-- Schematic Name: CK_IO40 -->
+ <pin index="56" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="L20"/> <!-- Schematic Name: CK_IO41 -->
+
+ <pin index="57" name ="shield_spi_miso_i" iostandard="LVCMOS33" loc="W15"/> <!-- Schematic Name: CK_MISO -->
+ <pin index="58" name ="shield_spi_mosi_i" iostandard="LVCMOS33" loc="T12"/> <!-- Schematic Name: CK_MOSI -->
+ <pin index="59" name ="shield_spi_sck_i" iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: CK_SCK -->
+ <pin index="60" name ="shield_spi_ss_i" iostandard="LVCMOS33" loc="F16"/> <!-- Schematic Name: CK_SS -->
+
+ <pin index="61" name ="user_dio_tri_i_0" iostandard="LVCMOS33" loc="L19"/> <!-- Schematic Name: USER_DIO1 -->
+ <pin index="62" name ="user_dio_tri_i_1" iostandard="LVCMOS33" loc="M19"/> <!-- Schematic Name: USER_DIO2 -->
+ <pin index="63" name ="user_dio_tri_i_2" iostandard="LVCMOS33" loc="N20"/> <!-- Schematic Name: USER_DIO3 -->
+ <pin index="64" name ="user_dio_tri_i_3" iostandard="LVCMOS33" loc="P20"/> <!-- Schematic Name: USER_DIO4 -->
+ <pin index="65" name ="user_dio_tri_i_4" iostandard="LVCMOS33" loc="P19"/> <!-- Schematic Name: USER_DIO5 -->
+ <pin index="66" name ="user_dio_tri_i_5" iostandard="LVCMOS33" loc="R19"/> <!-- Schematic Name: USER_DIO6 -->
+ <pin index="67" name ="user_dio_tri_i_6" iostandard="LVCMOS33" loc="T20"/> <!-- Schematic Name: USER_DIO7 -->
+ <pin index="68" name ="user_dio_tri_i_7" iostandard="LVCMOS33" loc="T19"/> <!-- Schematic Name: USER_DIO8 -->
+ <pin index="69" name ="user_dio_tri_i_8" iostandard="LVCMOS33" loc="U20"/> <!-- Schematic Name: USER_DIO9 -->
+ <pin index="70" name ="user_dio_tri_i_9" iostandard="LVCMOS33" loc="V20"/> <!-- Schematic Name: USER_DIO10 -->
+ <pin index="71" name ="user_dio_tri_i_10" iostandard="LVCMOS33" loc="W20"/> <!-- Schematic Name: USER_DIO11 -->
+ <pin index="72" name ="user_dio_tri_i_11" iostandard="LVCMOS33" loc="K19"/> <!-- Schematic Name: USER_DIO12 -->
+
+
+
+ </pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml
new file mode 100644
index 000000000..88b7edf10
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-07s/B.0/preset.xml
@@ -0,0 +1,590 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="15.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="15.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.USE_RESET" value="false"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.USE_RESET" value="false"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="input_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
+ <user_parameter name="CONFIG.C_GPO1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
+ <user_parameter name="CONFIG.C_GPO2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
+ <user_parameter name="CONFIG.C_GPO3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
+ <user_parameter name="CONFIG.C_GPO4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO1" value="1"/>
+ <user_parameter name="CONFIG.GPO1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO2" value="1"/>
+ <user_parameter name="CONFIG.GPO2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO3" value="1"/>
+ <user_parameter name="CONFIG.GPO3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO4" value="1"/>
+ <user_parameter name="CONFIG.GPO4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp13_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="user_dio_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml
new file mode 100644
index 000000000..0c1c3a91b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/board.xml
@@ -0,0 +1,688 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-10" display_name="Cora Z7-10" url="http://www.digilentinc.com" preset_file="preset.xml" >
+ <compatible_board_revisions>
+ <revision id="0">B.0</revision>
+ </compatible_board_revisions>
+ <file_version>1.0</file_version>
+ <description>Cora Z7-10</description>
+ <components>
+ <component name="part0" display_name="Cora Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="btns_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_2bits" preset_proc="input_2bits_preset">
+ <description>2 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_2bits_tri_i" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_2bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_2bits_tri_i_1"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_leds" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_leds" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_leds_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="shield_i2c">
+ <description>Shield I2C</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="shield_i2c_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="shield_i2c_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="shield_i2c_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="shield_i2c_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="shield_i2c_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="shield_i2c_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="shield_spi" preset_proc="shield_spi_preset">
+ <description>Shield SPI</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="shield_spi_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="shield_spi_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="shield_spi_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="shield_spi_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="shield_spi_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="shield_spi_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="shield_spi_sck_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_sck_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="shield_spi_sck_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_sck_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="shield_spi_sck_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_sck_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="shield_spi_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="shield_spi_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="shield_spi_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_spi_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
+ <pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
+ <pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
+ <pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
+ <pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
+ <pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
+ <pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
+ <pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
+ <pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
+ <pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
+ <pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
+ <pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
+ <pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
+ <pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
+ <pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
+ <pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="user_dio" type="xilinx.com:interface:gpio_rtl:1.0" of_component="user_dio" preset_proc="user_dio_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="user_dio_tri_i" dir="in" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
+ <pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
+ <pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
+ <pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
+ <pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
+ <pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
+ <pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
+ <pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
+ <pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
+ <pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
+ <pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
+ <pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="user_dio_tri_o" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
+ <pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
+ <pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
+ <pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
+ <pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
+ <pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
+ <pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
+ <pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
+ <pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
+ <pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
+ <pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
+ <pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="user_dio_tri_t" dir="out" left="11" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
+ <pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
+ <pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
+ <pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
+ <pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
+ <pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
+ <pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
+ <pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
+ <pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
+ <pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
+ <pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
+ <pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="btns_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 1 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="rgb_leds" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB LEDs 5 to 0 (3 bits per LED, ordered "RGBRGB")</description>
+ </component>
+ <component name="shield_i2c" display_name="Shield I2C on J3" type="chip" sub_type="mux" major_group="I2C">
+ <description>Shield I2C</description>
+ </component>
+ <component name="shield_spi" display_name="Shield SPI on J7" type="chip" sub_type="mux" major_group="SPI">
+ <description>Shield SPI</description>
+ </component>
+ <component name="shield_dp0_dp13" display_name="Shield Pins 0 to 13" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP0 through DP13</description>
+ </component>
+ <component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
+ <description>Digital Shield pins DP26 through DP41</description>
+ </component>
+ <component name="user_dio" display_name="User Digital I/O on J1" type="chip" sub_type="led" major_group="GPIO">
+ <description>User Digital I/O pins 1 through 12</description>
+ </component>
+
+ </components>
+
+ <jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+ </jtag_chains>
+
+ <connections>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_btns_2bits" component1="part0" component2="btns_2bits">
+ <connection_map name="part0_btns_2bits_1" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_rgb_leds" component1="part0" component2="rgb_leds">
+ <connection_map name="part0_rgb_leds_1" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_shield_i2c" component1="part0" component2="shield_i2c">
+ <connection_map name="part0_shield_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
+ <connection_map name="part0_shield_dp0_dp13_1" c1_st_index="27" c1_end_index="40" c2_st_index="0" c2_end_index="13"/>
+ </connection>
+ <connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
+ <connection_map name="part0_shield_dp26_dp41_1" c1_st_index="41" c1_end_index="56" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_shield_spi" component1="part0" component2="shield_spi">
+ <connection_map name="part0_shield_spi_1" c1_st_index="57" c1_end_index="60" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_user_dio" component1="part0" component2="user_dio">
+ <connection_map name="part0_user_dio_1" c1_st_index="61" c1_end_index="72" c2_st_index="0" c2_end_index="11"/>
+ </connection>
+ </connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml
new file mode 100644
index 000000000..34e336078
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/part0_pins.xml
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z010clg400-1">
+ <pins>
+ <pin index="0" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/> <!-- Schematic Name: SYSCLK -->
+
+ <pin index="1" name ="btns_2bits_tri_i_0" iostandard="LVCMOS33" loc="D20"/> <!-- Schematic Name: BTN0 -->
+ <pin index="2" name ="btns_2bits_tri_i_1" iostandard="LVCMOS33" loc="D19"/> <!-- Schematic Name: BTN1 -->
+
+ <pin index="3" name ="rgb_leds_tri_o_0" iostandard="LVCMOS33" loc="N15"/> <!-- Schematic Name: LED0_R -->
+ <pin index="4" name ="rgb_leds_tri_o_1" iostandard="LVCMOS33" loc="G17"/> <!-- Schematic Name: LED0_G -->
+ <pin index="5" name ="rgb_leds_tri_o_2" iostandard="LVCMOS33" loc="L15"/> <!-- Schematic Name: LED0_B -->
+ <pin index="6" name ="rgb_leds_tri_o_3" iostandard="LVCMOS33" loc="M15"/> <!-- Schematic Name: LED1_R -->
+ <pin index="7" name ="rgb_leds_tri_o_4" iostandard="LVCMOS33" loc="L14"/> <!-- Schematic Name: LED1_G -->
+ <pin index="8" name ="rgb_leds_tri_o_5" iostandard="LVCMOS33" loc="G14"/> <!-- Schematic Name: LED1_B -->
+
+ <pin index="9" name ="JA1" iostandard="LVCMOS33" loc="Y18"/> <!-- Schematic Name: JA1_P -->
+ <pin index="10" name ="JA2" iostandard="LVCMOS33" loc="Y19"/> <!-- Schematic Name: JA1_N -->
+ <pin index="11" name ="JA3" iostandard="LVCMOS33" loc="Y16"/> <!-- Schematic Name: JA2_P -->
+ <pin index="12" name ="JA4" iostandard="LVCMOS33" loc="Y17"/> <!-- Schematic Name: JA2_N -->
+ <pin index="13" name ="JA7" iostandard="LVCMOS33" loc="U18"/> <!-- Schematic Name: JA3_P -->
+ <pin index="14" name ="JA8" iostandard="LVCMOS33" loc="U19"/> <!-- Schematic Name: JA3_N -->
+ <pin index="15" name ="JA9" iostandard="LVCMOS33" loc="W18"/> <!-- Schematic Name: JA4_P -->
+ <pin index="16" name ="JA10" iostandard="LVCMOS33" loc="W19"/> <!-- Schematic Name: JA4_N -->
+
+ <pin index="17" name ="JB1" iostandard="LVCMOS33" loc="W14"/> <!-- Schematic Name: JB1_P -->
+ <pin index="18" name ="JB2" iostandard="LVCMOS33" loc="Y14"/> <!-- Schematic Name: JB1_N -->
+ <pin index="19" name ="JB3" iostandard="LVCMOS33" loc="T11"/> <!-- Schematic Name: JB2_P -->
+ <pin index="20" name ="JB4" iostandard="LVCMOS33" loc="T10"/> <!-- Schematic Name: JB2_N -->
+ <pin index="21" name ="JB7" iostandard="LVCMOS33" loc="V16"/> <!-- Schematic Name: JB3_P -->
+ <pin index="22" name ="JB8" iostandard="LVCMOS33" loc="W16"/> <!-- Schematic Name: JB3_N -->
+ <pin index="23" name ="JB9" iostandard="LVCMOS33" loc="V12"/> <!-- Schematic Name: JB4_P -->
+ <pin index="24" name ="JB10" iostandard="LVCMOS33" loc="W13"/> <!-- Schematic Name: JB4_N -->
+
+ <pin index="25" name ="shield_i2c_sda_i" iostandard="LVCMOS33" loc="P15"/> <!-- Schematic Name: CK_SDA -->
+ <pin index="26" name ="shield_i2c_scl_i" iostandard="LVCMOS33" loc="P16"/> <!-- Schematic Name: CK_SCL -->
+
+ <pin index="27" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="U14"/> <!-- Schematic Name: CK_IO0 -->
+ <pin index="28" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="V13"/> <!-- Schematic Name: CK_IO1 -->
+ <pin index="29" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="T14"/> <!-- Schematic Name: CK_IO2 -->
+ <pin index="30" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="T15"/> <!-- Schematic Name: CK_IO3 -->
+ <pin index="31" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V17"/> <!-- Schematic Name: CK_IO4 -->
+ <pin index="33" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="V18"/> <!-- Schematic Name: CK_IO5 -->
+ <pin index="33" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R17"/> <!-- Schematic Name: CK_IO6 -->
+ <pin index="34" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="R14"/> <!-- Schematic Name: CK_IO7 -->
+ <pin index="35" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="N18"/> <!-- Schematic Name: CK_IO8 -->
+ <pin index="36" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="M18"/> <!-- Schematic Name: CK_IO9 -->
+ <pin index="37" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="U15"/> <!-- Schematic Name: CK_IO10 -->
+ <pin index="38" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="K18"/> <!-- Schematic Name: CK_IO11 -->
+ <pin index="39" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="J18"/> <!-- Schematic Name: CK_IO12 -->
+ <pin index="40" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="G15"/> <!-- Schematic Name: CK_IO13 -->
+
+ <pin index="41" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="R16"/> <!-- Schematic Name: CK_IO26 -->
+ <pin index="42" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="U12"/> <!-- Schematic Name: CK_IO27 -->
+ <pin index="43" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="U13"/> <!-- Schematic Name: CK_IO28 -->
+ <pin index="44" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="V15"/> <!-- Schematic Name: CK_IO29 -->
+ <pin index="45" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="T16"/> <!-- Schematic Name: CK_IO30 -->
+ <pin index="46" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U17"/> <!-- Schematic Name: CK_IO31 -->
+ <pin index="47" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="T17"/> <!-- Schematic Name: CK_IO32 -->
+ <pin index="48" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="R18"/> <!-- Schematic Name: CK_IO33 -->
+ <pin index="49" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="P18"/> <!-- Schematic Name: CK_IO34 -->
+ <pin index="50" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N17"/> <!-- Schematic Name: CK_IO35 -->
+ <pin index="51" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="M17"/> <!-- Schematic Name: CK_IO36 -->
+ <pin index="52" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="L17"/> <!-- Schematic Name: CK_IO37 -->
+ <pin index="53" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="H17"/> <!-- Schematic Name: CK_IO38 -->
+ <pin index="54" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="H18"/> <!-- Schematic Name: CK_IO39 -->
+ <pin index="55" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="G18"/> <!-- Schematic Name: CK_IO40 -->
+ <pin index="56" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="L20"/> <!-- Schematic Name: CK_IO41 -->
+
+ <pin index="57" name ="shield_spi_miso_i" iostandard="LVCMOS33" loc="W15"/> <!-- Schematic Name: CK_MISO -->
+ <pin index="58" name ="shield_spi_mosi_i" iostandard="LVCMOS33" loc="T12"/> <!-- Schematic Name: CK_MOSI -->
+ <pin index="59" name ="shield_spi_sck_i" iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: CK_SCK -->
+ <pin index="60" name ="shield_spi_ss_i" iostandard="LVCMOS33" loc="F16"/> <!-- Schematic Name: CK_SS -->
+
+ <pin index="61" name ="user_dio_tri_i_0" iostandard="LVCMOS33" loc="L19"/> <!-- Schematic Name: USER_DIO1 -->
+ <pin index="62" name ="user_dio_tri_i_1" iostandard="LVCMOS33" loc="M19"/> <!-- Schematic Name: USER_DIO2 -->
+ <pin index="63" name ="user_dio_tri_i_2" iostandard="LVCMOS33" loc="N20"/> <!-- Schematic Name: USER_DIO3 -->
+ <pin index="64" name ="user_dio_tri_i_3" iostandard="LVCMOS33" loc="P20"/> <!-- Schematic Name: USER_DIO4 -->
+ <pin index="65" name ="user_dio_tri_i_4" iostandard="LVCMOS33" loc="P19"/> <!-- Schematic Name: USER_DIO5 -->
+ <pin index="66" name ="user_dio_tri_i_5" iostandard="LVCMOS33" loc="R19"/> <!-- Schematic Name: USER_DIO6 -->
+ <pin index="67" name ="user_dio_tri_i_6" iostandard="LVCMOS33" loc="T20"/> <!-- Schematic Name: USER_DIO7 -->
+ <pin index="68" name ="user_dio_tri_i_7" iostandard="LVCMOS33" loc="T19"/> <!-- Schematic Name: USER_DIO8 -->
+ <pin index="69" name ="user_dio_tri_i_8" iostandard="LVCMOS33" loc="U20"/> <!-- Schematic Name: USER_DIO9 -->
+ <pin index="70" name ="user_dio_tri_i_9" iostandard="LVCMOS33" loc="V20"/> <!-- Schematic Name: USER_DIO10 -->
+ <pin index="71" name ="user_dio_tri_i_10" iostandard="LVCMOS33" loc="W20"/> <!-- Schematic Name: USER_DIO11 -->
+ <pin index="72" name ="user_dio_tri_i_11" iostandard="LVCMOS33" loc="K19"/> <!-- Schematic Name: USER_DIO12 -->
+
+
+
+ </pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml
new file mode 100644
index 000000000..ea36e107b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/cora-z7-10/B.0/preset.xml
@@ -0,0 +1,590 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="15.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="15.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.USE_RESET" value="false"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.USE_RESET" value="false"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="input_2bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI3_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI4_SIZE" value="2"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
+ <user_parameter name="CONFIG.C_GPO1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
+ <user_parameter name="CONFIG.C_GPO2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
+ <user_parameter name="CONFIG.C_GPO3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
+ <user_parameter name="CONFIG.C_GPO4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO1" value="1"/>
+ <user_parameter name="CONFIG.GPO1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO2" value="1"/>
+ <user_parameter name="CONFIG.GPO2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO3" value="1"/>
+ <user_parameter name="CONFIG.GPO3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPO4" value="1"/>
+ <user_parameter name="CONFIG.GPO4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp0_dp13_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="shield_dp26_dp41_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="user_dio_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
+ <user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/board.xml
new file mode 100644
index 000000000..d2bbe887a
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/board.xml
@@ -0,0 +1,1643 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="genesys2" display_name="Genesys2" url="www.digilentinc.com/genesys2" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">H</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Genesys2</description>
+<components>
+ <component name="part0" display_name="Genesys2" type="fpga" part_name="xc7k325tffg900-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/genesys2">
+ <interfaces>
+ <interface mode="master" name="audio_codec_iic" type="xilinx.com:interface:iic_rtl:1.0" of_component="audio_codec_iic">
+ <description>I2C bus to communicate with the Audio Codec</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="aud_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="aud_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="aud_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="aud_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="aud_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="aud_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="aud_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="aud_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="aud_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="aud_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="aud_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="aud_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_8bits" preset_proc="dip_switches_8bits_preset">
+ <description>8 DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_8bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_8bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_8bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_8bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="dip_switches_8bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="dip_switches_8bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="dip_switches_8bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="dip_switches_8bits_tri_i_7"/>
+ </pin_maps>
+ </port_map>
+
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <description>HDMI DDC</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+ <description>HDMI Out</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="dspi" type="xilinx.com:interface:spi_rtl:1.0" of_component="dspi" preset_proc="dspi_preset">
+ <description>System Dual-SPI</description>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+ <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+ <port_maps>
+ <port_map logical_port="TD" physical_port="eth_rgmii_td" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_td_0"/>
+ <pin_map port_index="1" component_pin="eth_rgmii_td_1"/>
+ <pin_map port_index="2" component_pin="eth_rgmii_td_2"/>
+ <pin_map port_index="3" component_pin="eth_rgmii_td_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RD" physical_port="eth_rgmii_rd" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_rd_0"/>
+ <pin_map port_index="1" component_pin="eth_rgmii_rd_1"/>
+ <pin_map port_index="2" component_pin="eth_rgmii_rd_2"/>
+ <pin_map port_index="3" component_pin="eth_rgmii_rd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_CTL" physical_port="eth_rgmii_rx_ctl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_rx_ctl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_CTL" physical_port="eth_rgmii_tx_ctl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_tx_ctl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TXC" physical_port="eth_rgmii_txc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_txc"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXC" physical_port="eth_rgmii_rxc" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_rxc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
+ <description>Onboard Reset Button</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="phy_reset_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="phy_reset_n"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="iic_bus" type="xilinx.com:interface:iic_rtl:1.0" of_component="iic_bus">
+ <description>System I2C</description>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
+ <description>8 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_8bits_tri_o" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+ <description>5 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="0" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="sd_spi_mode" type="xilinx.com:interface:spi_rtl:1.0" of_component="sd_spi_mode" preset_proc="spi_preset">
+ <description>SD Card reader in SPI Mode</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="sd_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="sd_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="sd_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="sd_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="sd_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="sd_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="sd_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="sd_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="sd_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="sd_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="sd_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="sd_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sd_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!--<interface mode="master" name="usb_otg_master" type="xilinx.com:interface:ulpi_rtl:1.0" of_component="usb_otg_master">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="otg_clk_m" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_clk_m"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RST" physical_port="otg_rst_m" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_rst_m"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DIR" physical_port="otg_dir_m" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_dir_m"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="NEXT" physical_port="otg_next_m" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_next_m"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="STOP" physical_port="otg_stop_m" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_stop_m"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_I" physical_port="otg_data_i" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_data_i_0"/>
+ <pin_map port_index="1" component_pin="otg_data_i_1"/>
+ <pin_map port_index="2" component_pin="otg_data_i_2"/>
+ <pin_map port_index="3" component_pin="otg_data_i_3"/>
+ <pin_map port_index="4" component_pin="otg_data_i_4"/>
+ <pin_map port_index="5" component_pin="otg_data_i_5"/>
+ <pin_map port_index="6" component_pin="otg_data_i_6"/>
+ <pin_map port_index="7" component_pin="otg_data_i_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_O" physical_port="otg_data_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_data_i_0"/>
+ <pin_map port_index="1" component_pin="otg_data_i_1"/>
+ <pin_map port_index="2" component_pin="otg_data_i_2"/>
+ <pin_map port_index="3" component_pin="otg_data_i_3"/>
+ <pin_map port_index="4" component_pin="otg_data_i_4"/>
+ <pin_map port_index="5" component_pin="otg_data_i_5"/>
+ <pin_map port_index="6" component_pin="otg_data_i_6"/>
+ <pin_map port_index="7" component_pin="otg_data_i_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_T" physical_port="otg_data_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="otg_data_i_0"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>-->
+
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="SD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="SD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="SD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="SD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="SD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="SD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="SD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_diff_clock" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sys_diff_clock" preset_proc="sys_diff_clock_preset">
+ <parameters>
+ <parameter name="frequency" value="200000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk_n"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="audio_codec_iic" display_name="Audio Codec I2C" type="chip" sub_type="mux" major_group="Audio">
+ <description>I2C bus to communicate with the Audio Codec</description>
+ </component>
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>1 GB 1800Mt/s on-board DDR3 </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="1GB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_8bits" display_name="8 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 7 to 0</description>
+ </component>
+ <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI input (Requires Digilent's TMDS interface)</description>
+ <component_modes>
+ <component_mode name="HDMI_IN" display_name="HDMI In">
+ <interfaces>
+ <interface name="hdmi_in" order="0"/>
+ <interface name="hdmi_in_ddc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI in HPD (Connected to LD8)</description>
+ </component>
+ <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI Out (Requires Digilent's TMDS interface)</description>
+ </component>
+ <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI out HPD</description>
+ </component>
+ <component name="dspi" display_name="DSPI" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>Dual SPI</description>
+ </component>
+ <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>PHY Ethernet on the board</description>
+ <component_modes>
+ <component_mode name="rgmii" display_name="RGMII mode">
+ <interfaces>
+ <interface name="eth_rgmii" order="0"/>
+ <interface name="eth_mdio_mdc" order="1"/>
+ <interface name="phy_reset_out" order="2" optional="true"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="iic_bus" display_name="I2C" type="chip" sub_type="mux" major_group="I2C">
+ <description>I2C bus</description>
+ </component>
+ <component name="led_8bits" display_name="8 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 7 to 0</description>
+ </component>
+ <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+ <description>System Reset Button</description>
+ </component>
+ <component name="sd_spi_mode" display_name="SD Card (SPI)" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>SD Card in SPI Mode</description>
+ </component>
+ <!--<component name="usb_otg_master" display_name="USB OTG" type="chip" sub_type="uart" major_group="UART">
+ <description>USB OTG (Needs work)</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_usb2_device" order="0"/>
+ </preferred_ips>
+ </component>-->
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="sd" display_name="Micro SD Card" type="chip" sub_type="chip" major_group="External Memory">
+ <description>Micro SD Card Reader</description>
+ <component_modes>
+ <component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+ <component_modes>
+ <component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+ <interfaces>
+ <interface name="oled"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="oled"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+
+ <description>Onboard OLED (DISP1)</description>
+ </component>
+
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ </component>
+ <component name="sys_diff_clock" display_name="System differential clock" type="chip" sub_type="system_clock" major_group="Clock Sources" >
+ <description>3.3V LVDS differential 200 MHz oscillator used as system differential clock on the board</description>
+ <parameters>
+ <parameter name="frequency" value="200000000"/>
+ </parameters>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_audio_codec_iic" component1="part0" component2="audio_codec_iic">
+ <connection_map name="part0_audio_codec_iic_1" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
+ <connection_map name="part0_dip_switches_8bits_1" c1_st_index="4" c1_end_index="11" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+ <connection_map name="part0_hdmi_in_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+ <connection_map name="part0_hdmi_in_ddc" c1_st_index="89" c1_end_index="90" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+ <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+ <connection_map name="part0_hdmi_out_1" c1_st_index="81" c1_end_index="88" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+ <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="21" c1_end_index="21" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_dspi" component1="part0" component2="dspi">
+ <connection_map name="part0_dspi_1" c1_st_index="44" c1_end_index="77" c2_st_index="0" c2_end_index="33"/>
+ </connection>
+ <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+ <connection_map name="part0_eth_rgmii_1" c1_st_index="24" c1_end_index="35" c2_st_index="0" c2_end_index="11"/>
+ <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="22" c1_end_index="23" c2_st_index="0" c2_end_index="1"/>
+ <connection_map name="part0_eth_phy_reset_n" c1_st_index="80" c1_end_index="80" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_iic_bus" component1="part0" component2="iic_bus">
+ <connection_map name="part0_iic_bus_1" c1_st_index="71" c1_end_index="72" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_led_8bits" component1="part0" component2="led_8bits">
+ <connection_map name="part0_led_8bits_1" c1_st_index="36" c1_end_index="43" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+ <connection_map name="part0_push_buttons_5bits_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="64" c1_end_index="68" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="69" c1_end_index="69" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_sd_spi_mode" component1="part0" component2="sd_spi_mode">
+ <connection_map name="part0_sd_spi_mode_1" c1_st_index="73" c1_end_index="76" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <!--<connection name="part0_usb_otg_master" component1="part0" component2="usb_otg_master">
+ <connection_map name="part0_usb_otg_master_1" c1_st_index="46" c1_end_index="58" c2_st_index="0" c2_end_index="12"/>
+ </connection>-->
+
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sd" component1="part0" component2="sd">
+ <connection_map name="part0_ja_1" c1_st_index="129" c1_end_index="135" c2_st_index="0" c2_end_index="6"/>
+ </connection>
+ <connection name="part0_oled" component1="part0" component2="oled">
+ <connection_map name="part0_oled_1" c1_st_index="123" c1_end_index="128" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="78" c1_end_index="79" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_sysclk" component1="part0" component2="sys_diff_clock">
+ <connection_map name="part0_sys_clk_1" c1_st_index="2" c1_end_index="3" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/mig.prj
new file mode 100644
index 000000000..d619ab469
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/mig.prj
@@ -0,0 +1,160 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>system_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
+ <Version>2.3</Version>
+ <SystemClock>Differential</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>0</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-107</MemoryDevice>
+ <TimePeriod>2500</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>800</MMCM_VCO>
+ <MMCMClkOut0>1</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>32</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>15</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Clock>
+ <Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />
+ </System_Clock>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="5" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml
new file mode 100644
index 000000000..019602694
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/part0_pins.xml
@@ -0,0 +1,141 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7k325tffg900-2">
+<pins>
+ <pin index="0" name ="aud_scl_i" iostandard="LVCMOS18" loc="AE19"/>
+ <pin index="1" name ="aud_sda_i" iostandard="LVCMOS18" loc="AF18"/>
+ <pin index="2" name ="clk_n" iostandard="TMDS_33" loc="AD11"/>
+ <pin index="3" name ="clk_p" iostandard="TMDS_33" loc="AD12"/>
+ <pin index="4" name ="dip_switches_8bits_tri_i_0" iostandard="LVCMOS12" loc="G19"/>
+ <pin index="5" name ="dip_switches_8bits_tri_i_1" iostandard="LVCMOS12" loc="G25"/>
+ <pin index="6" name ="dip_switches_8bits_tri_i_2" iostandard="LVCMOS12" loc="H24"/>
+ <pin index="7" name ="dip_switches_8bits_tri_i_3" iostandard="LVCMOS12" loc="K19"/>
+ <pin index="8" name ="dip_switches_8bits_tri_i_4" iostandard="LVCMOS12" loc="N19"/>
+ <pin index="9" name ="dip_switches_8bits_tri_i_5" iostandard="LVCMOS12" loc="P19"/>
+ <pin index="10" name ="dip_switches_8bits_tri_i_6" iostandard="LVCMOS33" loc="P26"/>
+ <pin index="11" name ="dip_switches_8bits_tri_i_7" iostandard="LVCMOS33" loc="P27"/>
+ <pin index="12" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="AH29"/>
+ <pin index="13" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="AE28"/>
+ <pin index="14" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="AF28"/>
+ <pin index="15" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="AJ26"/>
+ <pin index="16" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="AG27"/>
+ <pin index="17" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="AH26"/>
+ <pin index="18" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="AK26"/>
+ <pin index="19" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="AG28"/>
+ <pin index="20" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="AH27"/>
+ <pin index="21" name ="hdmi_tx_hpd" iostandard="LVCMOS18" loc="AG29"/>
+ <pin index="22" name ="eth_mdc" iostandard="LVCMOS15" loc="AF12"/>
+ <pin index="23" name ="eth_mdio_i" iostandard="LVCMOS15" loc="AG12"/>
+ <pin index="24" name ="eth_rgmii_rd_0" iostandard="LVCMOS15" loc="AJ14"/>
+ <pin index="25" name ="eth_rgmii_rd_1" iostandard="LVCMOS15" loc="AH14"/>
+ <pin index="26" name ="eth_rgmii_rd_2" iostandard="LVCMOS15" loc="AK13"/>
+ <pin index="27" name ="eth_rgmii_rd_3" iostandard="LVCMOS15" loc="AJ13"/>
+ <pin index="28" name ="eth_rgmii_rxc" iostandard="LVCMOS15" loc="AG10"/>
+ <pin index="29" name ="eth_rgmii_rx_ctl" iostandard="LVCMOS15" loc="AH11"/>
+ <pin index="30" name ="eth_rgmii_td_0" iostandard="LVCMOS15" loc="AJ12"/>
+ <pin index="31" name ="eth_rgmii_td_1" iostandard="LVCMOS15" loc="AK11"/>
+ <pin index="32" name ="eth_rgmii_td_2" iostandard="LVCMOS15" loc="AJ11"/>
+ <pin index="33" name ="eth_rgmii_td_3" iostandard="LVCMOS15" loc="AK10"/>
+ <pin index="34" name ="eth_rgmii_txc" iostandard="LVCMOS15" loc="AE10"/>
+ <pin index="35" name ="eth_rgmii_tx_ctl" iostandard="LVCMOS15" loc="AK14"/>
+ <pin index="36" name ="led_8bits_tri_o_0" iostandard="LVCMOS33" loc="T28"/>
+ <pin index="37" name ="led_8bits_tri_o_1" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="38" name ="led_8bits_tri_o_2" iostandard="LVCMOS33" loc="U30"/>
+ <pin index="39" name ="led_8bits_tri_o_3" iostandard="LVCMOS33" loc="U29"/>
+ <pin index="40" name ="led_8bits_tri_o_4" iostandard="LVCMOS33" loc="V20"/>
+ <pin index="41" name ="led_8bits_tri_o_5" iostandard="LVCMOS33" loc="V26"/>
+ <pin index="42" name ="led_8bits_tri_o_6" iostandard="LVCMOS33" loc="W24"/>
+ <pin index="43" name ="led_8bits_tri_o_7" iostandard="LVCMOS33" loc="W23"/>
+ <pin index="44" name ="miso_i" iostandard="LVCMOS33" loc="W28"/>
+ <pin index="45" name ="mosi_i" iostandard="LVCMOS33" loc="W27"/>
+ <pin index="46" name ="otg_clk_m" iostandard="LVCMOS18" loc="AD18"/>
+ <pin index="47" name ="otg_data_i_0" iostandard="LVCMOS18" loc="AE14"/>
+ <pin index="48" name ="otg_data_i_1" iostandard="LVCMOS18" loc="AE15"/>
+ <pin index="49" name ="otg_data_i_2" iostandard="LVCMOS18" loc="AC15"/>
+ <pin index="50" name ="otg_data_i_3" iostandard="LVCMOS18" loc="AC16"/>
+ <pin index="51" name ="otg_data_i_4" iostandard="LVCMOS18" loc="AB15"/>
+ <pin index="52" name ="otg_data_i_5" iostandard="LVCMOS18" loc="AA15"/>
+ <pin index="53" name ="otg_data_i_6" iostandard="LVCMOS18" loc="AD14"/>
+ <pin index="54" name ="otg_data_i_7" iostandard="LVCMOS18" loc="AC14"/>
+ <pin index="55" name ="otg_dir_m" iostandard="LVCMOS18" loc="Y16"/>
+ <pin index="56" name ="otg_next_m" iostandard="LVCMOS18" loc="AA16"/>
+ <pin index="57" name ="otg_rst_m" iostandard="LVCMOS18" loc="AB14"/>
+ <pin index="58" name ="otg_stop_m" iostandard="LVCMOS18" loc="AA17"/>
+ <pin index="59" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS12" loc="E18"/>c
+ <pin index="60" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS12" loc="B19"/>u
+ <pin index="61" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS12" loc="M20"/>l
+ <pin index="62" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS12" loc="C19"/>r
+ <pin index="63" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS12" loc="M19"/>d
+ <pin index="64" name ="qspi_csn_i" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="65" name ="qspi_db0_i" iostandard="LVCMOS33" loc="P24"/>
+ <pin index="66" name ="qspi_db1_i" iostandard="LVCMOS33" loc="R25"/>
+ <pin index="67" name ="qspi_db2_i" iostandard="LVCMOS33" loc="R20"/>
+ <pin index="68" name ="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
+ <pin index="69" name ="reset" iostandard="LVCMOS33" loc="R19"/>
+ <pin index="70" name ="sclk_i" iostandard="LVCMOS33" loc="AD27"/>
+ <pin index="71" name ="scl_i" iostandard="LVCMOS33" loc="AE30"/>
+ <pin index="72" name ="sda_i" iostandard="LVCMOS33" loc="AF30"/>
+ <pin index="73" name ="sd_miso_i" iostandard="LVCMOS33" loc="R26"/>
+ <pin index="74" name ="sd_mosi_i" iostandard="LVCMOS33" loc="R29"/>
+ <pin index="75" name ="sd_sclk_i" iostandard="LVCMOS33" loc="R28"/>
+ <pin index="76" name ="sd_ss_i" iostandard="LVCMOS33" loc="T30"/>
+ <pin index="77" name ="ss_i" iostandard="LVCMOS33" loc="W29"/>
+ <pin index="78" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="Y20"/>
+ <pin index="79" name ="usb_uart_txd" iostandard="LVCMOS33" loc="Y23"/>
+ <pin index="80" name ="phy_reset_n" iostandard="LVCMOS33" loc="AH24"/>
+ <pin index="81" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="AA20"/>
+ <pin index="82" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="AB20"/>
+ <pin index="83" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="AC20"/>
+ <pin index="84" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="AA22"/>
+ <pin index="85" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="AB24"/>
+ <pin index="86" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="AC21"/>
+ <pin index="87" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="AA23"/>
+ <pin index="88" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="AC25"/>
+ <pin index="89" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="AJ28"/>
+ <pin index="90" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="AJ29"/>
+ <pin index="91" name ="JC1" iostandard="LVCMOS33" loc="AC26"/>
+ <pin index="92" name ="JC2" iostandard="LVCMOS33" loc="AJ27"/>
+ <pin index="93" name ="JC3" iostandard="LVCMOS33" loc="AH30"/>
+ <pin index="94" name ="JC4" iostandard="LVCMOS33" loc="AK29"/>
+ <pin index="95" name ="JC7" iostandard="LVCMOS33" loc="AD26"/>
+ <pin index="96" name ="JC8" iostandard="LVCMOS33" loc="AG30"/>
+ <pin index="97" name ="JC9" iostandard="LVCMOS33" loc="AK30"/>
+ <pin index="98" name ="JC10" iostandard="LVCMOS33" loc="AK28"/>
+ <pin index="99" name ="JD1" iostandard="LVCMOS33" loc="V27"/>
+ <pin index="100" name ="JD2" iostandard="LVCMOS33" loc="Y30"/>
+ <pin index="101" name ="JD3" iostandard="LVCMOS33" loc="V24"/>
+ <pin index="102" name ="JD4" iostandard="LVCMOS33" loc="W22"/>
+ <pin index="103" name ="JD7" iostandard="LVCMOS33" loc="U24"/>
+ <pin index="104" name ="JD8" iostandard="LVCMOS33" loc="Y26"/>
+ <pin index="105" name ="JD9" iostandard="LVCMOS33" loc="V22"/>
+ <pin index="106" name ="JD10" iostandard="LVCMOS33" loc="W21"/>
+ <pin index="107" name ="JB1" iostandard="LVCMOS33" loc="V29"/>
+ <pin index="108" name ="JB2" iostandard="LVCMOS33" loc="V30"/>
+ <pin index="109" name ="JB3" iostandard="LVCMOS33" loc="V25"/>
+ <pin index="110" name ="JB4" iostandard="LVCMOS33" loc="W26"/>
+ <pin index="111" name ="JB7" iostandard="LVCMOS33" loc="T25"/>
+ <pin index="112" name ="JB8" iostandard="LVCMOS33" loc="U25"/>
+ <pin index="113" name ="JB9" iostandard="LVCMOS33" loc="U22"/>
+ <pin index="114" name ="JB10" iostandard="LVCMOS33" loc="U23"/>
+ <pin index="115" name ="JA1" iostandard="LVCMOS33" loc="U27"/>
+ <pin index="116" name ="JA2" iostandard="LVCMOS33" loc="U28"/>
+ <pin index="117" name ="JA3" iostandard="LVCMOS33" loc="T26"/>
+ <pin index="118" name ="JA4" iostandard="LVCMOS33" loc="T27"/>
+ <pin index="119" name ="JA7" iostandard="LVCMOS33" loc="T22"/>
+ <pin index="120" name ="JA8" iostandard="LVCMOS33" loc="T23"/>
+ <pin index="121" name ="JA9" iostandard="LVCMOS33" loc="T20"/>
+ <pin index="122" name ="JA10" iostandard="LVCMOS33" loc="T21"/>
+ <pin index="123" name ="OLED2" iostandard="LVCMOS18" loc="Y15"/>
+ <pin index="124" name ="OLED4" iostandard="LVCMOS18" loc="AF17"/>
+ <pin index="125" name ="OLED7" iostandard="LVCMOS18" loc="AC17"/>
+ <pin index="126" name ="OLED8" iostandard="LVCMOS18" loc="AB17"/>
+ <pin index="127" name ="OLED9" iostandard="LVCMOS33" loc="AB22"/>
+ <pin index="128" name ="OLED10" iostandard="LVCMOS18" loc="AG17"/>
+ <pin index="129" name ="SD1" iostandard="LVCMOS33" loc="T30"/>
+ <pin index="130" name ="SD2" iostandard="LVCMOS33" loc="R29"/>
+ <pin index="131" name ="SD3" iostandard="LVCMOS33" loc="R26"/>
+ <pin index="132" name ="SD4" iostandard="LVCMOS33" loc="R28"/>
+ <pin index="133" name ="SD7" iostandard="LVCMOS33" loc="R30"/>
+ <pin index="134" name ="SD8" iostandard="LVCMOS33" loc="P29"/>
+ <pin index="135" name ="SD9" iostandard="LVCMOS33" loc="P28"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/preset.xml
new file mode 100644
index 000000000..70d72caef
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/genesys2/H/preset.xml
@@ -0,0 +1,312 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="oled_preset">
+ <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+ <user_parameters>
+ <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/>
+ <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="1"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_5bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="mii_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.Physical_Interface" value="MII"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_diff_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="hdmi_in_preset">
+ <ip vendor="digilentinc.com" library="ip" name="dvi2rgb">
+ <user_parameters>
+ <user_parameter name="CONFIG.kRstActiveHigh" value="false"/>
+ <user_parameter name="CONFIG.kClkRange" value="2"/>
+ <user_parameter name="CONFIG.kAddBUFG" value="false"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/board.xml
new file mode 100644
index 000000000..289590232
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/board.xml
@@ -0,0 +1,1563 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+ <board schema_version="2.0" vendor="digilentinc.com" name="nexys4" display_name="Nexys4" url="www.digilentinc.com/nexys4" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">B.1</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Nexys4</description>
+<components>
+ <component name="part0" display_name="Nexys4" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/nexys4">
+ <interfaces>
+ <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+ <description>Accelerometer control through SPI</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="emc_preset">
+ <description>16MB of Cell RAM</description>
+ <port_maps>
+ <port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="22" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_addr_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_addr_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_addr_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_addr_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_addr_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_addr_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_addr_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_addr_7"/>
+ <pin_map port_index="8" component_pin="cellular_ram_addr_8"/>
+ <pin_map port_index="9" component_pin="cellular_ram_addr_9"/>
+ <pin_map port_index="10" component_pin="cellular_ram_addr_10"/>
+ <pin_map port_index="11" component_pin="cellular_ram_addr_11"/>
+ <pin_map port_index="12" component_pin="cellular_ram_addr_12"/>
+ <pin_map port_index="13" component_pin="cellular_ram_addr_13"/>
+ <pin_map port_index="14" component_pin="cellular_ram_addr_14"/>
+ <pin_map port_index="15" component_pin="cellular_ram_addr_15"/>
+ <pin_map port_index="16" component_pin="cellular_ram_addr_16"/>
+ <pin_map port_index="17" component_pin="cellular_ram_addr_17"/>
+ <pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
+ <pin_map port_index="19" component_pin="cellular_ram_addr_19"/>
+ <pin_map port_index="20" component_pin="cellular_ram_addr_20"/>
+ <pin_map port_index="21" component_pin="cellular_ram_addr_21"/>
+ <pin_map port_index="22" component_pin="cellular_ram_addr_22"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_i_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_i_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_i_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_i_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_i_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_i_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_i_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_i_7"/>
+ <pin_map port_index="8" component_pin="cellular_ram_dq_i_8"/>
+ <pin_map port_index="9" component_pin="cellular_ram_dq_i_9"/>
+ <pin_map port_index="10" component_pin="cellular_ram_dq_i_10"/>
+ <pin_map port_index="11" component_pin="cellular_ram_dq_i_11"/>
+ <pin_map port_index="12" component_pin="cellular_ram_dq_i_12"/>
+ <pin_map port_index="13" component_pin="cellular_ram_dq_i_13"/>
+ <pin_map port_index="14" component_pin="cellular_ram_dq_i_14"/>
+ <pin_map port_index="15" component_pin="cellular_ram_dq_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_i_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_i_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_i_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_i_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_i_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_i_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_i_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_i_7"/>
+ <pin_map port_index="8" component_pin="cellular_ram_dq_i_8"/>
+ <pin_map port_index="9" component_pin="cellular_ram_dq_i_9"/>
+ <pin_map port_index="10" component_pin="cellular_ram_dq_i_10"/>
+ <pin_map port_index="11" component_pin="cellular_ram_dq_i_11"/>
+ <pin_map port_index="12" component_pin="cellular_ram_dq_i_12"/>
+ <pin_map port_index="13" component_pin="cellular_ram_dq_i_13"/>
+ <pin_map port_index="14" component_pin="cellular_ram_dq_i_14"/>
+ <pin_map port_index="15" component_pin="cellular_ram_dq_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_dq_i_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_dq_i_1"/>
+ <pin_map port_index="2" component_pin="cellular_ram_dq_i_2"/>
+ <pin_map port_index="3" component_pin="cellular_ram_dq_i_3"/>
+ <pin_map port_index="4" component_pin="cellular_ram_dq_i_4"/>
+ <pin_map port_index="5" component_pin="cellular_ram_dq_i_5"/>
+ <pin_map port_index="6" component_pin="cellular_ram_dq_i_6"/>
+ <pin_map port_index="7" component_pin="cellular_ram_dq_i_7"/>
+ <pin_map port_index="8" component_pin="cellular_ram_dq_i_8"/>
+ <pin_map port_index="9" component_pin="cellular_ram_dq_i_9"/>
+ <pin_map port_index="10" component_pin="cellular_ram_dq_i_10"/>
+ <pin_map port_index="11" component_pin="cellular_ram_dq_i_11"/>
+ <pin_map port_index="12" component_pin="cellular_ram_dq_i_12"/>
+ <pin_map port_index="13" component_pin="cellular_ram_dq_i_13"/>
+ <pin_map port_index="14" component_pin="cellular_ram_dq_i_14"/>
+ <pin_map port_index="15" component_pin="cellular_ram_dq_i_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="ADV_LDN" physical_port="cellular_ram_adv_ldn" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_adv_ldn"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_oen"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_wen"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_ce_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CRE" physical_port="cellular_ram_cre" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_cre"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="BEN" physical_port="cellular_ram_ben" dir="inout" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_ben_0"/>
+ <pin_map port_index="1" component_pin="cellular_ram_ben_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="WAIT" physical_port="cellular_ram_wait" dir="inout">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="cellular_ram_wait"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+ <description>16 DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/>
+ <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/>
+ <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/>
+ <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/>
+ <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/>
+ <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/>
+ <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/>
+ <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/>
+ <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+ <description>Dual 7 Seg LED Segments</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="dual_seven_seg_led_disp_tri_o" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="eth_mdio_mdc">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_rmii" type="xilinx.com:interface:rmii_rtl:1.0" of_component="eth_rmii">
+ <description>Primary interface to communicate with ethernet phy in RMII mode. </description>
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="eth_rmii_txd" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_txd_0"/>
+ <pin_map port_index="1" component_pin="eth_rmii_txd_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXD" physical_port="eth_rmii_rxd" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_rxd_0"/>
+ <pin_map port_index="1" component_pin="eth_rmii_rxd_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_EN" physical_port="eth_rmii_tx_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_tx_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_ER" physical_port="eth_rmii_rx_er" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_rx_er"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CRS_DV" physical_port="eth_rmii_crs_dv" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_crs_dv"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+ <description>16 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_16bits_tri_o" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+ <description>5 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="0" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+ <description>7 Segment Display Anodes</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="seven_seg_led_an_tri_o" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+ <description>Temperature Sensor connected to I2C</description>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="SD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="SD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="SD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="SD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="SD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="SD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="SD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="SD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="SD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="SD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+
+ </component>
+ <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+ <description>Accelerometer controlled through SPI</description>
+ </component>
+ <component name="cellular_ram" display_name="Block RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
+ <description>16MB Cell RAM</description>
+ </component>
+ <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>16 Switches</description>
+ </component>
+ <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+ <description>7 Segment Display Segment Control</description>
+ </component>
+ <component name="eth_rmii" display_name="Ethernet RMII" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>Ethernet RMII Signals</description>
+ </component>
+ <component name="eth_mdio_mdc" display_name="Ethernet MDIO MDC" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>Ethernet MDIO/MDC Signals</description>
+ </component>
+ <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>16 LEDs</description>
+ </component>
+ <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+ <description>Onboard Reset Button</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>2 RGB LEDs</description>
+ </component>
+ <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+ <description>7 Segment Display Anodes</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+ <description>100 MHz Single-Ended System Clock</description>
+ </component>
+ <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+ <description>SPI Controlled Temperature Sensor</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JXADC</description>
+ </component>
+ <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+ <component_modes>
+ <component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+ <description>Onboard MicroSD Card Slot</description>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+ <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
+ <connection_map name="part0_cellular_ram_1" c1_st_index="4" c1_end_index="50" c2_st_index="0" c2_end_index="46"/>
+ </connection>
+ <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+ <connection_map name="part0_dip_switches_16bits_1" c1_st_index="52" c1_end_index="67" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+ <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="68" c1_end_index="75" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_rmii" component1="part0" component2="eth_rmii">
+ <connection_map name="part0_eth_rmii_1" c1_st_index="78" c1_end_index="84" c2_st_index="0" c2_end_index="6"/>
+ </connection>
+ <connection name="part0_mdio_mdc" component1="part0" component2="eth_mdio_mdc">
+ <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="76" c1_end_index="77" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+ <connection_map name="part0_led_16bits_1" c1_st_index="85" c1_end_index="100" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+ <connection_map name="part0_push_buttons_5bits_1" c1_st_index="101" c1_end_index="105" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="106" c1_end_index="110" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="112" c1_end_index="112" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="113" c1_end_index="118" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+ <connection_map name="part0_seven_seg_led_an_1" c1_st_index="119" c1_end_index="126" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="51" c1_end_index="51" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+ <connection_map name="part0_temp_sensor_1" c1_st_index="127" c1_end_index="128" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="129" c1_end_index="130" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="131" c1_end_index="138" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="139" c1_end_index="146" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="147" c1_end_index="154" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="155" c1_end_index="162" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jxadc" component1="part0" component2="jxadc">
+ <connection_map name="part0_jxadc_1" c1_st_index="163" c1_end_index="170" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sd" component1="part0" component2="sd">
+ <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml
new file mode 100644
index 000000000..8b335ee91
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/part0_pins.xml
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+ <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="D13"/>
+ <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="B14"/>
+ <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="C15"/>
+ <pin index="4" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="5" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="6" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="7" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="8" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="9" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="K15"/>
+ <pin index="10" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="11" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="12" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="13" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="14" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="15" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="16" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="17" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="18" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="19" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="20" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="21" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="22" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="23" name ="cellular_ram_addr_19" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="24" name ="cellular_ram_addr_20" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="25" name ="cellular_ram_addr_21" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="26" name ="cellular_ram_addr_22" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="27" name ="cellular_ram_adv_ldn" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="28" name ="cellular_ram_ben_0" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="29" name ="cellular_ram_ben_1" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="31" name ="cellular_ram_cre" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="32" name ="cellular_ram_dq_i_0" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="33" name ="cellular_ram_dq_i_1" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="34" name ="cellular_ram_dq_i_2" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="35" name ="cellular_ram_dq_i_3" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="36" name ="cellular_ram_dq_i_4" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="37" name ="cellular_ram_dq_i_5" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="38" name ="cellular_ram_dq_i_6" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="39" name ="cellular_ram_dq_i_7" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="40" name ="cellular_ram_dq_i_8" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="41" name ="cellular_ram_dq_i_9" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="42" name ="cellular_ram_dq_i_10" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="43" name ="cellular_ram_dq_i_11" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="44" name ="cellular_ram_dq_i_12" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="45" name ="cellular_ram_dq_i_13" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="46" name ="cellular_ram_dq_i_14" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="47" name ="cellular_ram_dq_i_15" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="48" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="49" name ="cellular_ram_wait" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="50" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="51" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+ <pin index="52" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="U9"/>
+ <pin index="53" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="U8"/>
+ <pin index="54" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="R7"/>
+ <pin index="55" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R6"/>
+ <pin index="56" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R5"/>
+ <pin index="57" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="58" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="V6"/>
+ <pin index="59" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="V5"/>
+ <pin index="60" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS33" loc="U4"/>
+ <pin index="61" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS33" loc="V2"/>
+ <pin index="62" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="U2"/>
+ <pin index="63" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T3"/>
+ <pin index="64" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="T1"/>
+ <pin index="65" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="R3"/>
+ <pin index="66" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="P3"/>
+ <pin index="67" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="P4"/>
+ <pin index="68" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="L3"/>
+ <pin index="69" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="N1"/>
+ <pin index="70" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="L5"/>
+ <pin index="71" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="L4"/>
+ <pin index="72" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="K3"/>
+ <pin index="73" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="M2"/>
+ <pin index="74" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L6"/>
+ <pin index="75" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="M4"/>
+ <pin index="76" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
+ <pin index="77" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
+ <pin index="78" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
+ <pin index="79" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="D10"/>
+ <pin index="80" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="81" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
+ <pin index="82" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="83" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
+ <pin index="84" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
+ <pin index="85" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="T8"/>
+ <pin index="86" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="V9"/>
+ <pin index="87" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="R8"/>
+ <pin index="88" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="T6"/>
+ <pin index="89" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="T5"/>
+ <pin index="90" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="T4"/>
+ <pin index="91" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="92" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U6"/>
+ <pin index="93" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V4"/>
+ <pin index="94" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="U3"/>
+ <pin index="95" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="V1"/>
+ <pin index="96" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="R1"/>
+ <pin index="97" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="P5"/>
+ <pin index="98" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="U1"/>
+ <pin index="99" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="R2"/>
+ <pin index="100" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="P2"/>
+ <pin index="101" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="102" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="103" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="104" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="105" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="E16"/>
+ <pin index="106" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="107" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="108" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="109" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="110" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="111" name ="qspi_sck_i" iostandard="LVCMOS33" loc="E9"/>
+ <pin index="112" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+ <pin index="113" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="K5"/>
+ <pin index="114" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
+ <pin index="115" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F6"/>
+ <pin index="116" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="K6"/>
+ <pin index="117" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="118" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="119" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="N6"/>
+ <pin index="120" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="M6"/>
+ <pin index="121" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="M3"/>
+ <pin index="122" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="N5"/>
+ <pin index="123" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="N2"/>
+ <pin index="124" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="N4"/>
+ <pin index="125" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="L1"/>
+ <pin index="126" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="M1"/>
+ <pin index="127" name ="temp_scl_i" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="128" name ="temp_sda_i" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="129" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+ <pin index="130" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+ <pin index="131" name ="JA1" iostandard="LVCMOS33" loc="B13"/>
+ <pin index="132" name ="JA2" iostandard="LVCMOS33" loc="F14"/>
+ <pin index="133" name ="JA3" iostandard="LVCMOS33" loc="D17"/>
+ <pin index="134" name ="JA4" iostandard="LVCMOS33" loc="E17"/>
+ <pin index="135" name ="JA7" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="136" name ="JA8" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="137" name ="JA9" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="138" name ="JA10" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="139" name ="JB1" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="140" name ="JB2" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="141" name ="JB3" iostandard="LVCMOS33" loc="V11"/>
+ <pin index="142" name ="JB4" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="143" name ="JB7" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="144" name ="JB8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="145" name ="JB9" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="146" name ="JB10" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="147" name ="JC1" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="148" name ="JC2" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="149" name ="JC3" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="150" name ="JC4" iostandard="LVCMOS33" loc="J4"/>
+ <pin index="151" name ="JC7" iostandard="LVCMOS33" loc="K1"/>
+ <pin index="152" name ="JC8" iostandard="LVCMOS33" loc="E6"/>
+ <pin index="153" name ="JC9" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="154" name ="JC10" iostandard="LVCMOS33" loc="G6"/>
+ <pin index="155" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+ <pin index="156" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+ <pin index="157" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+ <pin index="158" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="159" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+ <pin index="160" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+ <pin index="161" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+ <pin index="162" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+ <pin index="163" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+ <pin index="164" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+ <pin index="165" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="166" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="167" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="168" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+ <pin index="169" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+ <pin index="170" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+ <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+ <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+ <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+ <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+ <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+ <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+ <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml
new file mode 100644
index 000000000..34a52f469
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4/B.1/preset.xml
@@ -0,0 +1,373 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="emc_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_emc">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_TWPH_PS_MEM_0" value="10000"/>
+ <user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="55000"/>
+ <user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="85000"/>
+ <user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
+ <user_parameter name="CONFIG.C_TPACC_PS_FLASH_0" value="70000"/>
+ <user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="70000"/>
+ <user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="70000"/>
+ <user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_5bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml
new file mode 100644
index 000000000..ab788e174
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/board.xml
@@ -0,0 +1,1455 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys4_ddr" display_name="Nexys4 DDR" url="www.digilentinc.com/nexys4" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">C.1</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Nexys4 DDR</description>
+<components>
+ <component name="part0" display_name="Nexys4 DDR" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/nexys4">
+ <interfaces>
+ <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+ <description>Accelerometer control through SPI</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="acl_miso_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="acl_miso_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="acl_miso_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_miso_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="acl_mosi_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="acl_mosi_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="acl_mosi_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_mosi_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_sclk_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_ss_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="acl_ss_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset">
+ <description>DDR2 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+ <description>16 DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/>
+ <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/>
+ <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/>
+ <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/>
+ <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/>
+ <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/>
+ <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/>
+ <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/>
+ <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+ <description>Dual 7 Seg LED Segments</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="dual_seven_seg_led_disp_tri_o" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/>
+ <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/>
+ <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/>
+ <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/>
+ <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/>
+ <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/>
+ <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/>
+ <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="eth_mdio_mdc">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_rmii" type="xilinx.com:interface:rmii_rtl:1.0" of_component="eth_rmii">
+ <description>Primary interface to communicate with ethernet phy in RMII mode. </description>
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="eth_rmii_txd" dir="out" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_txd_0"/>
+ <pin_map port_index="1" component_pin="eth_rmii_txd_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXD" physical_port="eth_rmii_rxd" dir="in" left="1" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_rxd_0"/>
+ <pin_map port_index="1" component_pin="eth_rmii_rxd_1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_EN" physical_port="eth_rmii_tx_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_tx_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_ER" physical_port="eth_rmii_rx_er" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_rx_er"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CRS_DV" physical_port="eth_rmii_crs_dv" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rmii_crs_dv"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+ <description>16 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_16bits_tri_o" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+ <description>5 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="0" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+ <description>7 Segment Display Anodes</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
+ <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
+ <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
+ <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
+ <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/>
+ <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/>
+ <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/>
+ <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+ <description>Temperature Sensor connected to I2C</description>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_sda_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_scl_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="temp_scl_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rts"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_cts"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="SD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="SD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="SD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="SD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="SD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="SD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="SD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="SD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="SD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="SD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+ <description>Accelerometer controlled through SPI</description>
+ </component>
+ <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>256 MB Onboard DDR Memory </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr2"/>
+ <parameter name="size" value="256MB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>16 Switches</description>
+ </component>
+ <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+ <description>7 Segment Display Segment Control</description>
+ </component>
+ <component name="eth_rmii" display_name="Ethernet RMII" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>Ethernet RMII Signals</description>
+ </component>
+ <component name="eth_mdio_mdc" display_name="Ethernet MDIO MDC" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>Ethernet MDIO/MDC Signals</description>
+ </component>
+ <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>16 LEDs</description>
+ </component>
+ <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+ <description>Onboard Reset Button</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>2 RGB LEDs</description>
+ </component>
+ <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+ <description>7 Segment Display Anodes</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+ <description>100 MHz Single-Ended System Clock</description>
+ </component>
+ <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+ <description>SPI Controlled Temperature Sensor</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JXADC</description>
+ </component>
+ <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+ <component_modes>
+ <component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+ <description>Onboard MicroSD Card Slot</description>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+ <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+ <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+ <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_eth_mdio_mdc" component1="part0" component2="eth_mdio_mdc">
+ <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="29" c1_end_index="30" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_eth_rmii" component1="part0" component2="eth_rmii">
+ <connection_map name="part0_eth_rmii_1" c1_st_index="31" c1_end_index="37" c2_st_index="0" c2_end_index="6"/>
+ </connection>
+ <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+ <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+ <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+ <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+ <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+ <connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jxadc" component1="part0" component2="jxadc">
+ <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sd" component1="part0" component2="sd">
+ <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+
+
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/mig.prj
new file mode 100644
index 000000000..254931c3b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/mig.prj
@@ -0,0 +1,128 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_2</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
+ <Version>2.2</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>
+ <TimePeriod>3077</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>199.995</InputClkFreq>
+ <UIExtraClocks>1</UIExtraClocks>
+ <MMCM_VCO>1200</MMCM_VCO>
+ <MMCMClkOut0>12.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>13</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <C0_MEM_SIZE>134217728</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" name="ddr2_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" name="ddr2_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" name="ddr2_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" name="ddr2_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" name="ddr2_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" name="ddr2_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" name="ddr2_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" name="ddr2_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" name="ddr2_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" name="ddr2_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" name="ddr2_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" name="ddr2_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" name="ddr2_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" name="ddr2_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" name="ddr2_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" name="ddr2_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" name="ddr2_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" name="ddr2_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" name="ddr2_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" name="ddr2_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" name="ddr2_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" name="ddr2_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" name="ddr2_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" name="ddr2_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" name="ddr2_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" name="ddr2_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" name="ddr2_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" name="ddr2_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" name="ddr2_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" name="ddr2_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" name="ddr2_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" name="ddr2_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" name="ddr2_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" name="ddr2_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" name="ddr2_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" name="ddr2_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" name="ddr2_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" name="ddr2_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" name="ddr2_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" name="ddr2_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" name="ddr2_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" name="ddr2_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" name="ddr2_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" name="ddr2_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" name="ddr2_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" name="ddr2_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="10" trefi="7.8" tfaw="45" trtp="7.5" trfc="127.5" trp="12.5" tras="40" trcd="15" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8</mrBurstLength>
+ <mrBurstType name="Burst Type" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="PD Mode" >Fast exit</mrPdMode>
+ <mrWriteRecovery name="Write Recovery" >5</mrWriteRecovery>
+ <emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable>
+ <emrOutputDriveStrength name="Output Drive Strength" >Fullstrength</emrOutputDriveStrength>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrCKSelection name="Memory Clock Selection" >1</emrCKSelection>
+ <emrRTT name="RTT (nominal) - ODT" >50ohms</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="OCD Operation" >OCD Exit</emrOCD>
+ <emrDQS name="DQS# Enable" >Enable</emrDQS>
+ <emrRDQS name="RDQS Enable" >Disable</emrRDQS>
+ <emrOutputs name="Outputs" >Enable</emrOutputs>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml
new file mode 100644
index 000000000..0ae3a724d
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/part0_pins.xml
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+ <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+ <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+ <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+ <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+ <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+ <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+ <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="29" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
+ <pin index="30" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
+ <pin index="31" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
+ <pin index="32" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="33" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="D10"/>
+ <pin index="34" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
+ <pin index="35" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="36" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
+ <pin index="37" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
+ <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+ <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+ <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+ <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+ <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+ <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+ <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+ <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+ <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+ <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+ <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+ <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+ <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+ <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+ <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+ <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+ <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+ <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+ <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="99" name ="JC1" iostandard="LVCMOS33" loc="K1"/>
+ <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+ <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+ <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+ <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+ <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+ <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+ <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+ <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+ <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+ <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+ <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+ <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+ <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+ <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+ <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+ <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+ <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+ <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+ <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+ <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+ <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+ <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+ <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+ <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+ <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+ <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+ <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+ <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml
new file mode 100644
index 000000000..4496b8b62
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys4_ddr/C.1/preset.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr2_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_5bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_6bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/board.xml
new file mode 100644
index 000000000..16c3c5d1c
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/board.xml
@@ -0,0 +1,1332 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys_video" display_name="Nexys Video" url="www.digilentinc.com/nexysvideo" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Nexys Video</description>
+<components>
+ <component name="part0" display_name="Nexys Video" type="fpga" part_name="xc7a200tsbg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/nexysvideo">
+ <interfaces>
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 board interface, it can use MIG IP for connection.</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <interface mode="master" name="dip_switches_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_8bits" preset_proc="dip_switches_8bits_preset">
+ <description>8 DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_8bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_8bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_8bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_8bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="dip_switches_8bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="dip_switches_8bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="dip_switches_8bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="dip_switches_8bits_tri_i_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+ <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+ <port_maps>
+ <port_map logical_port="TD" physical_port="eth_txd" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_txd_0"/>
+ <pin_map port_index="1" component_pin="eth_txd_1"/>
+ <pin_map port_index="2" component_pin="eth_txd_2"/>
+ <pin_map port_index="3" component_pin="eth_txd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_CTL" physical_port="eth_tx_ctl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_ctl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TXC" physical_port="eth_tx_clk" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_tx_clk"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RD" physical_port="eth_rxd" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rxd_0"/>
+ <pin_map port_index="1" component_pin="eth_rxd_1"/>
+ <pin_map port_index="2" component_pin="eth_rxd_2"/>
+ <pin_map port_index="3" component_pin="eth_rxd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_CTL" physical_port="eth_rx_ctl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_ctl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXC" physical_port="eth_rx_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rx_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
+ <description>Onboard Reset Button</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="phy_reset_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="phy_reset_n"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="led_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_8bits" preset_proc="led_8bits_preset">
+ <description>8 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_8bits_tri_o" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_8bits_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+ <description>5 Push Buttons</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>Onboard Reset Button</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="0" />
+ </parameters>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset">
+ <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <description>HDMI DDC</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+ <description>HDMI Out</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JXADC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="SD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="SD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="SD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="SD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="SD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="SD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="SD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="SD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="SD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="SD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="SD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="SD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="SD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="SD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="SD9"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>512MB 800Mt/s on-board DDR3 </description>
+ </component>
+ <component name="dip_switches_8bits" display_name="8 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>Switches 7 to 0</description>
+ </component>
+ <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>PHY Ethernet on the board</description>
+ <component_modes>
+ <component_mode name="rgmii" display_name="RGMII mode">
+ <interfaces>
+ <interface name="eth_rgmii" order="0"/>
+ <interface name="eth_mdio_mdc" order="1"/>
+ <interface name="phy_reset_out" order="2" optional="true"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+ <component_modes>
+ <component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+ <interfaces>
+ <interface name="oled"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="oled"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+ <description>Onboard OLED (DISP1)</description>
+ </component>
+ <component name="led_8bits" display_name="8 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 7 to 0</description>
+ </component>
+ <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+ <description>System Reset Button</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+ <description>100 MHz Single-Ended System Clock</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ </component>
+ <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI input (Requires Digilent's TMDS interface)</description>
+ <component_modes>
+ <component_mode name="HDMI_IN" display_name="HDMI In">
+ <interfaces>
+ <interface name="hdmi_in" order="0"/>
+ <interface name="hdmi_in_ddc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI in HPD (Connected to LD8)</description>
+ </component>
+ <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI Out (Requires Digilent's TMDS interface)</description>
+ </component>
+ <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI out HPD</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JXADC</description>
+ </component>
+ <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+ <component_modes>
+ <component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="sd"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+ <description>Onboard MicroSD Card Slot</description>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_dip_switches_8bits" component1="part0" component2="dip_switches_8bits">
+ <connection_map name="part0_dip_switches_8bits_1" c1_st_index="1" c1_end_index="8" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_eth_mdio_mdc" component1="part0" component2="phy_onboard">
+ <connection_map name="part0_eth_rgmii_1" c1_st_index="12" c1_end_index="23" c2_st_index="0" c2_end_index="11"/>
+ <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="9" c1_end_index="10" c2_st_index="0" c2_end_index="1"/>
+ <connection_map name="part0_eth_phy_reset_n" c1_st_index="45" c1_end_index="45" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_led_8bits" component1="part0" component2="led_8bits">
+ <connection_map name="part0_led_8bits_1" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_phy_reset_out" component1="part0" component2="phy_reset_out">
+ <connection_map name="part0_phy_reset_out_1" c1_st_index="11" c1_end_index="11" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+ <connection_map name="part0_push_buttons_5bits_1" c1_st_index="32" c1_end_index="36" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="37" c1_end_index="41" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="42" c1_end_index="42" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+ <connection_map name="part0_hdmi_in_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+ <connection_map name="part0_hdmi_in_ddc" c1_st_index="64" c1_end_index="65" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+ <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="46" c1_end_index="46" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+ <connection_map name="part0_hdmi_out_1" c1_st_index="56" c1_end_index="63" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+ <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="55" c1_end_index="55" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="66" c1_end_index="73" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="74" c1_end_index="81" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="82" c1_end_index="89" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jxadc" component1="part0" component2="jxadc">
+ <connection_map name="part0_jxadc_1" c1_st_index="90" c1_end_index="97" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_oled" component1="part0" component2="oled">
+ <connection_map name="part0_oled_1" c1_st_index="98" c1_end_index="103" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_sd" component1="part0" component2="sd">
+ <connection_map name="part0_ja_1" c1_st_index="104" c1_end_index="110" c2_st_index="0" c2_end_index="6"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/mig.prj
new file mode 100644
index 000000000..d73937fb0
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/mig.prj
@@ -0,0 +1,133 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>system_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a200t-sbg484/-1</TargetFPGA>
+ <Version>2.1</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>
+ <TimePeriod>2500</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>15</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <C0_MEM_SIZE>536870912</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L5" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N5" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N4" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P2" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P6" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M5" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M3" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P1" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N3" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N2" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M6" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R1" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L3" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K6" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L4" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K3" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="P4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="P5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J6" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G3" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F3" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D2" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A1" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E2" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B1" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H4" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H5" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J1" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K1" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H3" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H2" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J5" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E3" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B2" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="J2" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="D1" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="K2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="E1" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K4" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J4" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="G1" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L1" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>29</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>32</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/part0_pins.xml
new file mode 100644
index 000000000..f7007b9f6
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/part0_pins.xml
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7a200tsbg484-1">
+<pins>
+ <pin index="0" name ="clk" iostandard="LVCMOS33" loc="R4"/>
+ <pin index="1" name ="dip_switches_8bits_tri_i_0" iostandard="LVCMOS33" loc="E22"/>
+ <pin index="2" name ="dip_switches_8bits_tri_i_1" iostandard="LVCMOS33" loc="F21"/>
+ <pin index="3" name ="dip_switches_8bits_tri_i_2" iostandard="LVCMOS33" loc="G21"/>
+ <pin index="4" name ="dip_switches_8bits_tri_i_3" iostandard="LVCMOS33" loc="G22"/>
+ <pin index="5" name ="dip_switches_8bits_tri_i_4" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="6" name ="dip_switches_8bits_tri_i_5" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="7" name ="dip_switches_8bits_tri_i_6" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="8" name ="dip_switches_8bits_tri_i_7" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="9" name ="eth_mdc" iostandard="LVCMOS25" loc="AA16"/>
+ <pin index="10" name ="eth_mdio_i" iostandard="LVCMOS25" loc="Y16"/>
+ <pin index="11" name ="eth_rst" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="12" name ="eth_rxd_0" iostandard="LVCMOS25" loc="AB16"/>
+ <pin index="13" name ="eth_rxd_1" iostandard="LVCMOS25" loc="AA15"/>
+ <pin index="14" name ="eth_rxd_2" iostandard="LVCMOS25" loc="AB15"/>
+ <pin index="15" name ="eth_rxd_3" iostandard="LVCMOS25" loc="AB11"/>
+ <pin index="16" name ="eth_rx_clk" iostandard="LVCMOS25" loc="V13"/>
+ <pin index="17" name ="eth_rx_ctl" iostandard="LVCMOS25" loc="W10"/>
+ <pin index="18" name ="eth_txd_0" iostandard="LVCMOS25" loc="Y12"/>
+ <pin index="19" name ="eth_txd_1" iostandard="LVCMOS25" loc="W12"/>
+ <pin index="20" name ="eth_txd_2" iostandard="LVCMOS25" loc="W11"/>
+ <pin index="21" name ="eth_txd_3" iostandard="LVCMOS25" loc="Y11"/>
+ <pin index="22" name ="eth_tx_clk" iostandard="LVCMOS25" loc="AA14"/>
+ <pin index="23" name ="eth_tx_ctl" iostandard="LVCMOS25" loc="V10"/>
+ <pin index="24" name ="led_8bits_tri_o_0" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="25" name ="led_8bits_tri_o_1" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="26" name ="led_8bits_tri_o_2" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="27" name ="led_8bits_tri_o_3" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="28" name ="led_8bits_tri_o_4" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="29" name ="led_8bits_tri_o_5" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="30" name ="led_8bits_tri_o_6" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="31" name ="led_8bits_tri_o_7" iostandard="LVCMOS33" loc="Y13"/>
+ <pin index="32" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="B22"/>
+ <pin index="33" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="34" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="C22"/>
+ <pin index="35" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="D14"/>
+ <pin index="36" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="D22"/>
+ <pin index="37" name ="qspi_csn_i" iostandard="LVCMOS33" loc="T19"/>
+ <pin index="38" name ="qspi_db0_i" iostandard="LVCMOS33" loc="P22"/>
+ <pin index="39" name ="qspi_db1_i" iostandard="LVCMOS33" loc="R22"/>
+ <pin index="40" name ="qspi_db2_i" iostandard="LVCMOS33" loc="P21"/>
+ <pin index="41" name ="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
+ <pin index="42" name ="reset" iostandard="LVCMOS15" loc="G4"/>
+ <pin index="43" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V18"/>
+ <pin index="44" name ="usb_uart_txd" iostandard="LVCMOS33" loc="AA19"/>
+ <pin index="45" name ="phy_reset_n" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="46" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="AB12"/>
+ <pin index="47" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="V4"/>
+ <pin index="48" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="W4"/>
+ <pin index="49" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="Y3"/>
+ <pin index="50" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="W2"/>
+ <pin index="51" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="U2"/>
+ <pin index="52" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="AA3"/>
+ <pin index="53" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="Y2"/>
+ <pin index="54" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="V2"/>
+ <pin index="55" name ="hdmi_tx_hpd" iostandard="LVCMOS18" loc="AB13"/>
+ <pin index="56" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="T1"/>
+ <pin index="57" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="U1"/>
+ <pin index="58" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="W1"/>
+ <pin index="59" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="AA1"/>
+ <pin index="60" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="AB3"/>
+ <pin index="61" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="Y1"/>
+ <pin index="62" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="AB1"/>
+ <pin index="63" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="AB2"/>
+ <pin index="64" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="Y4"/>
+ <pin index="65" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="AB5"/>
+ <pin index="66" name ="JA1" iostandard="LVCMOS33" loc="AB22"/>
+ <pin index="67" name ="JA2" iostandard="LVCMOS33" loc="AB21"/>
+ <pin index="68" name ="JA3" iostandard="LVCMOS33" loc="AB20"/>
+ <pin index="69" name ="JA4" iostandard="LVCMOS33" loc="AB18"/>
+ <pin index="70" name ="JA7" iostandard="LVCMOS33" loc="Y21"/>
+ <pin index="71" name ="JA8" iostandard="LVCMOS33" loc="AA21"/>
+ <pin index="72" name ="JA9" iostandard="LVCMOS33" loc="AA20"/>
+ <pin index="73" name ="JA10" iostandard="LVCMOS33" loc="AA18"/>
+ <pin index="74" name ="JB1" iostandard="LVCMOS33" loc="V9"/>
+ <pin index="75" name ="JB2" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="76" name ="JB3" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="77" name ="JB4" iostandard="LVCMOS33" loc="W7"/>
+ <pin index="78" name ="JB7" iostandard="LVCMOS33" loc="W9"/>
+ <pin index="79" name ="JB8" iostandard="LVCMOS33" loc="Y9"/>
+ <pin index="80" name ="JB9" iostandard="LVCMOS33" loc="Y8"/>
+ <pin index="81" name ="JB10" iostandard="LVCMOS33" loc="Y7"/>
+ <pin index="82" name ="JC1" iostandard="LVCMOS33" loc="Y6"/>
+ <pin index="83" name ="JC2" iostandard="LVCMOS33" loc="AA6"/>
+ <pin index="84" name ="JC3" iostandard="LVCMOS33" loc="AA8"/>
+ <pin index="85" name ="JC4" iostandard="LVCMOS33" loc="AB8"/>
+ <pin index="86" name ="JC7" iostandard="LVCMOS33" loc="R6"/>
+ <pin index="87" name ="JC8" iostandard="LVCMOS33" loc="T6"/>
+ <pin index="88" name ="JC9" iostandard="LVCMOS33" loc="AB7"/>
+ <pin index="89" name ="JC10" iostandard="LVCMOS33" loc="AB6"/>
+ <pin index="90" name ="JXADC1" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="91" name ="JXADC2" iostandard="LVCMOS33" loc="H13"/>
+ <pin index="92" name ="JXADC3" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="93" name ="JXADC4" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="94" name ="JXADC7" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="95" name ="JXADC8" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="96" name ="JXADC9" iostandard="LVCMOS33" loc="G16"/>
+ <pin index="97" name ="JXADC10" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="98" name ="OLED2" iostandard="LVCMOS33" loc="Y22"/>
+ <pin index="99" name ="OLED4" iostandard="LVCMOS33" loc="W21"/>
+ <pin index="100" name ="OLED7" iostandard="LVCMOS33" loc="W22"/>
+ <pin index="101" name ="OLED8" iostandard="LVCMOS33" loc="U21"/>
+ <pin index="102" name ="OLED9" iostandard="LVCMOS33" loc="P20"/>
+ <pin index="103" name ="OLED10" iostandard="LVCMOS33" loc="V22"/>
+ <pin index="104" name ="SD1" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="105" name ="SD2" iostandard="LVCMOS33" loc="W20"/>
+ <pin index="106" name ="SD3" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="107" name ="SD4" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="108" name ="SD7" iostandard="LVCMOS33" loc="T21"/>
+ <pin index="109" name ="SD8" iostandard="LVCMOS33" loc="T20"/>
+ <pin index="110" name ="SD9" iostandard="LVCMOS33" loc="T18"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/preset.xml
new file mode 100644
index 000000000..58983c61a
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/nexys_video/A.0/preset.xml
@@ -0,0 +1,322 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="oled_preset">
+ <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+ <user_parameters>
+ <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/>
+ <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="spi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="dip_switches_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_5bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="led_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_diff_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/board.xml
new file mode 100644
index 000000000..401a2c97a
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/board.xml
@@ -0,0 +1,1057 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- confirm url -->
+<board schema_version="2.0" vendor="digilentinc.com" name="sword" display_name="Sword" url="www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">C.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Sword</description>
+<components>
+ <component name="part0" display_name="Sword" type="fpga" part_name="xc7k325tffg900-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com/sword">
+ <interfaces>
+ <!-- Clock Signal -->
+ <interface mode="slave" name="sys_diff_clock" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sys_diff_clock" preset_proc="sys_diff_clock_preset">
+ <description>Differential System Clock</description>
+ <parameters>
+ <parameter name="frequency" value="200000000"/>
+ </parameters>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="clk_n"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- User Reset Button-->
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+ <description>User Reset Button</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="reset" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="reset"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="rst_polarity" value="0" />
+ </parameters>
+ </interface>
+ <!-- Switches -->
+ <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+ <description>16 DIP Switches</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/>
+ <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/>
+ <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/>
+ <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/>
+ <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/>
+ <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/>
+ <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/>
+ <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/>
+ <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- LEDs -->
+ <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="led_16bits_preset">
+ <description>16 LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="led_16bits_tri_o" dir="in" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
+ <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
+ <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
+ <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
+ <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
+ <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
+ <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
+ <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
+ <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- RGB LEDs -->
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="rgb_led_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Twenty-Five Button Keypad -->
+ <interface mode="master" name="keypad" type="xilinx.com:interface:gpio_rtl:1.0" of_component="keypad" preset_proc="keypad_preset">
+ <description>25 Button Keypad</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="keypad_tri_o" dir="out" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="keypad_col_0"/>
+ <pin_map port_index="1" component_pin="keypad_col_1"/>
+ <pin_map port_index="2" component_pin="keypad_col_2"/>
+ <pin_map port_index="3" component_pin="keypad_col_3"/>
+ <pin_map port_index="4" component_pin="keypad_col_4"/>
+ <pin_map port_index="5" component_pin="keypad_row_0"/>
+ <pin_map port_index="6" component_pin="keypad_row_1"/>
+ <pin_map port_index="7" component_pin="keypad_row_2"/>
+ <pin_map port_index="8" component_pin="keypad_row_3"/>
+ <pin_map port_index="9" component_pin="keypad_row_4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="keypad_tri_o" dir="in" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="keypad_col_0"/>
+ <pin_map port_index="1" component_pin="keypad_col_1"/>
+ <pin_map port_index="2" component_pin="keypad_col_2"/>
+ <pin_map port_index="3" component_pin="keypad_col_3"/>
+ <pin_map port_index="4" component_pin="keypad_col_4"/>
+ <pin_map port_index="5" component_pin="keypad_row_0"/>
+ <pin_map port_index="6" component_pin="keypad_row_1"/>
+ <pin_map port_index="7" component_pin="keypad_row_2"/>
+ <pin_map port_index="8" component_pin="keypad_row_3"/>
+ <pin_map port_index="9" component_pin="keypad_row_4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="keypad_tri_o" dir="in" left="9" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="keypad_col_0"/>
+ <pin_map port_index="1" component_pin="keypad_col_1"/>
+ <pin_map port_index="2" component_pin="keypad_col_2"/>
+ <pin_map port_index="3" component_pin="keypad_col_3"/>
+ <pin_map port_index="4" component_pin="keypad_col_4"/>
+ <pin_map port_index="5" component_pin="keypad_row_0"/>
+ <pin_map port_index="6" component_pin="keypad_row_1"/>
+ <pin_map port_index="7" component_pin="keypad_row_2"/>
+ <pin_map port_index="8" component_pin="keypad_row_3"/>
+ <pin_map port_index="9" component_pin="keypad_row_4"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Seven Segment Display -->
+ <interface mode="master" name="sseg" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sseg" preset_proc="sseg_preset">
+ <description>7 Segment Display</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="sseg_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sseg_clk"/>
+ <pin_map port_index="1" component_pin="sseg_en"/>
+ <pin_map port_index="2" component_pin="sseg_sdo"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="sseg_o" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sseg_clk"/>
+ <pin_map port_index="1" component_pin="sseg_en"/>
+ <pin_map port_index="2" component_pin="sseg_sdo"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="sseg_o" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sseg_clk"/>
+ <pin_map port_index="1" component_pin="sseg_en"/>
+ <pin_map port_index="2" component_pin="sseg_sdo"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Pmod Header JA -->
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Pmod Header JB -->
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Pmod Header JC -->
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- Pmod Header JD -->
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- USB-UART Interface -->
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="usb_uart_preset">
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- QSPI Flash -->
+ <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+ <description>Quad SPI Flash</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db0_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db1_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db2_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_db3_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="qspi_csn_i"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <!-- DDR3 SDRAM -->
+ <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
+ <description>DDR3 Interface</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+ </preferred_ips>
+ </interface>
+ <!-- Ethernet PHY -->
+ <interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
+ <description>Secondary interface to communicate with ethernet phy. </description>
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdio_i"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_mdc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
+ <description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
+ <port_maps>
+ <port_map logical_port="TD" physical_port="eth_rgmii_td" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_td_0"/>
+ <pin_map port_index="1" component_pin="eth_rgmii_td_1"/>
+ <pin_map port_index="2" component_pin="eth_rgmii_td_2"/>
+ <pin_map port_index="3" component_pin="eth_rgmii_td_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RD" physical_port="eth_rgmii_rd" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_rd_0"/>
+ <pin_map port_index="1" component_pin="eth_rgmii_rd_1"/>
+ <pin_map port_index="2" component_pin="eth_rgmii_rd_2"/>
+ <pin_map port_index="3" component_pin="eth_rgmii_rd_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RX_CTL" physical_port="eth_rgmii_rx_ctl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_rx_ctl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TX_CTL" physical_port="eth_rgmii_tx_ctl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_tx_ctl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TXC" physical_port="eth_rgmii_txc" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_txc"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RXC" physical_port="eth_rgmii_rxc" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="eth_rgmii_rxc"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+
+ <component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+ <description>1 GB 1800Mt/s on-board DDR3 </description>
+ <parameters>
+ <parameter name="ddr_type" value="ddr3"/>
+ <parameter name="size" value="1GB"/>
+ </parameters>
+ </component>
+ <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 15 to 0</description>
+ </component>
+ <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 15 to 0</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB LEDs 16 and 17</description>
+ </component>
+ <component name="keypad" display_name="25 Button Keypad" type="chip" sub_type="switch" major_group="GPIO">
+ <description>25 Button Keypad</description>
+ </component>
+ <component name="sseg" display_name="7 Segment Display" type="chip" sub_type="led" major_group="GPIO">
+ <description>7 Segment Display</description>
+ </component>
+ <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+ <description>QSPI Flash</description>
+ </component>
+ <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+ <description>System Reset Button</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, allows a connection to a host computer with a USB port</description>
+ </component>
+ <component name="sys_diff_clock" display_name="System Differential Clock" type="chip" sub_type="system_clock" major_group="Clock Sources" >
+ <description>3.3V LVDS differential 200 MHz oscillator used as system differential clock source</description>
+ <parameters>
+ <parameter name="frequency" value="200000000"/>
+ </parameters>
+ </component>
+ <component name="phy_onboard" display_name="Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
+ <description>PHY Ethernet on the board</description>
+ <component_modes>
+ <component_mode name="rgmii" display_name="RGMII mode">
+ <interfaces>
+ <interface name="eth_rgmii" order="0"/>
+ <interface name="eth_mdio_mdc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_sysclk" component1="part0" component2="sys_diff_clock">
+ <connection_map name="part0_sys_clk_1" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_reset" component1="part0" component2="reset">
+ <connection_map name="part0_reset_1" c1_st_index="2" c1_end_index="2" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+ <connection_map name="part0_dip_switches_16bits_1" c1_st_index="3" c1_end_index="18" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+ <connection_map name="part0_led_16bits_1" c1_st_index="19" c1_end_index="34" c2_st_index="0" c2_end_index="15"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="35" c1_end_index="40" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_keypad" component1="part0" component2="keypad">
+ <connection_map name="part0_keypad_1" c1_st_index="41" c1_end_index="50" c2_st_index="0" c2_end_index="9"/>
+ </connection>
+ <connection name="part0_sseg" component1="part0" component2="sseg">
+ <connection_map name="part0_sseg_1" c1_st_index="51" c1_end_index="53" c2_st_index="0" c2_end_index="2"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="54" c1_end_index="61" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="62" c1_end_index="69" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="70" c1_end_index="77" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="78" c1_end_index="85" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="86" c1_end_index="87" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+ <connection_map name="part0_qspi_flash_1" c1_st_index="88" c1_end_index="92" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_phy_onboard" component1="part0" component2="phy_onboard">
+ <connection_map name="part0_eth_rgmii_1" c1_st_index="95" c1_end_index="106" c2_st_index="0" c2_end_index="11"/>
+ <connection_map name="part0_eth_mdio_mdc_1" c1_st_index="93" c1_end_index="94" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/mig.prj
new file mode 100644
index 000000000..cde7e6ff3
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/mig.prj
@@ -0,0 +1,159 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
+ <Version>4.0</Version>
+ <SystemClock>Differential</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>0</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-107</MemoryDevice>
+ <TimePeriod>1250</TimePeriod>
+ <VccAuxIO>2.0V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>800</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>32</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <BankMachineCnt>4</BankMachineCnt>
+ <CustomPart>TRUE</CustomPart>
+ <NewPartName>2Xmt41k256m16xx-107</NewPartName>
+ <RowAddress>16</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <C0_MEM_SIZE>2147483648</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG9" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG10" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF6" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH4" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AA13" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >11</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>31</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml
new file mode 100644
index 000000000..6dc2c715b
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/part0_pins.xml
@@ -0,0 +1,126 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7k325tffg900-2">
+<pins>
+ <!-- Clock Signal -->
+ <pin index="0" name="clk_n" iostandard="LVDS" loc="AD11"/>
+ <pin index="1" name="clk_p" iostandard="LVDS" loc="AD12"/>
+ <!-- User Reset Button-->
+ <pin index="2" name="reset" iostandard="LVCMOS15" loc="Y13"/>
+ <!-- Switches -->
+ <pin index="3" name="dip_switches_16bits_tri_i_0" iostandard="LVCMOS18" loc="AG19"/>
+ <pin index="4" name="dip_switches_16bits_tri_i_1" iostandard="LVCMOS18" loc="AH19"/>
+ <pin index="5" name="dip_switches_16bits_tri_i_2" iostandard="LVCMOS18" loc="AH17"/>
+ <pin index="6" name="dip_switches_16bits_tri_i_3" iostandard="LVCMOS18" loc="AF16"/>
+ <pin index="7" name="dip_switches_16bits_tri_i_4" iostandard="LVCMOS18" loc="AH16"/>
+ <pin index="8" name="dip_switches_16bits_tri_i_5" iostandard="LVCMOS18" loc="AE16"/>
+ <pin index="9" name="dip_switches_16bits_tri_i_6" iostandard="LVCMOS18" loc="AJ19"/>
+ <pin index="10" name="dip_switches_16bits_tri_i_7" iostandard="LVCMOS18" loc="AK19"/>
+ <pin index="11" name="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="AJ17"/>
+ <pin index="12" name="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="AJ16"/>
+ <pin index="13" name="dip_switches_16bits_tri_i_10" iostandard="LVCMOS18" loc="AK16"/>
+ <pin index="14" name="dip_switches_16bits_tri_i_11" iostandard="LVCMOS18" loc="AK15"/>
+ <pin index="15" name="dip_switches_16bits_tri_i_12" iostandard="LVCMOS18" loc="AG15"/>
+ <pin index="16" name="dip_switches_16bits_tri_i_13" iostandard="LVCMOS18" loc="AH15"/>
+ <pin index="17" name="dip_switches_16bits_tri_i_14" iostandard="LVCMOS18" loc="AG14"/>
+ <pin index="18" name="dip_switches_16bits_tri_i_15" iostandard="LVCMOS18" loc="AF15"/>
+ <!-- LEDs -->
+ <pin index="19" name="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="20" name="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="21" name="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="H11"/>
+ <pin index="22" name="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="H12"/>
+ <pin index="23" name="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="24" name="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="25" name="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="G13"/>
+ <pin index="26" name="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="F13"/>
+ <pin index="27" name="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="F12"/>
+ <pin index="28" name="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="E13"/>
+ <pin index="29" name="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="C12"/>
+ <pin index="30" name="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="B12"/>
+ <pin index="31" name="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="F11"/>
+ <pin index="32" name="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="AB27"/>
+ <pin index="33" name="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="AC27"/>
+ <pin index="34" name="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="G30"/>
+ <!-- RGB LEDs -->
+ <pin index="35" name="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="F15"/> <!-- LED16_B -->
+ <pin index="36" name="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="E14"/> <!-- LED16_G -->
+ <pin index="37" name="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="E16"/> <!-- LED16_R -->
+ <pin index="38" name="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/> <!-- LED16_B -->
+ <pin index="39" name="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="C14"/> <!-- LED16_G -->
+ <pin index="40" name="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="D14"/> <!-- LED16_R -->
+ <!-- Twenty-Five Button Keypad -->
+ <pin index="41" name="keypad_col_0" iostandard="LVCMOS15" loc="AE13"/>
+ <pin index="42" name="keypad_col_1" iostandard="LVCMOS15" loc="AJ14"/>
+ <pin index="43" name="keypad_col_2" iostandard="LVCMOS15" loc="AJ13"/>
+ <pin index="44" name="keypad_col_3" iostandard="LVCMOS15" loc="AH14"/>
+ <pin index="45" name="keypad_col_4" iostandard="LVCMOS15" loc="AG12"/>
+ <pin index="46" name="keypad_row_0" iostandard="LVCMOS15" loc="AK14"/>
+ <pin index="47" name="keypad_row_1" iostandard="LVCMOS15" loc="AK13"/>
+ <pin index="48" name="keypad_row_2" iostandard="LVCMOS15" loc="AJ12"/>
+ <pin index="49" name="keypad_row_3" iostandard="LVCMOS15" loc="AF12"/>
+ <pin index="50" name="keypad_row_4" iostandard="LVCMOS15" loc="AH10"/>
+ <!-- Seven Segment Display -->
+ <pin index="51" name="sseg_clk" iostandard="LVCMOS33" loc="A11"/>
+ <pin index="52" name="sseg_en" iostandard="LVCMOS33" loc="A12"/>
+ <pin index="53" name="sseg_sdo" iostandard="LVCMOS33" loc="E11"/>
+ <!-- Pmod Header JA -->
+ <pin index="54" name="JA1" iostandard="LVCMOS33" loc="D24"/>
+ <pin index="55" name="JA2" iostandard="LVCMOS33" loc="E24"/>
+ <pin index="56" name="JA3" iostandard="LVCMOS33" loc="G24"/>
+ <pin index="57" name="JA4" iostandard="LVCMOS33" loc="G23"/>
+ <pin index="58" name="JA7" iostandard="LVCMOS33" loc="E26"/>
+ <pin index="59" name="JA8" iostandard="LVCMOS33" loc="F26"/>
+ <pin index="60" name="JA9" iostandard="LVCMOS33" loc="A27"/>
+ <pin index="61" name="JA10" iostandard="LVCMOS33" loc="B27"/>
+ <!-- Pmod Header JB -->
+ <pin index="62" name="JB1" iostandard="LVCMOS33" loc="A28"/>
+ <pin index="63" name="JB2" iostandard="LVCMOS33" loc="B28"/>
+ <pin index="64" name="JB3" iostandard="LVCMOS33" loc="A26"/>
+ <pin index="65" name="JB4" iostandard="LVCMOS33" loc="A25"/>
+ <pin index="66" name="JB7" iostandard="LVCMOS33" loc="C26"/>
+ <pin index="67" name="JB8" iostandard="LVCMOS33" loc="D26"/>
+ <pin index="68" name="JB9" iostandard="LVCMOS33" loc="B25"/>
+ <pin index="69" name="JB10" iostandard="LVCMOS33" loc="C25"/>
+ <!-- Pmod Header JC -->
+ <pin index="70" name="JC1" iostandard="LVCMOS33" loc="E28"/>
+ <pin index="71" name="JC2" iostandard="LVCMOS33" loc="D28"/>
+ <pin index="72" name="JC3" iostandard="LVCMOS33" loc="C29"/>
+ <pin index="73" name="JC4" iostandard="LVCMOS33" loc="B29"/>
+ <pin index="74" name="JC7" iostandard="LVCMOS33" loc="D29"/>
+ <pin index="75" name="JC8" iostandard="LVCMOS33" loc="C30"/>
+ <pin index="76" name="JC9" iostandard="LVCMOS33" loc="B30"/>
+ <pin index="77" name="JC10" iostandard="LVCMOS33" loc="A30"/>
+ <!-- Pmod Header JD -->
+ <pin index="78" name="JD1" iostandard="LVCMOS33" loc="E29"/>
+ <pin index="79" name="JD2" iostandard="LVCMOS33" loc="E30"/>
+ <pin index="80" name="JD3" iostandard="LVCMOS33" loc="H24"/>
+ <pin index="81" name="JD4" iostandard="LVCMOS33" loc="H25"/>
+ <pin index="82" name="JD7" iostandard="LVCMOS33" loc="G28"/>
+ <pin index="83" name="JD8" iostandard="LVCMOS33" loc="F28"/>
+ <pin index="84" name="JD9" iostandard="LVCMOS33" loc="G27"/>
+ <pin index="85" name="JD10" iostandard="LVCMOS33" loc="F27"/>
+ <!-- USB-UART Interface -->
+ <pin index="86" name="usb_uart_rxd" iostandard="LVCMOS33" loc="G29"/>
+ <pin index="87" name="usb_uart_txd" iostandard="LVCMOS33" loc="F30"/>
+ <!-- QSPI Flash -->
+ <pin index="88" name="qspi_csn_i" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="89" name="qspi_db0_i" iostandard="LVCMOS33" loc="P24"/>
+ <pin index="90" name="qspi_db1_i" iostandard="LVCMOS33" loc="R25"/>
+ <pin index="91" name="qspi_db2_i" iostandard="LVCMOS33" loc="R20"/>
+ <pin index="92" name="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
+ <!-- Ethernet PHY -->
+ <pin index="93" name="eth_mdc" iostandard="LVCMOS18" loc="AA18"/>
+ <pin index="94" name="eth_mdio_i" iostandard="LVCMOS18" loc="Y18"/>
+ <pin index="95" name="eth_rgmii_rd_0" iostandard="LVCMOS18" loc="AE15"/>
+ <pin index="96" name="eth_rgmii_rd_1" iostandard="LVCMOS18" loc="AE18"/>
+ <pin index="97" name="eth_rgmii_rd_2" iostandard="LVCMOS18" loc="AD16"/>
+ <pin index="98" name="eth_rgmii_rd_3" iostandard="LVCMOS18" loc="AC19"/>
+ <pin index="99" name="eth_rgmii_rxc" iostandard="LVCMOS18" loc="AD18"/>
+ <pin index="100" name="eth_rgmii_rx_ctl" iostandard="LVCMOS18" loc="AE14"/>
+ <pin index="101" name="eth_rgmii_td_0" iostandard="LVCMOS18" loc="AA15"/>
+ <pin index="102" name="eth_rgmii_td_1" iostandard="LVCMOS18" loc="AD17"/>
+ <pin index="103" name="eth_rgmii_td_2" iostandard="LVCMOS18" loc="AG17"/>
+ <pin index="104" name="eth_rgmii_td_3" iostandard="LVCMOS18" loc="AC17"/>
+ <pin index="105" name="eth_rgmii_txc" iostandard="LVCMOS18" loc="AB15"/>
+ <pin index="106" name="eth_rgmii_tx_ctl" iostandard="LVCMOS18" loc="AB17"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/preset.xml
new file mode 100644
index 000000000..b45e11aaf
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/sword/C.0/preset.xml
@@ -0,0 +1,408 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ddr3_sdram_preset">
+ <ip vendor="xilinx.com" library="ip" name="mig_7series">
+ <user_parameters>
+ <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="qspi_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+ <user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+ <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_16bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="rgb_led_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sseg_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="keypad_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="10"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="usb_uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_diff_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="hdmi_in_preset">
+ <ip vendor="digilentinc.com" library="ip" name="dvi2rgb">
+ <user_parameters>
+ <user_parameter name="CONFIG.kRstActiveHigh" value="false"/>
+ <user_parameter name="CONFIG.kClkRange" value="2"/>
+ <user_parameter name="CONFIG.kAddBUFG" value="false"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="mii_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernetlite" ip_interface="mii">
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
+ <user_parameters>
+ <user_parameter name="CONFIG.Physical_Interface" value="MII"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/board.xml
new file mode 100644
index 000000000..9341cc79d
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/board.xml
@@ -0,0 +1,812 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="zedboard" display_name="Zedboard" url="http://www.digilentinc.com" preset_file="preset.xml">
+ <images>
+ <image name="zed_board.jpg" display_name="ZED BOARD" sub_type="board">
+ <description>ZED Board File Image</description>
+ </image>
+ </images>
+ <compatible_board_revisions>
+ <revision id="0">D.3</revision>
+ </compatible_board_revisions>
+ <file_version>1.0</file_version>
+ <description>ZedBoard Zynq Evaluation and Development Kit</description>
+ <components>
+ <component name="part0" display_name="ZedBoard" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/zedboard/start?redirect=1id=zedboard/zedboard">
+ <description>FPGA part on the board</description>
+ <interfaces>
+ <interface mode="master" name="btns_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_5bits" preset_proc="btns_5bits_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_5bits_tri_i" dir="in" left="4" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_5bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_5bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_5bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_5bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="btns_5bits_tri_i_4"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_8bits" preset_proc="leds_8bits_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_8bits_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="leds_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="leds_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="leds_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="leds_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_8bits_tri_o" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="leds_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="leds_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="leds_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="leds_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_8bits_tri_o" dir="out" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_8bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_8bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_8bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_8bits_tri_o_3"/>
+ <pin_map port_index="4" component_pin="leds_8bits_tri_o_4"/>
+ <pin_map port_index="5" component_pin="leds_8bits_tri_o_5"/>
+ <pin_map port_index="6" component_pin="leds_8bits_tri_o_6"/>
+ <pin_map port_index="7" component_pin="leds_8bits_tri_o_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_8bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_8bits" preset_proc="sws_8bits_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_8bits_tri_i" dir="in" left="7" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_8bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_8bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="sws_8bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="sws_8bits_tri_i_3"/>
+ <pin_map port_index="4" component_pin="sws_8bits_tri_i_4"/>
+ <pin_map port_index="5" component_pin="sws_8bits_tri_i_5"/>
+ <pin_map port_index="6" component_pin="sws_8bits_tri_i_6"/>
+ <pin_map port_index="7" component_pin="sws_8bits_tri_i_7"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000" />
+ </parameters>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="oled" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="oled" preset_proc="oled_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="PIN2_I" physical_port="OLED2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="OLED2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="OLED2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="OLED4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="OLED4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="OLED4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="OLED7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="OLED7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="OLED7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="OLED8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="OLED8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="OLED8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="OLED9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="OLED9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="OLED9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="OLED10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="OLED10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="OLED10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="OLED10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_txd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="usb_uart_rxd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+ <component name="btns_5bits" display_name="Push buttons" type="chip" sub_type="push_button" major_group="General Purpose Input or Output">
+ <description>Push Buttons, U R L D C, Active High</description>
+ </component>
+ <component name="leds_8bits" display_name="LED" type="chip" sub_type="led" major_group="General Purpose Input or Output">
+ <description>LEDs, 7 to 0, Active High</description>
+ </component>
+ <component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_8bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output">
+ <description>DIP Switches, 7 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System clock" type="chip" sub_type="system_clock" major_group="Clock Sources">
+ <description>System Clock, 100 MHz</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JE</description>
+ </component>
+ <component name="oled" display_name="Onboard OLED" type="chip" sub_type="chip" major_group="GPIO">
+ <component_modes>
+ <component_mode name="apmodoled" display_name="Digilent PmodOLED IP">
+ <interfaces>
+ <interface name="oled"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="PmodOLED" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ <component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+ <interfaces>
+ <interface name="oled"/>
+ </interfaces>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+ </preferred_ips>
+ </component_mode>
+ </component_modes>
+ <description>Onboard OLED (DISP1)</description>
+ </component>
+ <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+ <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+ </component>
+ </components>
+ <jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+ </jtag_chains>
+ <connections>
+ <connection name="part0_btns_5bits" component1="part0" component2="btns_5bits">
+ <connection_map name="part0_btns_5bits_1" c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
+ </connection>
+ <connection name="part0_leds_8bits" component1="part0" component2="leds_8bits">
+ <connection_map name="part0_leds_8bits_1" c1_st_index="5" c1_end_index="12" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sws_8bits" component1="part0" component2="sws_8bits">
+ <connection_map name="part0_sws_8bits_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="21" c1_end_index="21" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="38" c1_end_index="45" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="22" c1_end_index="29" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="30" c1_end_index="37" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="46" c1_end_index="53" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_oled" component1="part0" component2="oled">
+ <connection_map name="part0_oled_1" c1_st_index="54" c1_end_index="59" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+ <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+ <connection_map name="part0_usb_uart_1" c1_st_index="60" c1_end_index="61" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ </connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml
new file mode 100644
index 000000000..eddc454ab
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/part0_pins.xml
@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z020clg484-1">
+<pins>
+ <pin index="0" name ="btns_5bits_tri_i_0" iostandard="LVCMOS25" loc="P16"/>
+ <pin index="1" name ="btns_5bits_tri_i_1" iostandard="LVCMOS25" loc="R16"/>
+ <pin index="2" name ="btns_5bits_tri_i_2" iostandard="LVCMOS25" loc="N15"/>
+ <pin index="3" name ="btns_5bits_tri_i_3" iostandard="LVCMOS25" loc="R18"/>
+ <pin index="4" name ="btns_5bits_tri_i_4" iostandard="LVCMOS25" loc="T18"/>
+ <pin index="5" name ="leds_8bits_tri_o_0" iostandard="LVCMOS33" loc="T22"/>
+ <pin index="6" name ="leds_8bits_tri_o_1" iostandard="LVCMOS33" loc="T21"/>
+ <pin index="7" name ="leds_8bits_tri_o_2" iostandard="LVCMOS33" loc="U22"/>
+ <pin index="8" name ="leds_8bits_tri_o_3" iostandard="LVCMOS33" loc="U21"/>
+ <pin index="9" name ="leds_8bits_tri_o_4" iostandard="LVCMOS33" loc="V22"/>
+ <pin index="10" name ="leds_8bits_tri_o_5" iostandard="LVCMOS33" loc="W22"/>
+ <pin index="11" name ="leds_8bits_tri_o_6" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="12" name ="leds_8bits_tri_o_7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="13" name ="sws_8bits_tri_i_0" iostandard="LVCMOS25" loc="F22"/>
+ <pin index="14" name ="sws_8bits_tri_i_1" iostandard="LVCMOS25" loc="G22"/>
+ <pin index="15" name ="sws_8bits_tri_i_2" iostandard="LVCMOS25" loc="H22"/>
+ <pin index="16" name ="sws_8bits_tri_i_3" iostandard="LVCMOS25" loc="F21"/>
+ <pin index="17" name ="sws_8bits_tri_i_4" iostandard="LVCMOS25" loc="H19"/>
+ <pin index="18" name ="sws_8bits_tri_i_5" iostandard="LVCMOS25" loc="H18"/>
+ <pin index="19" name ="sws_8bits_tri_i_6" iostandard="LVCMOS25" loc="H17"/>
+ <pin index="20" name ="sws_8bits_tri_i_7" iostandard="LVCMOS25" loc="M15"/>
+ <pin index="21" name ="sys_clk" iostandard="LVCMOS33" loc="Y9"/>
+ <pin index="22" name ="JB1" iostandard="LVCMOS33" loc="W12"/>
+ <pin index="23" name ="JB2" iostandard="LVCMOS33" loc="W11"/>
+ <pin index="24" name ="JB3" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="25" name ="JB4" iostandard="LVCMOS33" loc="W8"/>
+ <pin index="26" name ="JB7" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="27" name ="JB8" iostandard="LVCMOS33" loc="W10"/>
+ <pin index="28" name ="JB9" iostandard="LVCMOS33" loc="V9"/>
+ <pin index="29" name ="JB10" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="30" name ="JC1" iostandard="LVCMOS33" loc="AB7"/>
+ <pin index="31" name ="JC2" iostandard="LVCMOS33" loc="AB6"/>
+ <pin index="32" name ="JC3" iostandard="LVCMOS33" loc="Y4"/>
+ <pin index="33" name ="JC4" iostandard="LVCMOS33" loc="AA4"/>
+ <pin index="34" name ="JC7" iostandard="LVCMOS33" loc="R6"/>
+ <pin index="35" name ="JC8" iostandard="LVCMOS33" loc="T6"/>
+ <pin index="36" name ="JC9" iostandard="LVCMOS33" loc="T4"/>
+ <pin index="37" name ="JC10" iostandard="LVCMOS33" loc="U4"/>
+ <pin index="38" name ="JA1" iostandard="LVCMOS33" loc="Y11"/>
+ <pin index="39" name ="JA2" iostandard="LVCMOS33" loc="AA11"/>
+ <pin index="40" name ="JA3" iostandard="LVCMOS33" loc="Y10"/>
+ <pin index="41" name ="JA4" iostandard="LVCMOS33" loc="AA9"/>
+ <pin index="42" name ="JA7" iostandard="LVCMOS33" loc="AB11"/>
+ <pin index="43" name ="JA8" iostandard="LVCMOS33" loc="AB10"/>
+ <pin index="44" name ="JA9" iostandard="LVCMOS33" loc="AB9"/>
+ <pin index="45" name ="JA10" iostandard="LVCMOS33" loc="AA8"/>
+ <pin index="46" name ="JD1" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="47" name ="JD2" iostandard="LVCMOS33" loc="W7"/>
+ <pin index="48" name ="JD3" iostandard="LVCMOS33" loc="V5"/>
+ <pin index="49" name ="JD4" iostandard="LVCMOS33" loc="V4"/>
+ <pin index="50" name ="JD7" iostandard="LVCMOS33" loc="W6"/>
+ <pin index="51" name ="JD8" iostandard="LVCMOS33" loc="W5"/>
+ <pin index="52" name ="JD9" iostandard="LVCMOS33" loc="U6"/>
+ <pin index="53" name ="JD10" iostandard="LVCMOS33" loc="U5"/>
+ <pin index="54" name ="OLED2" iostandard="LVCMOS33" loc="AA12"/>
+ <pin index="55" name ="OLED4" iostandard="LVCMOS33" loc="AB12"/>
+ <pin index="56" name ="OLED7" iostandard="LVCMOS33" loc="U10"/>
+ <pin index="57" name ="OLED8" iostandard="LVCMOS33" loc="U9"/>
+ <pin index="58" name ="OLED9" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="59" name ="OLED10" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="60" name ="usb_uart_rxd" iostandard="LVCMOS18" loc="D11"/>
+ <pin index="61" name ="usb_uart_txd" iostandard="LVCMOS18" loc="C14"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml
new file mode 100644
index 000000000..b835318b4
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/preset.xml
@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+<ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.preset" value="ZedBoard" />
+ </user_parameters>
+ </ip>
+</ip_preset>
+ <ip_preset preset_proc_name="oled_preset">
+ <ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
+ <user_parameters>
+ <user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/>
+ <user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="leds_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
+ <user_parameter name="CONFIG.C_GPO1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
+ <user_parameter name="CONFIG.C_GPO2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
+ <user_parameter name="CONFIG.C_GPO3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
+ <user_parameter name="CONFIG.C_GPO4_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="sws_8bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
+ </ip_preset>
+ <ip_preset preset_proc_name="btns_5bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+<ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="uart_preset">
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
+ <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.176"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.159"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.162"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.187"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.073"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.034"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.03"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.082"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K128M16 JT-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/zed_board.jpg b/quad/vivado_workspace/vivado-boards-master/new/board_files/zedboard/1.3/zed_board.jpg
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diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml
new file mode 100644
index 000000000..f7dd8ff0d
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/board.xml
@@ -0,0 +1,861 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo-z7-10" display_name="Zybo Z7-10" url="http://www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Zybo Z7-10</description>
+<components>
+ <component name="part0" display_name="Zybo Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+
+ <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <description>HDMI DDC</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+ <description>HDMI Out</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JE1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JE2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JE3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JE4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JE7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JE8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JE9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JE10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 3 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JE</description>
+ </component>
+ <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+ </component>
+
+ <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI input (Requires Digilent's TMDS interface)</description>
+ <component_modes>
+ <component_mode name="HDMI_IN" display_name="HDMI In">
+ <interfaces>
+ <interface name="hdmi_in" order="0"/>
+ <interface name="hdmi_in_ddc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI in HPD (Connected to LD8)</description>
+ </component>
+ <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI Out (Requires Digilent's TMDS interface)</description>
+ </component>
+ <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI out HPD</description>
+ </component>
+
+
+
+
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+ <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+ <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+ <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+
+ <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+ <connection_map name="part0_hdmi_in_1" c1_st_index="14" c1_end_index="21" c2_st_index="0" c2_end_index="7"/>
+
+ <connection_map name="part0_hdmi_in_ddc" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+
+ <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+ <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="13" c1_end_index="13" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+ <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+ <connection_map name="part0_hdmi_out_1" c1_st_index="23" c1_end_index="30" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+
+ <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+ <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="39" c1_end_index="46" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="55" c1_end_index="62" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="63" c1_end_index="70" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_je" component1="part0" component2="je">
+ <connection_map name="part0_je_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml
new file mode 100644
index 000000000..6cf9fd004
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/part0_pins.xml
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z010clg400-1">
+<pins>
+ <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="K19"/>
+ <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+ <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="K17"/>
+
+ <pin index="13" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="W19"/>
+
+ <pin index="14" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="U18"/>
+ <pin index="15" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="U19"/>
+ <pin index="16" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="V20"/>
+ <pin index="17" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="T20"/>
+ <pin index="18" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="N20"/>
+ <pin index="19" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="W20"/>
+ <pin index="20" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="U20"/>
+ <pin index="21" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="P20"/>
+
+ <pin index="22" name ="hdmi_tx_hpd" iostandard="LVCMOS33" loc="E18"/>
+
+ <pin index="23" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="24" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="25" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="26" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="C20"/>
+ <pin index="27" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="B19"/>
+ <pin index="28" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="D20"/>
+ <pin index="29" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="B20"/>
+ <pin index="30" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="A20"/>
+
+ <pin index="31" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="32" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="Y19"/>
+
+ <pin index="36" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="37" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F17"/>
+ <pin index="38" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="V16"/>
+
+ <pin index="39" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="40" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="41" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="42" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+ <pin index="43" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="44" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+ <pin index="45" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="46" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+
+ <pin index="55" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="56" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="57" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="58" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="59" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="60" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+ <pin index="61" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="62" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+
+ <pin index="63" name ="JD1" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="64" name ="JD2" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="65" name ="JD3" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="66" name ="JD4" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="67" name ="JD7" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="68" name ="JD8" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="69" name ="JD9" iostandard="LVCMOS33" loc="V18"/>
+ <pin index="70" name ="JD10" iostandard="LVCMOS33" loc="V17"/>
+
+ <pin index="71" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="72" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="73" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="74" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="75" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="76" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="77" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="78" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml
new file mode 100644
index 000000000..cb0ef2e7d
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-10/A.0/preset.xml
@@ -0,0 +1,667 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="667"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="39"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="33.333333"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.221"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.222"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.217"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.244"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="32 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="22.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="27.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="22.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="29.4"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.050"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.044"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.035"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="22.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="27.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="22.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="29.4"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="533.333333"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml
new file mode 100644
index 000000000..7e7e438e2
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/board.xml
@@ -0,0 +1,994 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo-z7-20" display_name="Zybo Z7-20" url="http://www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">B.2</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Zybo Z7-20</description>
+<components>
+ <component name="part0" display_name="Zybo Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+
+ <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_IN_clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_IN_clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_IN_D_P" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_IN_D_N" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_IN_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_IN_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_IN_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <description>HDMI DDC</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="hdmi_in_ddc_sda" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="hdmi_in_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="hdmi_in_ddc_scl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="hdmi_in_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_in_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_in_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_rx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_rx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_rx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+ <description>HDMI Out</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_OUT_clk_p" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_OUT_clk_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_OUT_D_P" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_OUT_D_N" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_OUT_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_OUT_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_OUT_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out_hpd_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_hpd_led" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_tx_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_tx_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_tx_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JE1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JE2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JE3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JE4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JE7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JE8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JE9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JE10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+ <description>2 RGB LEDs</description>
+ <preferred_ips>
+ <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="rgb_led_tri_o" dir="in" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
+ <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
+ <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
+ <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
+ <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
+ <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 3 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JE</description>
+ </component>
+ <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+ <description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+ </component>
+
+ <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI input (Requires Digilent's TMDS interface)</description>
+ <component_modes>
+ <component_mode name="HDMI_IN" display_name="HDMI In">
+ <interfaces>
+ <interface name="hdmi_in" order="0"/>
+ <interface name="hdmi_in_ddc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="hdmi_in_hpd_led" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI in HPD (Connected to LD8)</description>
+ </component>
+ <component name="hdmi_out" display_name="HDMI out" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI Out (Requires Digilent's TMDS interface)</description>
+ </component>
+ <component name="hdmi_out_hpd_led" display_name="HDMI out HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI out HPD</description>
+ </component>
+
+
+
+
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+ <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+ <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+ <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+
+ <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+ <connection_map name="part0_hdmi_in_1" c1_st_index="14" c1_end_index="21" c2_st_index="0" c2_end_index="7"/>
+
+ <connection_map name="part0_hdmi_in_ddc" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+
+ <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+ <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="13" c1_end_index="13" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+ <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+ <connection_map name="part0_hdmi_out_1" c1_st_index="23" c1_end_index="30" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+
+ <connection name="part0_hdmi_out_hpd_led" component1="part0" component2="hdmi_out_hpd_led">
+ <connection_map name="part0_hdmi_out_hpd_led_1" c1_st_index="22" c1_end_index="22" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+
+
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="39" c1_end_index="46" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="55" c1_end_index="62" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="63" c1_end_index="70" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_je" component1="part0" component2="je">
+ <connection_map name="part0_je_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+ <connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="38" c2_st_index="0" c2_end_index="5"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml
new file mode 100644
index 000000000..e166d82ba
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/part0_pins.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z020clg400-1">
+<pins>
+ <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="K18"/>
+ <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="K19"/>
+ <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+ <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="K17"/>
+
+ <pin index="13" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="W19"/>
+
+ <pin index="14" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="U18"/>
+ <pin index="15" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="U19"/>
+ <pin index="16" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="V20"/>
+ <pin index="17" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="T20"/>
+ <pin index="18" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="N20"/>
+ <pin index="19" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="W20"/>
+ <pin index="20" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="U20"/>
+ <pin index="21" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="P20"/>
+
+
+ <pin index="22" name ="hdmi_tx_hpd" iostandard="LVCMOS33" loc="E18"/>
+
+ <pin index="23" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="H16"/>
+ <pin index="24" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="25" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="D19"/>
+ <pin index="26" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="C20"/>
+ <pin index="27" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="B19"/>
+ <pin index="28" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="D20"/>
+ <pin index="29" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="B20"/>
+ <pin index="30" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="A20"/>
+
+ <pin index="31" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="32" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="Y19"/>
+
+
+
+ <pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="Y12"/>
+ <pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="T5"/>
+ <pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="Y11"/>
+ <pin index="36" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="37" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F17"/>
+ <pin index="38" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="V16"/>
+
+
+ <pin index="39" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="40" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="41" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="42" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+ <pin index="43" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="44" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+ <pin index="45" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="46" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+
+ <pin index="47" name ="JB1" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="48" name ="JB2" iostandard="LVCMOS33" loc="W8"/>
+ <pin index="49" name ="JB3" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="50" name ="JB4" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="51" name ="JB7" iostandard="LVCMOS33" loc="Y7"/>
+ <pin index="52" name ="JB8" iostandard="LVCMOS33" loc="Y6"/>
+ <pin index="53" name ="JB9" iostandard="LVCMOS33" loc="V6"/>
+ <pin index="54" name ="JB10" iostandard="LVCMOS33" loc="W6"/>
+
+ <pin index="55" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="56" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="57" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="58" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="59" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="60" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+ <pin index="61" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="62" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+
+ <pin index="63" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="64" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="65" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="66" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="67" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="68" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="69" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="70" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+
+ <pin index="71" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="72" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="73" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="74" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="75" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="76" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="77" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="78" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml
new file mode 100644
index 000000000..3175792ea
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo-z7-20/A.0/preset.xml
@@ -0,0 +1,667 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="667"/>
+ <user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="39"/>
+ <user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
+ <user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="33.333333"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7"/>
+ <user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
+ <user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32"/>
+ <user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
+ <user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
+ <user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
+ <user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
+ <user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
+ <user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30"/>
+ <user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
+ <user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="in"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS" value="0xFCFFFFFF"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
+ <user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
+ <user_parameter name="CONFIG.PCW_UART1_BAUD_RATE" value="115200"/>
+ <user_parameter name="CONFIG.PCW_UART1_GRP_FULL_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 48 .. 49"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
+ <user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.221"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.222"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.217"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.244"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="32 Bit"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="18.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="22.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="27.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="22.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="29.4"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.050"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.044"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.035"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.100"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="22.8"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="27.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="22.9"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="29.4"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="533.333333"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ <user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
+ <user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
+ <user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
+ <user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/board.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/board.xml
new file mode 100644
index 000000000..61f28def1
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/board.xml
@@ -0,0 +1,937 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="digilentinc.com" name="zybo" display_name="Zybo" url="http://www.digilentinc.com" preset_file="preset.xml" >
+<compatible_board_revisions>
+ <revision id="0">B.3</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Zybo</description>
+<components>
+ <component name="part0" display_name="Zybo" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.digilentinc.com">
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="leds_4bits_tri_o" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
+ <pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
+ <pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
+ <pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+ </interface>
+ <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_4bits" preset_proc="dip_switches_4bits_preset">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i" dir="in" left="3" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sws_4bits_tri_i_0"/>
+ <pin_map port_index="1" component_pin="sws_4bits_tri_i_1"/>
+ <pin_map port_index="2" component_pin="sws_4bits_tri_i_2"/>
+ <pin_map port_index="3" component_pin="sws_4bits_tri_i_3"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="sys_clk"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000" />
+ </parameters>
+ </interface>
+ <interface mode="slave" name="hdmi_in" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_clk_p" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_clk_n" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_D_P" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_D_N" dir="in" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_in_ddc" type="xilinx.com:interface:iic_rtl:1.0" of_component="hdmi_in" preset_proc="hdmi_in_preset">
+ <description>HDMI DDC</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="dvi2rgb" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="hdmi_ddc_sda" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_O" physical_port="hdmi_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SDA_T" physical_port="hdmi_ddc_sda" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_ddc_sda"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_I" physical_port="hdmi_ddc_scl" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_O" physical_port="hdmi_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="SCL_T" physical_port="hdmi_ddc_scl" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_ddc_scl"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_hpd" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_hpd" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_hpd" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_hpd"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_hpd" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_hpd"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out_en" type="xilinx.com:interface:gpio_rtl:1.0" of_component="hdmi_out_en" preset_proc="output_1bit_preset">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="hdmi_out_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_out_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_I" physical_port="hdmi_out_en" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_out_en"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="TRI_T" physical_port="hdmi_out_en" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="hdmi_out_en"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="hdmi_out" type="digilentinc.com:interface:tmds_rtl:1.0" of_component="hdmi_out">
+ <description>HDMI Out</description>
+ <preferred_ips>
+ <preferred_ip vendor="digilentinc.com" library="ip" name="rgb2dvi" order="0"/>
+ </preferred_ips>
+ <port_maps>
+ <port_map logical_port="CLK_P" physical_port="TMDS_clk_p" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_clk_p"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="CLK_N" physical_port="TMDS_clk_n" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_clk_n"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_P" physical_port="TMDS_D_P" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_data_p_0"/>
+ <pin_map port_index="1" component_pin="TMDS_data_p_1"/>
+ <pin_map port_index="2" component_pin="TMDS_data_p_2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="DATA_N" physical_port="TMDS_D_N" dir="out" left="2" right="0">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="TMDS_data_n_0"/>
+ <pin_map port_index="1" component_pin="TMDS_data_n_1"/>
+ <pin_map port_index="2" component_pin="TMDS_data_n_2"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JA10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JB10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JC10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JD10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="je" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="je">
+ <port_maps>
+ <port_map logical_port="PIN1_I" physical_port="JE1" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_O" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN1_T" physical_port="JE1" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE1"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_I" physical_port="JE2" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_O" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN2_T" physical_port="JE2" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE2"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_I" physical_port="JE3" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_O" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN3_T" physical_port="JE3" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE3"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_I" physical_port="JE4" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_O" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN4_T" physical_port="JE4" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE4"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_I" physical_port="JE7" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_O" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN7_T" physical_port="JE7" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE7"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_I" physical_port="JE8" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_O" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN8_T" physical_port="JE8" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE8"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_I" physical_port="JE9" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_O" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN9_T" physical_port="JE9" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE9"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_I" physical_port="JE10" dir="in">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_O" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ <port_map logical_port="PIN10_T" physical_port="JE10" dir="out">
+ <pin_maps>
+ <pin_map port_index="0" component_pin="JE10"/>
+ </pin_maps>
+ </port_map>
+ </port_maps>
+ </interface>
+ </interfaces>
+ </component>
+
+ <component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+ <description>Buttons 3 to 0</description>
+ </component>
+ <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JA</description>
+ </component>
+ <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JB</description>
+ </component>
+ <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JC</description>
+ </component>
+ <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JD</description>
+ </component>
+ <component name="je" display_name="Connector JE" type="chip" sub_type="chip" major_group="Pmod">
+ <description>Pmod Connector JE</description>
+ </component>
+ <component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
+ <description>LEDs 3 to 0</description>
+ </component>
+ <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+ <component name="sws_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
+ <description>DIP Switches 3 to 0</description>
+ </component>
+ <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+ <description>3.3V Single-Ended 50 MHz oscillator used as system clock on the board</description>
+ </component>
+ <component name="hdmi_in" display_name="HDMI In" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI input (Requires Digilent's TMDS interface)</description>
+ <component_modes>
+ <component_mode name="HDMI_IN" display_name="HDMI In">
+ <interfaces>
+ <interface name="hdmi_in" order="0"/>
+ <interface name="hdmi_in_ddc" order="1"/>
+ </interfaces>
+ </component_mode>
+ </component_modes>
+ </component>
+ <component name="hdmi_hpd" display_name="HDMI In HPD" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI in HPD</description>
+ </component>
+ <component name="hdmi_out_en" display_name="HDMI Out Enable" type="chip" sub_type="led" major_group="HDMI">
+ <description>HDMI out enable, 1 for HDMI out, 0 for HDMI in</description>
+ </component>
+ <component name="hdmi_out" display_name="HDMI Out" type="chip" sub_type="fixed_io" major_group="HDMI">
+ <description>HDMI Out (Requires Digilent's TMDS interface)</description>
+ </component>
+
+</components>
+<jtag_chains>
+ <jtag_chain name="chain1">
+ <position name="0" component="part0"/>
+ </jtag_chain>
+</jtag_chains>
+<connections>
+ <connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
+ <connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
+ <connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sws_4bits" component1="part0" component2="sws_4bits">
+ <connection_map name="part0_sws_4bits_1" c1_st_index="8" c1_end_index="11" c2_st_index="0" c2_end_index="3"/>
+ </connection>
+ <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+ <connection_map name="part0_sys_clock_1" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_hdmi_in" component1="part0" component2="hdmi_in">
+ <connection_map name="part0_hdmi_in_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+ <connection_map name="part0_hdmi_in_ddc" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_hdmi_out" component1="part0" component2="hdmi_out">
+ <connection_map name="part0_hdmi_out_1" c1_st_index="13" c1_end_index="20" c2_st_index="0" c2_end_index="7"/>
+ <connection_map name="part0_hdmi_out_ddc" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+ </connection>
+ <connection name="part0_hdmi_in_hpd_led" component1="part0" component2="hdmi_in_hpd_led">
+ <connection_map name="part0_hdmi_in_hpd_led_1" c1_st_index="23" c1_end_index="23" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_hdmi_out_en" component1="part0" component2="hdmi_out_en">
+ <connection_map name="part0_hdmi_out_en_1" c1_st_index="24" c1_end_index="24" c2_st_index="0" c2_end_index="0"/>
+ </connection>
+ <connection name="part0_ja" component1="part0" component2="ja">
+ <connection_map name="part0_ja_1" c1_st_index="41" c1_end_index="48" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jb" component1="part0" component2="jb">
+ <connection_map name="part0_jb_1" c1_st_index="25" c1_end_index="32" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jc" component1="part0" component2="jc">
+ <connection_map name="part0_jc_1" c1_st_index="33" c1_end_index="40" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_jd" component1="part0" component2="jd">
+ <connection_map name="part0_jd_1" c1_st_index="49" c1_end_index="56" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+ <connection name="part0_je" component1="part0" component2="je">
+ <connection_map name="part0_je_1" c1_st_index="57" c1_end_index="64" c2_st_index="0" c2_end_index="7"/>
+ </connection>
+</connections>
+</board>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml
new file mode 100644
index 000000000..0fed0a447
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/part0_pins.xml
@@ -0,0 +1,70 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z010clg400-1">
+<pins>
+ <pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="Y16"/>
+ <pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="8" name ="sws_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="9" name ="sws_4bits_tri_i_1" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="10" name ="sws_4bits_tri_i_2" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="11" name ="sws_4bits_tri_i_3" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="12" name ="sys_clk" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="13" name ="TMDS_clk_p" iostandard="TMDS_33" loc="H16"/>
+ <pin index="14" name ="TMDS_clk_n" iostandard="TMDS_33" loc="H17"/>
+ <pin index="15" name ="TMDS_data_p_0" iostandard="TMDS_33" loc="D19"/>
+ <pin index="16" name ="TMDS_data_p_1" iostandard="TMDS_33" loc="C20"/>
+ <pin index="17" name ="TMDS_data_p_2" iostandard="TMDS_33" loc="B19"/>
+ <pin index="18" name ="TMDS_data_n_0" iostandard="TMDS_33" loc="D20"/>
+ <pin index="19" name ="TMDS_data_n_1" iostandard="TMDS_33" loc="B20"/>
+ <pin index="20" name ="TMDS_data_n_2" iostandard="TMDS_33" loc="A20"/>
+ <pin index="21" name ="hdmi_ddc_sda" iostandard="LVCMOS33" loc="G18"/>
+ <pin index="22" name ="hdmi_ddc_scl" iostandard="LVCMOS33" loc="G17"/>
+ <pin index="23" name ="hdmi_hpd" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="24" name ="hdmi_out_en" iostandard="LVCMOS33" loc="F17"/>
+ <pin index="25" name ="JB1" iostandard="LVCMOS33" loc="T20"/>
+ <pin index="26" name ="JB2" iostandard="LVCMOS33" loc="U20"/>
+ <pin index="27" name ="JB3" iostandard="LVCMOS33" loc="V20"/>
+ <pin index="28" name ="JB4" iostandard="LVCMOS33" loc="W20"/>
+ <pin index="29" name ="JB7" iostandard="LVCMOS33" loc="Y18"/>
+ <pin index="30" name ="JB8" iostandard="LVCMOS33" loc="Y19"/>
+ <pin index="31" name ="JB9" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="32" name ="JB10" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="33" name ="JC1" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="34" name ="JC2" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="35" name ="JC3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="36" name ="JC4" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="37" name ="JC7" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="38" name ="JC8" iostandard="LVCMOS33" loc="Y14"/>
+ <pin index="39" name ="JC9" iostandard="LVCMOS33" loc="T12"/>
+ <pin index="40" name ="JC10" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="41" name ="JA1" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="42" name ="JA2" iostandard="LVCMOS33" loc="L14"/>
+ <pin index="43" name ="JA3" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="44" name ="JA4" iostandard="LVCMOS33" loc="K14"/>
+ <pin index="45" name ="JA7" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="46" name ="JA8" iostandard="LVCMOS33" loc="L15"/>
+ <pin index="47" name ="JA9" iostandard="LVCMOS33" loc="J16"/>
+ <pin index="48" name ="JA10" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="49" name ="JD1" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="50" name ="JD2" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="51" name ="JD3" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="52" name ="JD4" iostandard="LVCMOS33" loc="R14"/>
+ <pin index="53" name ="JD7" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="54" name ="JD8" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="55" name ="JD9" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="56" name ="JD10" iostandard="LVCMOS33" loc="V18"/>
+ <pin index="57" name ="JE1" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="58" name ="JE2" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="59" name ="JE3" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="60" name ="JE4" iostandard="LVCMOS33" loc="H15"/>
+ <pin index="61" name ="JE7" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="62" name ="JE8" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="63" name ="JE9" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="64" name ="JE10" iostandard="LVCMOS33" loc="Y17"/>
+</pins>
+</part_info>
diff --git a/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/preset.xml b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/preset.xml
new file mode 100644
index 000000000..110a6172e
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/new/board_files/zybo/B.3/preset.xml
@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+ <ip_preset preset_proc_name="ps7_preset">
+ <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+ <user_parameters>
+ <user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
+ <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/>
+ <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+ <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/>
+ <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>
+ <user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="HSTL 1.8V"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
+ <user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="disabled"/>
+ <user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
+ <user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="fast"/>
+ <user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
+ <user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
+ <user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50"/>
+ <user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.176"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.159"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.162"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.187"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="-0.073"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="-0.034"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.03"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.082"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K128M16 JT-125"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
+ <user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+ <user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="dip_switches_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="push_buttons_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
+ <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="led_4bits_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="output_1bit_preset">
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
+ <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI1" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI2" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI3" value="1"/>
+ <user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_GPI4" value="1"/>
+ <user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+
+ <ip_preset preset_proc_name="sys_clock_preset">
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+ <user_parameters>
+ <user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ <ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+ <user_parameters>
+ <user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
+ <user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
+ <user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
+ <user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
+ </user_parameters>
+ </ip>
+ </ip_preset>
+</ip_presets>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml
new file mode 100644
index 000000000..d7e39d2db
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/board_part.xml
@@ -0,0 +1,704 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Arty" board_revision="C.0" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+ <part_info part_name="xc7a35ticsg324-1L" device="xc7a35t" family="artix7" jtag_position="1" package="csg324" silicon_version="1.0" speed_grade="1L"/>
+
+ <board_info description="Arty" display_name="Arty" url="www.digilentinc.com/Arty"/>
+
+
+ <interfaces>
+
+ <interface mode="master" name="DDR3_SDRAM" type="xilinx.com:interface:ddrx_rtl:1.0">
+ <preset_file name="mig.prj"/>
+ </interface>
+
+ <interface mode="master" name="DIP_Switches_4Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="DIP_Switches_4Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="LED_4Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="LED_4Bits_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="RGB_LED" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="RGB_LED_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+
+ <interface mode="master" name="Push_Buttons_4Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="Push_Buttons_4Bits_TRI_I"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+ <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+ <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+ <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+ <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+ <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+
+ <port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+ <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+ <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+
+ <port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+ <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+ <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+
+ <port_map logical_port="SCK_I" physical_port="Qspi_CSn_i"/>
+ <port_map logical_port="SCK_O" physical_port="Qspi_CSn_o"/>
+ <port_map logical_port="SCK_T" physical_port="Qspi_CSn_t"/>
+
+ <port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+ <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+ <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+
+
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="I2C" type="xilinx.com:interface:iic_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="I2C_SDA_i"/>
+ <port_map logical_port="SDA_O" physical_port="I2C_SDA_o"/>
+ <port_map logical_port="SDA_T" physical_port="I2C_SDA_t"/>
+ <port_map logical_port="SCL_I" physical_port="I2C_SCL_i"/>
+ <port_map logical_port="SCL_O" physical_port="I2C_SCL_o"/>
+ <port_map logical_port="SCL_T" physical_port="I2C_SCL_t"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="I2C_PULLUPS" type="xilinx.com:interface:gpio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="I2C_PULLUP"/>
+ </port_maps>
+ </interface>
+
+
+ <interface mode="master" name="SPI" type="xilinx.com:interface:spi_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="SPI_MISO_i"/>
+ <port_map logical_port="IO0_O" physical_port="SPI_MISO_o"/>
+ <port_map logical_port="IO0_T" physical_port="SPI_MISO_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="SPI_MOSI_i"/>
+ <port_map logical_port="IO1_O" physical_port="SPI_MOSI_o"/>
+ <port_map logical_port="IO1_T" physical_port="SPI_MOSI_t"/>
+
+ <port_map logical_port="SCK_I" physical_port="SPI_SCLK_i"/>
+ <port_map logical_port="SCK_O" physical_port="SPI_SCLK_o"/>
+ <port_map logical_port="SCK_T" physical_port="SPI_SCLK_t"/>
+
+ <port_map logical_port="SS_I" physical_port="SPI_SS_i"/>
+ <port_map logical_port="SS_O" physical_port="SPI_SS_o"/>
+ <port_map logical_port="SS_T" physical_port="SPI_SS_t"/>
+
+ </port_maps>
+ </interface>
+
+
+ <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+ <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+ <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+ <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+ </port_maps>
+ </interface>
+
+
+
+<interface mode="master" name="ETH_mii" type="xilinx.com:interface:mii_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="ETH_txd"/>
+ <port_map logical_port="TX_EN" physical_port="ETH_tx_en"/>
+ <port_map logical_port="RXD" physical_port="ETH_rxd"/>
+ <port_map logical_port="RX_DV" physical_port="ETH_rx_dv"/>
+ <port_map logical_port="RX_ER" physical_port="ETH_rx_er"/>
+ <port_map logical_port="CRS" physical_port="ETH_crs"/>
+ <port_map logical_port="COL" physical_port="ETH_col"/>
+ <port_map logical_port="TX_CLK" physical_port="ETH_tx_clk"/>
+ <port_map logical_port="RX_CLK" physical_port="ETH_rx_clk"/>
+ <port_map logical_port="RST_N" physical_port="ETH_rstn"/>
+ </port_maps>
+ </interface>
+
+
+
+ <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk"/>
+ </port_maps>
+
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+
+ </interface>
+
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="RESET"/>
+ </port_maps>
+ <parameters>
+ <parameter name="RST_POLARITY" value="0"/>
+ </parameters>
+ </interface>
+
+ <interface mode="master" name="shield_dp0_dp19" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="SHEILD_dp0_dp19_TRI_I"/>
+ <port_map logical_port="TRI_O" physical_port="SHEILD_dp0_dp19_TRI_O"/>
+ <port_map logical_port="TRI_T" physical_port="SHEILD_dp0_dp19_TRI_T"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="SHEILD_dp26_dp41_TRI_I"/>
+ <port_map logical_port="TRI_O" physical_port="SHEILD_dp26_dp41_TRI_O"/>
+ <port_map logical_port="TRI_T" physical_port="SHEILD_dp26_dp41_TRI_T"/>
+ </port_maps>
+
+ </interface>
+
+
+ </interfaces>
+
+
+ <ports>
+
+ <port name="DIP_Switches_4Bits_TRI_I" dir="in" left="3" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="A8"/>
+ <pin index="1" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="2" iostandard="LVCMOS33" loc="C10"/>
+ <pin index="3" iostandard="LVCMOS33" loc="A10"/>
+ </pins>
+ </port>
+
+ <port name="LED_4Bits_TRI_O" dir="out" left="3" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="H5"/>
+ <pin index="1" iostandard="LVCMOS33" loc="J5"/>
+ <pin index="2" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="3" iostandard="LVCMOS33" loc="T10"/>
+ </pins>
+ </port>
+
+
+ <port dir="out" left="11" name="RGB_LED_TRI_O" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="E1"/>
+ <pin index="1" iostandard="LVCMOS33" loc="F6"/>
+ <pin index="2" iostandard="LVCMOS33" loc="G6"/>
+ <pin index="3" iostandard="LVCMOS33" loc="G4"/>
+ <pin index="4" iostandard="LVCMOS33" loc="J4"/>
+ <pin index="5" iostandard="LVCMOS33" loc="G3"/>
+ <pin index="6" iostandard="LVCMOS33" loc="H4"/>
+ <pin index="7" iostandard="LVCMOS33" loc="J2"/>
+ <pin index="8" iostandard="LVCMOS33" loc="J3"/>
+ <pin index="9" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="10" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="11" iostandard="LVCMOS33" loc="K1"/>
+ </pins>
+ </port>
+
+ <port name="Push_Buttons_4Bits_TRI_I" dir="in" left="3" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="D9"/>
+ <pin index="1" iostandard="LVCMOS33" loc="C9"/>
+ <pin index="2" iostandard="LVCMOS33" loc="B9"/>
+ <pin index="3" iostandard="LVCMOS33" loc="B8"/>
+ </pins>
+ </port>
+ <port name="RESET" dir="in" >
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C2"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="USB_Uart_RxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+ <port dir="out" name="USB_Uart_TxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D10"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="Qspi_DB0_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB1_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB2_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB3_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_sclk_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L16"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_sclk_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L16"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_sclk_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L16"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_CSn_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="I2C_SCL_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L18"/>
+ </pins>
+ </port>
+ <port dir="out" name="I2C_SCL_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L18"/>
+ </pins>
+ </port>
+ <port dir="out" name="I2C_SCL_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="I2C_SDA_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M18"/>
+ </pins>
+ </port>
+ <port dir="out" name="I2C_SDA_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M18"/>
+ </pins>
+ </port>
+ <port dir="out" name="I2C_SDA_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M18"/>
+ </pins>
+ </port>
+
+ <port dir="out" left="1" name="I2C_PULLUP" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="A14"/>
+ <pin index="1" iostandard="LVCMOS33" loc="A13"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="SPI_MISO_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_MISO_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_MISO_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G1"/>
+ </pins>
+ </port>
+ <port dir="in" name="SPI_MOSI_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="H1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_MOSI_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="H1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_MOSI_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="H1"/>
+ </pins>
+ </port>
+ <port dir="in" name="SPI_SCLK_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_SCLK_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_SCLK_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F1"/>
+ </pins>
+ </port>
+ <port dir="in" name="SPI_SS_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_SS_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C1"/>
+ </pins>
+ </port>
+ <port dir="out" name="SPI_SS_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C1"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="out" name="ETH_mdc">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F16"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_mdio_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K13"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdio_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K13"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdio_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K13"/>
+ </pins>
+ </port>
+
+
+ <port dir="out" left="3" name="ETH_txd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="H14"/>
+ <pin index="1" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="2" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="H17"/>
+ </pins>
+ </port>
+
+ <port dir="in" left="3" name="ETH_rxd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="D18"/>
+ <pin index="1" iostandard="LVCMOS33" loc="E17"/>
+ <pin index="2" iostandard="LVCMOS33" loc="E18"/>
+ <pin index="3" iostandard="LVCMOS33" loc="G17"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_tx_en">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="H15"/>
+ </pins>
+ </port>
+ <port dir="in" name="ETH_rx_dv">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G16"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_rx_er">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C17"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_crs">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G14"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_col">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D17"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_tx_clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="H16"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_rx_clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F15"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_rstn">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C16"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E3"/>
+ </pins>
+ </port>
+
+ <port name="SHEILD_dp0_dp19_TRI_I" dir="in" left="19" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="6" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="7" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="8" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="9" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="10" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="12" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="13" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="14" iostandard="LVCMOS33" loc="F5"/>
+ <pin index="15" iostandard="LVCMOS33" loc="D8"/>
+ <pin index="16" iostandard="LVCMOS33" loc="C7"/>
+ <pin index="17" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="18" iostandard="LVCMOS33" loc="D7"/>
+ <pin index="19" iostandard="LVCMOS33" loc="D5"/>
+ </pins>
+ </port>
+
+ <port name="SHEILD_dp0_dp19_TRI_O" dir="out" left="19" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="6" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="7" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="8" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="9" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="10" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="12" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="13" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="14" iostandard="LVCMOS33" loc="F5"/>
+ <pin index="15" iostandard="LVCMOS33" loc="D8"/>
+ <pin index="16" iostandard="LVCMOS33" loc="C7"/>
+ <pin index="17" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="18" iostandard="LVCMOS33" loc="D7"/>
+ <pin index="19" iostandard="LVCMOS33" loc="D5"/>
+ </pins>
+ </port>
+
+ <port name="SHEILD_dp0_dp19_TRI_T" dir="out" left="19" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="3" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="6" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="7" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="8" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="9" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="10" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="12" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="13" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="14" iostandard="LVCMOS33" loc="F5"/>
+ <pin index="15" iostandard="LVCMOS33" loc="D8"/>
+ <pin index="16" iostandard="LVCMOS33" loc="C7"/>
+ <pin index="17" iostandard="LVCMOS33" loc="E7"/>
+ <pin index="18" iostandard="LVCMOS33" loc="D7"/>
+ <pin index="19" iostandard="LVCMOS33" loc="D5"/>
+ </pins>
+ </port>
+
+ <port name="SHEILD_dp26_dp41_TRI_I" dir="in" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="5" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="6" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="7" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="9" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="10" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="13" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="14" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="15" iostandard="LVCMOS33" loc="N17"/>
+ </pins>
+ </port>
+
+ <port name="SHEILD_dp26_dp41_TRI_O" dir="out" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="5" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="6" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="7" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="9" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="10" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="13" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="14" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="15" iostandard="LVCMOS33" loc="N17"/>
+ </pins>
+ </port>
+
+ <port name="SHEILD_dp26_dp41_TRI_T" dir="out" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="5" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="6" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="7" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="8" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="9" iostandard="LVCMOS33" loc="N16"/>
+ <pin index="10" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="12" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="13" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="14" iostandard="LVCMOS33" loc="P18"/>
+ <pin index="15" iostandard="LVCMOS33" loc="N17"/>
+ </pins>
+ </port>
+
+ </ports>
+
+</board_part>
+
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/mig.prj b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/mig.prj
new file mode 100644
index 000000000..9b31d7bc8
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/C.0/mig.prj
@@ -0,0 +1,134 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
+ <Version>2.3</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>No Buffer</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+ <TimePeriod>3000</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>166.666</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>666</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.35V</MemoryVoltage>
+ <C0_MEM_SIZE>268435456</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini
new file mode 100644
index 000000000..d957fd188
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/arty/desktop.ini
@@ -0,0 +1,4 @@
+[ViewState]
+Mode=
+Vid=
+FolderType=Generic
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml
new file mode 100644
index 000000000..cd473b463
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/basys3/1.1/board_part.xml
@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Basys3" board_revision="1.1" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+ <part_info part_name="xc7a35tcpg236-1" device="xc7a35t" family="artix7" jtag_position="1" package="cpg236" silicon_version="1.0" speed_grade="1"/>
+
+ <board_info description="Basys3 Artix-7 FPGA Board" display_name="Basys3 Artix-7 FPGA Board" url="www.digilentinc.com/basys3"/>
+
+
+ <interfaces>
+
+
+ <interface mode="master" name="DIP_Switches_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="DIP_Switches_16Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="LED_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="LED_16Bits_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="SEVEN_SEG_LED_DISP" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_DISP_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="SEVEN_SEG_LED_AN" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_AN_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+ <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+ <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+ <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+ <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+ <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+
+
+ <port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+ <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+ <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+
+ <port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+ <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+ <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+
+ <port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+ <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+ <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+
+ </port_maps>
+
+ </interface>
+
+ <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="clk"/>
+ </port_maps>
+
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+
+ </interface>
+
+ <interface mode="slave" name="Reset" type="xilinx.com:signal:reset_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="RST" physical_port="RESET"/>
+ </port_maps>
+ <parameters>
+ <parameter name="RST_POLARITY" value="1"/>
+ </parameters>
+ </interface>
+
+ </interfaces>
+
+
+ <ports>
+
+ <port name="DIP_Switches_16Bits_TRI_I" dir="in" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="1" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="W16"/>
+ <pin index="3" iostandard="LVCMOS33" loc="W17"/>
+ <pin index="4" iostandard="LVCMOS33" loc="W15"/>
+ <pin index="5" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="6" iostandard="LVCMOS33" loc="W14"/>
+ <pin index="7" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="8" iostandard="LVCMOS33" loc="V2"/>
+ <pin index="9" iostandard="LVCMOS33" loc="T3"/>
+ <pin index="10" iostandard="LVCMOS33" loc="T2"/>
+ <pin index="11" iostandard="LVCMOS33" loc="R3"/>
+ <pin index="12" iostandard="LVCMOS33" loc="W2"/>
+ <pin index="13" iostandard="LVCMOS33" loc="U1"/>
+ <pin index="14" iostandard="LVCMOS33" loc="T1"/>
+ <pin index="15" iostandard="LVCMOS33" loc="R2"/>
+ </pins>
+ </port>
+
+ <port name="LED_16Bits_TRI_O" dir="out" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="1" iostandard="LVCMOS33" loc="E19"/>
+ <pin index="2" iostandard="LVCMOS33" loc="U19"/>
+ <pin index="3" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="4" iostandard="LVCMOS33" loc="W18"/>
+ <pin index="5" iostandard="LVCMOS33" loc="U15"/>
+ <pin index="6" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="7" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="8" iostandard="LVCMOS33" loc="V13"/>
+ <pin index="9" iostandard="LVCMOS33" loc="V3"/>
+ <pin index="10" iostandard="LVCMOS33" loc="W3"/>
+ <pin index="11" iostandard="LVCMOS33" loc="U3"/>
+ <pin index="12" iostandard="LVCMOS33" loc="P3"/>
+ <pin index="13" iostandard="LVCMOS33" loc="N3"/>
+ <pin index="14" iostandard="LVCMOS33" loc="P1"/>
+ <pin index="15" iostandard="LVCMOS33" loc="L1"/>
+ </pins>
+ </port>
+
+ <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="3" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="1" iostandard="LVCMOS33" loc="W19"/>
+ <pin index="2" iostandard="LVCMOS33" loc="T17"/>
+ <pin index="3" iostandard="LVCMOS33" loc="U17"/>
+ </pins>
+ </port>
+
+ <port name="RESET" dir="in" >
+ <pins>
+ <pin iostandard="LVCMOS33" loc="U18"/>
+ </pins>
+ </port>
+
+
+ <port name="SEVEN_SEG_LED_DISP_TRI_O" dir="out" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="W7"/>
+ <pin index="1" iostandard="LVCMOS33" loc="W6"/>
+ <pin index="2" iostandard="LVCMOS33" loc="U8"/>
+ <pin index="3" iostandard="LVCMOS33" loc="V8"/>
+ <pin index="4" iostandard="LVCMOS33" loc="U5"/>
+ <pin index="5" iostandard="LVCMOS33" loc="V5"/>
+ <pin index="6" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="7" iostandard="LVCMOS33" loc="V7"/>
+ </pins>
+ </port>
+
+ <port name="SEVEN_SEG_LED_AN_TRI_O" dir="out" left="3" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="U2"/>
+ <pin index="1" iostandard="LVCMOS33" loc="U4"/>
+ <pin index="2" iostandard="LVCMOS33" loc="V4"/>
+ <pin index="3" iostandard="LVCMOS33" loc="W4"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="USB_Uart_RxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="B18"/>
+ </pins>
+ </port>
+ <port dir="out" name="USB_Uart_TxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB0_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB1_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D19"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D19"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D19"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB2_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB3_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_CSn_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K19"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K19"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K19"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W5"/>
+ </pins>
+ </port>
+
+ </ports>
+
+</board_part>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml
new file mode 100644
index 000000000..639fec2b0
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4/1.1/board_part.xml
@@ -0,0 +1,654 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Nexys4" board_revision="1.1" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+ <part_info part_name="xc7a100tcsg324-1" device="xc7a100t" family="artix7" jtag_position="1" package="csg324" silicon_version="1.0" speed_grade="1"/>
+
+ <board_info description="Nexys4 FPGA Board" display_name="Nexys4 FPGA Board" url="www.digilentinc.com/nexys4"/>
+
+
+ <interfaces>
+
+ <interface mode="master" name="DIP_Switches_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="DIP_Switches_16Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="LED_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="LED_16Bits_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="DUAL_SEVEN_SEG_LED_DISP" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="DUAL_SEVEN_SEG_LED_DISP_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="SEVEN_SEG_LED_AN" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_AN_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+ <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="SCK_I" physical_port="Qspi_SCK_i"/>
+ <port_map logical_port="SCK_O" physical_port="Qspi_SCK_o"/>
+ <port_map logical_port="SCK_T" physical_port="Qspi_SCK_t"/>
+
+ <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+ <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+ <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+ <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+ <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+
+
+ <port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+ <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+ <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+
+ <port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+ <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+ <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+
+ <port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+ <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+ <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+
+ </port_maps>
+
+ </interface>
+
+
+ <interface mode="master" name="TEMP_SENSOR" type="xilinx.com:interface:iic_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="TEMP_SDA_i"/>
+ <port_map logical_port="SDA_O" physical_port="TEMP_SDA_o"/>
+ <port_map logical_port="SDA_T" physical_port="TEMP_SDA_t"/>
+ <port_map logical_port="SCL_I" physical_port="TEMP_SCL_i"/>
+ <port_map logical_port="SCL_O" physical_port="TEMP_SCL_o"/>
+ <port_map logical_port="SCL_T" physical_port="TEMP_SCL_t"/>
+ </port_maps>
+ </interface>
+
+
+ <interface mode="master" name="ACL_SPI" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="ACL_MISO_i"/>
+ <port_map logical_port="IO0_O" physical_port="ACL_MISO_o"/>
+ <port_map logical_port="IO0_T" physical_port="ACL_MISO_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="ACL_MOSI_i"/>
+ <port_map logical_port="IO1_O" physical_port="ACL_MOSI_o"/>
+ <port_map logical_port="IO1_T" physical_port="ACL_MOSI_t"/>
+
+ <port_map logical_port="SCK_I" physical_port="ACL_SCLK_i"/>
+ <port_map logical_port="SCK_O" physical_port="ACL_SCLK_o"/>
+ <port_map logical_port="SCK_T" physical_port="ACL_SCLK_t"/>
+
+
+ <port_map logical_port="SS_I" physical_port="ACL_SS_i"/>
+ <port_map logical_port="SS_O" physical_port="ACL_SS_o"/>
+ <port_map logical_port="SS_T" physical_port="ACL_SS_t"/>
+
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+ <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+ <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+ <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ETH_rmii" type="xilinx.com:interface:rmii_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="ETH_rmii_txd"/>
+ <port_map logical_port="RXD" physical_port="ETH_rmii_rxd"/>
+ <port_map logical_port="TX_EN" physical_port="ETH_rmii_tx_en"/>
+ <port_map logical_port="RX_ER" physical_port="ETH_rmii_rx_er"/>
+ <port_map logical_port="CRS_DV" physical_port="ETH_rmii_crs_dv"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="cellular_RAM" type="xilinx.com:interface:emc_rtl:1.0" preset_proc_name="emc_preset">
+ <port_maps>
+ <port_map logical_port="ADDR" physical_port="cellular_RAM_addr"/>
+ <port_map logical_port="DQ_O" physical_port="cellular_RAM_dq_o"/>
+ <port_map logical_port="DQ_I" physical_port="cellular_RAM_dq_i"/>
+ <port_map logical_port="DQ_T" physical_port="cellular_RAM_dq_t"/>
+ <port_map logical_port="ADV_LDN" physical_port="cellular_RAM_adv_ldn"/>
+ <port_map logical_port="OEN" physical_port="cellular_RAM_oen"/>
+ <port_map logical_port="WEN" physical_port="cellular_RAM_wen"/>
+ <port_map logical_port="CE_N" physical_port="cellular_RAM_ce_n"/>
+ <port_map logical_port="CRE" physical_port="cellular_RAM_cre"/>
+ <port_map logical_port="BEN" physical_port="cellular_RAM_ben"/>
+ <port_map logical_port="WAIT" physical_port="cellular_RAM_wait"/>
+ </port_maps>
+ </interface>
+
+
+ <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk"/>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+ </interface>
+
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="RESET"/>
+ </port_maps>
+ <parameters>
+ <parameter name="RST_POLARITY" value="1"/>
+ </parameters>
+ </interface>
+
+ </interfaces>
+
+
+ <ports>
+
+ <port name="DIP_Switches_16Bits_TRI_I" dir="in" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="U9"/>
+ <pin index="1" iostandard="LVCMOS33" loc="U8"/>
+ <pin index="2" iostandard="LVCMOS33" loc="R7"/>
+ <pin index="3" iostandard="LVCMOS33" loc="R6"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R5"/>
+ <pin index="5" iostandard="LVCMOS33" loc="V7"/>
+ <pin index="6" iostandard="LVCMOS33" loc="V6"/>
+ <pin index="7" iostandard="LVCMOS33" loc="V5"/>
+ <pin index="8" iostandard="LVCMOS33" loc="U4"/>
+ <pin index="9" iostandard="LVCMOS33" loc="V2"/>
+ <pin index="10" iostandard="LVCMOS33" loc="U2"/>
+ <pin index="11" iostandard="LVCMOS33" loc="T3"/>
+ <pin index="12" iostandard="LVCMOS33" loc="T1"/>
+ <pin index="13" iostandard="LVCMOS33" loc="R3"/>
+ <pin index="14" iostandard="LVCMOS33" loc="P3"/>
+ <pin index="15" iostandard="LVCMOS33" loc="P4"/>
+ </pins>
+ </port>
+
+ <port name="LED_16Bits_TRI_O" dir="out" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="T8"/>
+ <pin index="1" iostandard="LVCMOS33" loc="V9"/>
+ <pin index="2" iostandard="LVCMOS33" loc="R8"/>
+ <pin index="3" iostandard="LVCMOS33" loc="T6"/>
+ <pin index="4" iostandard="LVCMOS33" loc="T5"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T4"/>
+ <pin index="6" iostandard="LVCMOS33" loc="U7"/>
+ <pin index="7" iostandard="LVCMOS33" loc="U6"/>
+ <pin index="8" iostandard="LVCMOS33" loc="V4"/>
+ <pin index="9" iostandard="LVCMOS33" loc="U3"/>
+ <pin index="10" iostandard="LVCMOS33" loc="V1"/>
+ <pin index="11" iostandard="LVCMOS33" loc="R1"/>
+ <pin index="12" iostandard="LVCMOS33" loc="P5"/>
+ <pin index="13" iostandard="LVCMOS33" loc="U1"/>
+ <pin index="14" iostandard="LVCMOS33" loc="R2"/>
+ <pin index="15" iostandard="LVCMOS33" loc="P2"/>
+ </pins>
+ </port>
+
+ <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="3" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="F15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="V10"/>
+ <pin index="3" iostandard="LVCMOS33" loc="R10"/>
+ </pins>
+ </port>
+
+ <port name="RESET" dir="in" >
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E16"/>
+ </pins>
+ </port>
+
+
+ <port name="DUAL_SEVEN_SEG_LED_DISP_TRI_O" dir="out" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="L3"/>
+ <pin index="1" iostandard="LVCMOS33" loc="N1"/>
+ <pin index="2" iostandard="LVCMOS33" loc="L5"/>
+ <pin index="3" iostandard="LVCMOS33" loc="L4"/>
+ <pin index="4" iostandard="LVCMOS33" loc="K3"/>
+ <pin index="5" iostandard="LVCMOS33" loc="M2"/>
+ <pin index="6" iostandard="LVCMOS33" loc="L6"/>
+ <pin index="7" iostandard="LVCMOS33" loc="M4"/>
+ </pins>
+ </port>
+
+ <port name="SEVEN_SEG_LED_AN_TRI_O" dir="out" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="N6"/>
+ <pin index="1" iostandard="LVCMOS33" loc="M6"/>
+ <pin index="2" iostandard="LVCMOS33" loc="M3"/>
+ <pin index="3" iostandard="LVCMOS33" loc="N5"/>
+ <pin index="4" iostandard="LVCMOS33" loc="N2"/>
+ <pin index="5" iostandard="LVCMOS33" loc="N4"/>
+ <pin index="6" iostandard="LVCMOS33" loc="L1"/>
+ <pin index="7" iostandard="LVCMOS33" loc="M1"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="USB_Uart_RxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C4"/>
+ </pins>
+ </port>
+ <port dir="out" name="USB_Uart_TxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D4"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="Qspi_SCK_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E9"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_SCK_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E9"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_SCK_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E9"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB0_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB1_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB2_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB3_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_CSn_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="TEMP_SDA_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G16"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SDA_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G16"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SDA_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="G16"/>
+ </pins>
+ </port>
+ <port dir="in" name="TEMP_SCL_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F16"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SCL_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F16"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SCL_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F16"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ACL_MISO_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D13"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MISO_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D13"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MISO_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D13"/>
+ </pins>
+ </port>
+ <port dir="in" name="ACL_MOSI_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="B14"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MOSI_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="B14"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MOSI_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="B14"/>
+ </pins>
+ </port>
+ <port dir="in" name="ACL_SCLK_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SCLK_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SCLK_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D15"/>
+ </pins>
+ </port>
+ <port dir="in" name="ACL_SS_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SS_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SS_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C15"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdc">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C9"/>
+ </pins>
+ </port>
+ <port dir="in" name="ETH_mdio_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+ <port dir="out" name="ETH_mdio_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+ <port dir="out" name="ETH_mdio_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+ <port dir="out" left="1" name="ETH_rmii_txd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="1" iostandard="LVCMOS33" loc="A8"/>
+ </pins>
+ </port>
+ <port dir="in" left="1" name="ETH_rmii_rxd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="D10"/>
+ <pin index="1" iostandard="LVCMOS33" loc="C11"/>
+ </pins>
+ </port>
+ <port dir="out" name="ETH_rmii_tx_en">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="B9"/>
+ </pins>
+ </port>
+ <port dir="in" name="ETH_rmii_rx_er">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C10"/>
+ </pins>
+ </port>
+ <port dir="in" name="ETH_rmii_crs_dv">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D9"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="inout" name="cellular_RAM_adv_ldn">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="T13"/>
+ </pins>
+ </port>
+ <port dir="inout" name="cellular_RAM_oen">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="H14"/>
+ </pins>
+ </port>
+ <port dir="inout" name="cellular_RAM_ce_n">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L18"/>
+ </pins>
+ </port>
+ <port dir="inout" name="cellular_RAM_wen">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R11"/>
+ </pins>
+ </port>
+ <port dir="inout" name="cellular_RAM_cre">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="J14"/>
+ </pins>
+ </port>
+ <port dir="inout" left="1" name="cellular_RAM_ben" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="J13"/>
+ </pins>
+ </port>
+ <port dir="inout" name="cellular_RAM_wait">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="T14"/>
+ </pins>
+ </port>
+<port dir="inout" left="22" name="cellular_RAM_addr" right="0">
+<pins>
+<pin index="0" iostandard="LVCMOS33" loc="J18"/>
+<pin index="1" iostandard="LVCMOS33" loc="H17"/>
+<pin index="2" iostandard="LVCMOS33" loc="H15"/>
+<pin index="3" iostandard="LVCMOS33" loc="J17"/>
+<pin index="4" iostandard="LVCMOS33" loc="H16"/>
+<pin index="5" iostandard="LVCMOS33" loc="K15"/>
+<pin index="6" iostandard="LVCMOS33" loc="K13"/>
+<pin index="7" iostandard="LVCMOS33" loc="N15"/>
+<pin index="8" iostandard="LVCMOS33" loc="V16"/>
+<pin index="9" iostandard="LVCMOS33" loc="U14"/>
+<pin index="10" iostandard="LVCMOS33" loc="V14"/>
+<pin index="11" iostandard="LVCMOS33" loc="V12"/>
+<pin index="12" iostandard="LVCMOS33" loc="P14"/>
+<pin index="13" iostandard="LVCMOS33" loc="U16"/>
+<pin index="14" iostandard="LVCMOS33" loc="R15"/>
+<pin index="15" iostandard="LVCMOS33" loc="N14"/>
+<pin index="16" iostandard="LVCMOS33" loc="N16"/>
+<pin index="17" iostandard="LVCMOS33" loc="M13"/>
+<pin index="18" iostandard="LVCMOS33" loc="V17"/>
+<pin index="19" iostandard="LVCMOS33" loc="U17"/>
+<pin index="20" iostandard="LVCMOS33" loc="T10"/>
+<pin index="21" iostandard="LVCMOS33" loc="M16"/>
+<pin index="22" iostandard="LVCMOS33" loc="U13"/>
+</pins>
+</port>
+<port dir="in" left="15" name="cellular_RAM_dq_i" right="0">
+<pins>
+<pin index="0" iostandard="LVCMOS33" loc="R12"/>
+<pin index="1" iostandard="LVCMOS33" loc="T11"/>
+<pin index="2" iostandard="LVCMOS33" loc="U12"/>
+<pin index="3" iostandard="LVCMOS33" loc="R13"/>
+<pin index="4" iostandard="LVCMOS33" loc="U18"/>
+<pin index="5" iostandard="LVCMOS33" loc="R17"/>
+<pin index="6" iostandard="LVCMOS33" loc="T18"/>
+<pin index="7" iostandard="LVCMOS33" loc="R18"/>
+<pin index="8" iostandard="LVCMOS33" loc="F18"/>
+<pin index="9" iostandard="LVCMOS33" loc="G18"/>
+<pin index="10" iostandard="LVCMOS33" loc="G17"/>
+<pin index="11" iostandard="LVCMOS33" loc="M18"/>
+<pin index="12" iostandard="LVCMOS33" loc="M17"/>
+<pin index="13" iostandard="LVCMOS33" loc="P18"/>
+<pin index="14" iostandard="LVCMOS33" loc="N17"/>
+<pin index="15" iostandard="LVCMOS33" loc="P17"/>
+</pins>
+</port>
+<port dir="out" left="15" name="cellular_RAM_dq_o" right="0">
+<pins>
+<pin index="0" iostandard="LVCMOS33" loc="R12"/>
+<pin index="1" iostandard="LVCMOS33" loc="T11"/>
+<pin index="2" iostandard="LVCMOS33" loc="U12"/>
+<pin index="3" iostandard="LVCMOS33" loc="R13"/>
+<pin index="4" iostandard="LVCMOS33" loc="U18"/>
+<pin index="5" iostandard="LVCMOS33" loc="R17"/>
+<pin index="6" iostandard="LVCMOS33" loc="T18"/>
+<pin index="7" iostandard="LVCMOS33" loc="R18"/>
+<pin index="8" iostandard="LVCMOS33" loc="F18"/>
+<pin index="9" iostandard="LVCMOS33" loc="G18"/>
+<pin index="10" iostandard="LVCMOS33" loc="G17"/>
+<pin index="11" iostandard="LVCMOS33" loc="M18"/>
+<pin index="12" iostandard="LVCMOS33" loc="M17"/>
+<pin index="13" iostandard="LVCMOS33" loc="P18"/>
+<pin index="14" iostandard="LVCMOS33" loc="N17"/>
+<pin index="15" iostandard="LVCMOS33" loc="P17"/>
+</pins>
+</port>
+<port dir="out" left="15" name="cellular_RAM_dq_t" right="0">
+<pins>
+<pin index="0" iostandard="LVCMOS33" loc="R12"/>
+<pin index="1" iostandard="LVCMOS33" loc="T11"/>
+<pin index="2" iostandard="LVCMOS33" loc="U12"/>
+<pin index="3" iostandard="LVCMOS33" loc="R13"/>
+<pin index="4" iostandard="LVCMOS33" loc="U18"/>
+<pin index="5" iostandard="LVCMOS33" loc="R17"/>
+<pin index="6" iostandard="LVCMOS33" loc="T18"/>
+<pin index="7" iostandard="LVCMOS33" loc="R18"/>
+<pin index="8" iostandard="LVCMOS33" loc="F18"/>
+<pin index="9" iostandard="LVCMOS33" loc="G18"/>
+<pin index="10" iostandard="LVCMOS33" loc="G17"/>
+<pin index="11" iostandard="LVCMOS33" loc="M18"/>
+<pin index="12" iostandard="LVCMOS33" loc="M17"/>
+<pin index="13" iostandard="LVCMOS33" loc="P18"/>
+<pin index="14" iostandard="LVCMOS33" loc="N17"/>
+<pin index="15" iostandard="LVCMOS33" loc="P17"/>
+</pins>
+</port>
+
+
+ <port dir="in" name="clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E3"/>
+ </pins>
+ </port>
+
+ </ports>
+
+</board_part>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml
new file mode 100644
index 000000000..698b5bdfb
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/board_part.xml
@@ -0,0 +1,539 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Nexys4_DDR" board_revision="1.1" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+ <part_info part_name="xc7a100tcsg324-1" device="xc7a100t" family="artix7" jtag_position="1" package="csg324" silicon_version="1.0" speed_grade="1"/>
+
+ <board_info description="Nexys4 DDR" display_name="Nexys4 DDR" url="www.digilentinc.com/nexys4"/>
+
+
+ <interfaces>
+
+ <interface mode="master" name="DDR2_SDRAM" type="xilinx.com:interface:ddrx_rtl:1.0">
+ <preset_file name="mig.prj"/>
+ </interface>
+
+ <interface mode="master" name="DIP_Switches_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="DIP_Switches_16Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="LED_16Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="LED_16Bits_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="RGB_LED" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="RGB_LED_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+
+ <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="DUAL_SEVEN_SEG_LED_DISP" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="DUAL_SEVEN_SEG_LED_DISP_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="SEVEN_SEG_LED_AN" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="SEVEN_SEG_LED_AN_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+ <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+ <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+ <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+ <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+ <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+
+ <port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+ <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+ <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+
+ <port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+ <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+ <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+
+ <port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+ <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+ <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+
+ </port_maps>
+
+ </interface>
+
+
+ <interface mode="master" name="TEMP_SENSOR" type="xilinx.com:interface:iic_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="TEMP_SDA_i"/>
+ <port_map logical_port="SDA_O" physical_port="TEMP_SDA_o"/>
+ <port_map logical_port="SDA_T" physical_port="TEMP_SDA_t"/>
+ <port_map logical_port="SCL_I" physical_port="TEMP_SCL_i"/>
+ <port_map logical_port="SCL_O" physical_port="TEMP_SCL_o"/>
+ <port_map logical_port="SCL_T" physical_port="TEMP_SCL_t"/>
+ </port_maps>
+ </interface>
+
+
+ <interface mode="master" name="ACL_SPI" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="ACL_MISO_i"/>
+ <port_map logical_port="IO0_O" physical_port="ACL_MISO_o"/>
+ <port_map logical_port="IO0_T" physical_port="ACL_MISO_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="ACL_MOSI_i"/>
+ <port_map logical_port="IO1_O" physical_port="ACL_MOSI_o"/>
+ <port_map logical_port="IO1_T" physical_port="ACL_MOSI_t"/>
+
+ <port_map logical_port="SCK_I" physical_port="ACL_SCLK_i"/>
+ <port_map logical_port="SCK_O" physical_port="ACL_SCLK_o"/>
+ <port_map logical_port="SCK_T" physical_port="ACL_SCLK_t"/>
+
+
+ <port_map logical_port="SS_I" physical_port="ACL_SS_i"/>
+ <port_map logical_port="SS_O" physical_port="ACL_SS_o"/>
+ <port_map logical_port="SS_T" physical_port="ACL_SS_t"/>
+
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+ <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+ <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+ <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ETH_rmii" type="xilinx.com:interface:rmii_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TXD" physical_port="ETH_rmii_txd"/>
+ <port_map logical_port="RXD" physical_port="ETH_rmii_rxd"/>
+ <port_map logical_port="TX_EN" physical_port="ETH_rmii_tx_en"/>
+ <port_map logical_port="RX_ER" physical_port="ETH_rmii_rx_er"/>
+ <port_map logical_port="CRS_DV" physical_port="ETH_rmii_crs_dv"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="clk" physical_port="clk"/>
+ </port_maps>
+
+ <parameters>
+ <parameter name="frequency" value="100000000"/>
+ </parameters>
+
+ </interface>
+
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="RESET"/>
+ </port_maps>
+ <parameters>
+ <parameter name="RST_POLARITY" value="0"/>
+ </parameters>
+ </interface>
+
+
+
+
+ </interfaces>
+
+
+ <ports>
+
+ <port name="DIP_Switches_16Bits_TRI_I" dir="in" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="J15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="L16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="M13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="R15"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R17"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T18"/>
+ <pin index="6" iostandard="LVCMOS33" loc="U18"/>
+ <pin index="7" iostandard="LVCMOS33" loc="R13"/>
+ <pin index="8" iostandard="LVCMOS18" loc="T8"/>
+ <pin index="9" iostandard="LVCMOS18" loc="U8"/>
+ <pin index="10" iostandard="LVCMOS33" loc="R16"/>
+ <pin index="11" iostandard="LVCMOS33" loc="T13"/>
+ <pin index="12" iostandard="LVCMOS33" loc="H6"/>
+ <pin index="13" iostandard="LVCMOS33" loc="U12"/>
+ <pin index="14" iostandard="LVCMOS33" loc="U11"/>
+ <pin index="15" iostandard="LVCMOS33" loc="V10"/>
+ </pins>
+ </port>
+
+ <port name="LED_16Bits_TRI_O" dir="out" left="15" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="H17"/>
+ <pin index="1" iostandard="LVCMOS33" loc="K15"/>
+ <pin index="2" iostandard="LVCMOS33" loc="J13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="N14"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="5" iostandard="LVCMOS33" loc="V17"/>
+ <pin index="6" iostandard="LVCMOS33" loc="U17"/>
+ <pin index="7" iostandard="LVCMOS33" loc="U16"/>
+ <pin index="8" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="9" iostandard="LVCMOS33" loc="T15"/>
+ <pin index="10" iostandard="LVCMOS33" loc="U14"/>
+ <pin index="11" iostandard="LVCMOS33" loc="T16"/>
+ <pin index="12" iostandard="LVCMOS33" loc="V15"/>
+ <pin index="13" iostandard="LVCMOS33" loc="V14"/>
+ <pin index="14" iostandard="LVCMOS33" loc="V12"/>
+ <pin index="15" iostandard="LVCMOS33" loc="V11"/>
+ </pins>
+ </port>
+
+ <port dir="out" left="5" name="RGB_LED_TRI_O" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="R12"/>
+ <pin index="1" iostandard="LVCMOS33" loc="M16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="N15"/>
+ <pin index="3" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="4" iostandard="LVCMOS33" loc="R11"/>
+ <pin index="5" iostandard="LVCMOS33" loc="N16"/>
+ </pins>
+ </port>
+
+ <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="4" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="N17"/>
+ <pin index="1" iostandard="LVCMOS33" loc="M18"/>
+ <pin index="2" iostandard="LVCMOS33" loc="P17"/>
+ <pin index="3" iostandard="LVCMOS33" loc="M17"/>
+ <pin index="4" iostandard="LVCMOS33" loc="P18"/>
+ </pins>
+ </port>
+
+ <port name="RESET" dir="in" >
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C12"/>
+ </pins>
+ </port>
+
+
+ <port name="DUAL_SEVEN_SEG_LED_DISP_TRI_O" dir="out" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="T10"/>
+ <pin index="1" iostandard="LVCMOS33" loc="R10"/>
+ <pin index="2" iostandard="LVCMOS33" loc="K16"/>
+ <pin index="3" iostandard="LVCMOS33" loc="K13"/>
+ <pin index="4" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T11"/>
+ <pin index="6" iostandard="LVCMOS33" loc="L18"/>
+ <pin index="7" iostandard="LVCMOS33" loc="H15"/>
+ </pins>
+ </port>
+
+ <port name="SEVEN_SEG_LED_AN_TRI_O" dir="out" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="J17"/>
+ <pin index="1" iostandard="LVCMOS33" loc="J18"/>
+ <pin index="2" iostandard="LVCMOS33" loc="T9"/>
+ <pin index="3" iostandard="LVCMOS33" loc="J14"/>
+ <pin index="4" iostandard="LVCMOS33" loc="P14"/>
+ <pin index="5" iostandard="LVCMOS33" loc="T14"/>
+ <pin index="6" iostandard="LVCMOS33" loc="K2"/>
+ <pin index="7" iostandard="LVCMOS33" loc="U13"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="USB_Uart_RxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C4"/>
+ </pins>
+ </port>
+ <port dir="out" name="USB_Uart_TxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D4"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="Qspi_DB0_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K17"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB1_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="K18"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB2_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L14"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_DB3_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="M14"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="Qspi_CSn_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L13"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="TEMP_SDA_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C15"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SDA_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C15"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SDA_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C15"/>
+ </pins>
+ </port>
+ <port dir="in" name="TEMP_SCL_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C14"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SCL_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C14"/>
+ </pins>
+ </port>
+ <port dir="out" name="TEMP_SCL_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C14"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="ACL_MISO_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MISO_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MISO_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E15"/>
+ </pins>
+ </port>
+ <port dir="in" name="ACL_MOSI_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F14"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MOSI_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F14"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_MOSI_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F14"/>
+ </pins>
+ </port>
+ <port dir="in" name="ACL_SCLK_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SCLK_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SCLK_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="F15"/>
+ </pins>
+ </port>
+ <port dir="in" name="ACL_SS_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SS_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D15"/>
+ </pins>
+ </port>
+ <port dir="out" name="ACL_SS_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D15"/>
+ </pins>
+ </port>
+
+
+ <port dir="out" name="ETH_mdc">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C9"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_mdio_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdio_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdio_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="A9"/>
+ </pins>
+ </port>
+
+ <port dir="out" left="1" name="ETH_rmii_txd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="A10"/>
+ <pin index="1" iostandard="LVCMOS33" loc="A8"/>
+ </pins>
+ </port>
+
+ <port dir="in" left="1" name="ETH_rmii_rxd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="C11"/>
+ <pin index="1" iostandard="LVCMOS33" loc="D10"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_rmii_tx_en">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="B9"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="ETH_rmii_rx_er">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="C10"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_rmii_crs_dv">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="D9"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="E3"/>
+ </pins>
+ </port>
+
+ </ports>
+
+</board_part>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/mig.prj b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/mig.prj
new file mode 100644
index 000000000..0bba8d649
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/artix7/nexys4_ddr/1.1/mig.prj
@@ -0,0 +1,127 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>design_1_mig_7series_0_2</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
+ <Version>2.2</Version>
+ <SystemClock>No Buffer</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>1</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>
+ <TimePeriod>3077</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>199.995</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>16</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>13</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <C0_MEM_SIZE>134217728</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" name="ddr2_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" name="ddr2_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" name="ddr2_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" name="ddr2_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" name="ddr2_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" name="ddr2_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" name="ddr2_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" name="ddr2_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" name="ddr2_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" name="ddr2_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" name="ddr2_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" name="ddr2_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" name="ddr2_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" name="ddr2_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" name="ddr2_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" name="ddr2_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" name="ddr2_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" name="ddr2_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" name="ddr2_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" name="ddr2_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" name="ddr2_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" name="ddr2_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" name="ddr2_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" name="ddr2_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" name="ddr2_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" name="ddr2_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" name="ddr2_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" name="ddr2_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" name="ddr2_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" name="ddr2_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" name="ddr2_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" name="ddr2_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" name="ddr2_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" name="ddr2_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" name="ddr2_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" name="ddr2_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" name="ddr2_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" name="ddr2_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" name="ddr2_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" name="ddr2_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" name="ddr2_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" name="ddr2_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" name="ddr2_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" name="ddr2_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" name="ddr2_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" name="ddr2_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="10" trefi="7.8" tfaw="45" trtp="7.5" trfc="127.5" trp="12.5" tras="40" trcd="15" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8</mrBurstLength>
+ <mrBurstType name="Burst Type" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="PD Mode" >Fast exit</mrPdMode>
+ <mrWriteRecovery name="Write Recovery" >5</mrWriteRecovery>
+ <emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable>
+ <emrOutputDriveStrength name="Output Drive Strength" >Fullstrength</emrOutputDriveStrength>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrCKSelection name="Memory Clock Selection" >1</emrCKSelection>
+ <emrRTT name="RTT (nominal) - ODT" >50ohms</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="OCD Operation" >OCD Exit</emrOCD>
+ <emrDQS name="DQS# Enable" >Enable</emrDQS>
+ <emrRDQS name="RDQS Enable" >Disable</emrRDQS>
+ <emrOutputs name="Outputs" >Enable</emrOutputs>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml b/quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml
new file mode 100644
index 000000000..79f38d2bd
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/board_part.xml
@@ -0,0 +1,766 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+
+<board_part board_name="Genesys2" board_revision="H" board_part="part0" schema_version="1.1" vendor="digilentinc.com" version="1.1">
+
+ <part_info part_name="xc7k325tffg900-2" device="xc7k325t" family="kintex7" jtag_position="1" package="ffg900" silicon_version="1.0" speed_grade="-2"/>
+
+ <board_info description="Genesys2" display_name="Genesys2" url="www.digilentinc.com/genesys2"/>
+
+
+ <interfaces>
+
+ <interface mode="master" name="DDR3_SDRAM" type="xilinx.com:interface:ddrx_rtl:1.0">
+ <preset_file name="mig.prj"/>
+ </interface>
+
+ <interface mode="master" name="DIP_Switches_8Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="DIP_Switches_8Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="LED_8Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="LED_8Bits_TRI_O"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Push_Buttons_5Bits" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="Push_Buttons_5Bits_TRI_I"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="USB_Uart" type="xilinx.com:interface:uart_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TxD" physical_port="USB_Uart_TxD"/>
+ <port_map logical_port="RxD" physical_port="USB_Uart_RxD"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="Qspi_flash" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="Qspi_DB0_i"/>
+ <port_map logical_port="IO0_O" physical_port="Qspi_DB0_o"/>
+ <port_map logical_port="IO0_T" physical_port="Qspi_DB0_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="Qspi_DB1_i"/>
+ <port_map logical_port="IO1_O" physical_port="Qspi_DB1_o"/>
+ <port_map logical_port="IO1_T" physical_port="Qspi_DB1_t"/>
+
+ <port_map logical_port="IO2_I" physical_port="Qspi_DB2_i"/>
+ <port_map logical_port="IO2_O" physical_port="Qspi_DB2_o"/>
+ <port_map logical_port="IO2_T" physical_port="Qspi_DB2_t"/>
+
+ <port_map logical_port="IO3_I" physical_port="Qspi_DB3_i"/>
+ <port_map logical_port="IO3_O" physical_port="Qspi_DB3_o"/>
+ <port_map logical_port="IO3_T" physical_port="Qspi_DB3_t"/>
+
+ <port_map logical_port="SS_I" physical_port="Qspi_CSn_i"/>
+ <port_map logical_port="SS_O" physical_port="Qspi_CSn_o"/>
+ <port_map logical_port="SS_T" physical_port="Qspi_CSn_t"/>
+
+ </port_maps>
+
+ </interface>
+
+
+ <interface mode="master" name="IIC_Bus" type="xilinx.com:interface:iic_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="SDA_i"/>
+ <port_map logical_port="SDA_O" physical_port="SDA_o"/>
+ <port_map logical_port="SDA_T" physical_port="SDA_t"/>
+ <port_map logical_port="SCL_I" physical_port="SCL_i"/>
+ <port_map logical_port="SCL_O" physical_port="SCL_o"/>
+ <port_map logical_port="SCL_T" physical_port="SCL_t"/>
+ </port_maps>
+ </interface>
+
+
+ <interface mode="master" name="Audio_Codec_IIC" type="xilinx.com:interface:iic_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="SDA_I" physical_port="AUD_SDA_i"/>
+ <port_map logical_port="SDA_O" physical_port="AUD_SDA_o"/>
+ <port_map logical_port="SDA_T" physical_port="AUD_SDA_t"/>
+ <port_map logical_port="SCL_I" physical_port="AUD_SCL_i"/>
+ <port_map logical_port="SCL_O" physical_port="AUD_SCL_o"/>
+ <port_map logical_port="SCL_T" physical_port="AUD_SCL_t"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="DSPI" type="xilinx.com:interface:spi_rtl:1.0">
+
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="MISO_i"/>
+ <port_map logical_port="IO0_O" physical_port="MISO_o"/>
+ <port_map logical_port="IO0_T" physical_port="MISO_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="MOSI_i"/>
+ <port_map logical_port="IO1_O" physical_port="MOSI_o"/>
+ <port_map logical_port="IO1_T" physical_port="MOSI_t"/>
+
+ <port_map logical_port="SCK_I" physical_port="SCLK_i"/>
+ <port_map logical_port="SCK_O" physical_port="SCLK_o"/>
+ <port_map logical_port="SCK_T" physical_port="SCLK_t"/>
+
+
+ <port_map logical_port="SS_I" physical_port="SS_i"/>
+ <port_map logical_port="SS_O" physical_port="SS_o"/>
+ <port_map logical_port="SS_T" physical_port="SS_t"/>
+
+ </port_maps>
+
+ </interface>
+
+ <interface mode="master" name="SD_SPI_MODE" type="xilinx.com:interface:spi_rtl:1.0">
+ <port_maps>
+
+ <port_map logical_port="IO0_I" physical_port="SD_MISO_i"/>
+ <port_map logical_port="IO0_O" physical_port="SD_MISO_o"/>
+ <port_map logical_port="IO0_T" physical_port="SD_MISO_t"/>
+
+ <port_map logical_port="IO1_I" physical_port="SD_MOSI_i"/>
+ <port_map logical_port="IO1_O" physical_port="SD_MOSI_o"/>
+ <port_map logical_port="IO1_T" physical_port="SD_MOSI_t"/>
+
+ <port_map logical_port="SCK_I" physical_port="SD_SCLK_i"/>
+ <port_map logical_port="SCK_O" physical_port="SD_SCLK_o"/>
+ <port_map logical_port="SCK_T" physical_port="SD_SCLK_t"/>
+
+
+ <port_map logical_port="SS_I" physical_port="SD_SS_i"/>
+ <port_map logical_port="SS_O" physical_port="SD_SS_o"/>
+ <port_map logical_port="SS_T" physical_port="SD_SS_t"/>
+
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ETH_mdio_io" type="xilinx.com:interface:mdio_io:1.0">
+ <port_maps>
+ <port_map logical_port="IO" physical_port="ETH_io"/>
+ <port_map logical_port="MDC" physical_port="ETH_mdc1"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ETH_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="MDIO_I" physical_port="ETH_mdio_i"/>
+ <port_map logical_port="MDIO_O" physical_port="ETH_mdio_o"/>
+ <port_map logical_port="MDIO_T" physical_port="ETH_mdio_t"/>
+ <port_map logical_port="MDC" physical_port="ETH_mdc"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="master" name="ETH_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TD" physical_port="ETH_rgmii_td"/>
+ <port_map logical_port="RD" physical_port="ETH_rgmii_rd"/>
+ <port_map logical_port="RX_CTL" physical_port="ETH_rgmii_rx_ctl"/>
+ <port_map logical_port="TX_CTL" physical_port="ETH_rgmii_tx_ctl"/>
+ <port_map logical_port="TXC" physical_port="ETH_rgmii_txc"/>
+ <port_map logical_port="RXC" physical_port="ETH_rgmii_rxc"/>
+ </port_maps>
+ </interface>
+
+ <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="RESET" physical_port="RESET"/>
+ </port_maps>
+ <parameters>
+ <parameter name="RST_POLARITY" value="0"/>
+ </parameters>
+ </interface>
+
+ <interface mode="master" name="Displayport_in_HPD_led" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="dp_rx_hpd"/>
+ </port_maps>
+
+ </interface>
+ <interface mode="master" name="Displayport_out_HPD_led" type="xilinx.com:interface:gpio_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="dp_tx_hpd"/>
+ </port_maps>
+
+ </interface>
+ <interface mode="master" name="Displayport_out" type="xilinx.com:interface:dp_aux_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="AUX_TX_CHANNEL_OUT_P" physical_port="dp_tx_out_p"/>
+ <port_map logical_port="AUX_TX_CHANNEL_OUT_N" physical_port="dp_tx_out_n"/>
+ <port_map logical_port="AUX_TX_CHANNEL_IN_P" physical_port="dp_tx_in_p"/>
+ <port_map logical_port="AUX_TX_CHANNEL_IN_N" physical_port="dp_tx_in_n"/>
+ </port_maps>
+
+ </interface>
+
+ <interface mode="slave" name="Displayport_in" type="xilinx.com:interface:dp_aux_rtl:1.0">
+
+ <port_maps>
+ <port_map logical_port="AUX_TX_CHANNEL_OUT_P" physical_port="dp_rx_out_p"/>
+ <port_map logical_port="AUX_TX_CHANNEL_OUT_N" physical_port="dp_rx_out_n"/>
+ <port_map logical_port="AUX_TX_CHANNEL_IN_P" physical_port="dp_rx_in_p"/>
+ <port_map logical_port="AUX_TX_CHANNEL_IN_N" physical_port="dp_rx_in_n"/>
+ </port_maps>
+
+ </interface>
+
+
+ <interface mode="master" name="USB_OTG_master" type="xilinx.com:interface:ulpi_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="otg_clk_m"/>
+ <port_map logical_port="RST" physical_port="otg_rst_m"/>
+ <port_map logical_port="DIR" physical_port="otg_dir_m"/>
+ <port_map logical_port="NEXT" physical_port="otg_next_m"/>
+ <port_map logical_port="STOP" physical_port="otg_stop_m"/>
+ <port_map logical_port="DATA_I" physical_port="otg_data_i"/>
+ <port_map logical_port="DATA_O" physical_port="otg_data_o"/>
+ <port_map logical_port="DATA_T" physical_port="otg_data_t"/>
+ </port_maps>
+ </interface>
+
+
+
+ </interfaces>
+
+
+ <ports>
+
+ <port name="DIP_Switches_8Bits_TRI_I" dir="in" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS12" loc="G19"/>
+ <pin index="1" iostandard="LVCMOS12" loc="G25"/>
+ <pin index="2" iostandard="LVCMOS12" loc="H24"/>
+ <pin index="3" iostandard="LVCMOS12" loc="K19"/>
+ <pin index="4" iostandard="LVCMOS12" loc="N19"/>
+ <pin index="5" iostandard="LVCMOS12" loc="P19"/>
+ <pin index="6" iostandard="LVCMOS33" loc="P26"/>
+ <pin index="7" iostandard="LVCMOS33" loc="P27"/>
+ </pins>
+ </port>
+
+ <port name="LED_8Bits_TRI_O" dir="out" left="7" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="T28"/>
+ <pin index="1" iostandard="LVCMOS33" loc="V19"/>
+ <pin index="2" iostandard="LVCMOS33" loc="U30"/>
+ <pin index="3" iostandard="LVCMOS33" loc="U29"/>
+ <pin index="4" iostandard="LVCMOS33" loc="V20"/>
+ <pin index="5" iostandard="LVCMOS33" loc="V26"/>
+ <pin index="6" iostandard="LVCMOS33" loc="W24"/>
+ <pin index="7" iostandard="LVCMOS33" loc="W23"/>
+ </pins>
+ </port>
+
+ <port name="Push_Buttons_5Bits_TRI_I" dir="in" left="4" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS12" loc="E18"/>
+ <pin index="1" iostandard="LVCMOS12" loc="B19"/>
+ <pin index="2" iostandard="LVCMOS12" loc="M20"/>
+ <pin index="3" iostandard="LVCMOS12" loc="C19"/>
+ <pin index="4" iostandard="LVCMOS12" loc="M19"/>
+ </pins>
+ </port>
+
+ <port name="RESET" dir="in" >
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R19"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="USB_Uart_RxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="Y20"/>
+ </pins>
+ </port>
+ <port dir="out" name="USB_Uart_TxD">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="Y23"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="Qspi_DB0_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="P24"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="P24"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB0_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="P24"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB1_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R25"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R25"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB1_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R25"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB2_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R20"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R20"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB2_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R20"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_DB3_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R21"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R21"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_DB3_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R21"/>
+ </pins>
+ </port>
+ <port dir="in" name="Qspi_CSn_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="U19"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="U19"/>
+ </pins>
+ </port>
+ <port dir="out" name="Qspi_CSn_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="U19"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="SDA_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AF30"/>
+ </pins>
+ </port>
+ <port dir="out" name="SDA_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AF30"/>
+ </pins>
+ </port>
+ <port dir="out" name="SDA_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AF30"/>
+ </pins>
+ </port>
+ <port dir="in" name="SCL_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AE30"/>
+ </pins>
+ </port>
+ <port dir="out" name="SCL_o">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AE30"/>
+ </pins>
+ </port>
+ <port dir="out" name="SCL_t">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AE30"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="AUD_SDA_i">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AF18"/>
+ </pins>
+ </port>
+ <port dir="out" name="AUD_SDA_o">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AF18"/>
+ </pins>
+ </port>
+ <port dir="out" name="AUD_SDA_t">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AF18"/>
+ </pins>
+ </port>
+ <port dir="in" name="AUD_SCL_i">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AE19"/>
+ </pins>
+ </port>
+ <port dir="out" name="AUD_SCL_o">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AE19"/>
+ </pins>
+ </port>
+ <port dir="out" name="AUD_SCL_t">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AE19"/>
+ </pins>
+ </port>
+
+
+ <port dir="in" name="MISO_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W28"/>
+ </pins>
+ </port>
+ <port dir="out" name="MISO_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W28"/>
+ </pins>
+ </port>
+ <port dir="out" name="MISO_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W28"/>
+ </pins>
+ </port>
+ <port dir="in" name="MOSI_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W27"/>
+ </pins>
+ </port>
+ <port dir="out" name="MOSI_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W27"/>
+ </pins>
+ </port>
+ <port dir="out" name="MOSI_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W27"/>
+ </pins>
+ </port>
+ <port dir="in" name="SCLK_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AD27"/>
+ </pins>
+ </port>
+ <port dir="out" name="SCLK_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AD27"/>
+ </pins>
+ </port>
+ <port dir="out" name="SCLK_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AD27"/>
+ </pins>
+ </port>
+ <port dir="in" name="SS_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W29"/>
+ </pins>
+ </port>
+ <port dir="out" name="SS_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W29"/>
+ </pins>
+ </port>
+ <port dir="out" name="SS_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="W29"/>
+ </pins>
+ </port>
+
+
+
+ <port dir="in" name="SD_MISO_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R26"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_MISO_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R26"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_MISO_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R26"/>
+ </pins>
+ </port>
+ <port dir="in" name="SD_MOSI_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R29"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_MOSI_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R29"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_MOSI_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R29"/>
+ </pins>
+ </port>
+ <port dir="in" name="SD_SCLK_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R28"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_SCLK_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R28"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_SCLK_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="R28"/>
+ </pins>
+ </port>
+ <port dir="in" name="SD_SS_i">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="T30"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_SS_o">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="T30"/>
+ </pins>
+ </port>
+ <port dir="out" name="SD_SS_t">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="T30"/>
+ </pins>
+ </port>
+
+ <port dir="inout" name="ETH_io">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AG12"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdc1">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AF12"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_mdc">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AF12"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_mdio_i">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AG12"/>
+ </pins>
+ </port>
+ <port dir="out" name="ETH_mdio_o">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AG12"/>
+ </pins>
+ </port>
+ <port dir="out" name="ETH_mdio_t">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AG12"/>
+ </pins>
+ </port>
+
+ <port dir="out" left="3" name="ETH_rgmii_td" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS15" loc="AJ12"/>
+ <pin index="1" iostandard="LVCMOS15" loc="AK11"/>
+ <pin index="2" iostandard="LVCMOS15" loc="AJ11"/>
+ <pin index="3" iostandard="LVCMOS15" loc="AK10"/>
+ </pins>
+ </port>
+
+ <port dir="in" left="3" name="ETH_rgmii_rd" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS15" loc="AJ14"/>
+ <pin index="1" iostandard="LVCMOS15" loc="AH14"/>
+ <pin index="2" iostandard="LVCMOS15" loc="AK13"/>
+ <pin index="3" iostandard="LVCMOS15" loc="AJ13"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_rgmii_rx_ctl">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AH11"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_rgmii_tx_ctl">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AK14"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="ETH_rgmii_txc">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AE10"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="ETH_rgmii_rxc">
+ <pins>
+ <pin iostandard="LVCMOS15" loc="AG10"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="clk_p">
+ <pins>
+ <pin iostandard="TMDS_33" loc="AD12"/>
+ </pins>
+ </port>
+ <port dir="in" name="clk_n">
+ <pins>
+ <pin iostandard="TMDS_33" loc="AD11"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="dp_tx_hpd">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AD21"/>
+ </pins>
+ </port>
+ <port dir="out" name="dp_tx_out_p">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AA18"/>
+ </pins>
+ </port>
+ <port dir="out" name="dp_tx_out_n">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AB18"/>
+ </pins>
+ </port>
+ <port dir="in" name="dp_tx_in_p">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AD17"/>
+ </pins>
+ </port>
+ <port dir="in" name="dp_tx_in_n">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AD16"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="dp_rx_hpd">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="AE21"/>
+ </pins>
+ </port>
+ <port dir="in" name="dp_rx_out_p">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="Y19"/>
+ </pins>
+ </port>
+ <port dir="in" name="dp_rx_out_n">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="Y18"/>
+ </pins>
+ </port>
+ <port dir="out" name="dp_rx_in_p">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AB19"/>
+ </pins>
+ </port>
+ <port dir="out" name="dp_rx_in_n">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AC19"/>
+ </pins>
+ </port>
+
+
+ <port dir="out" name="otg_clk_m">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AD18"/>
+ </pins>
+ </port>
+ <port dir="in" name="otg_rst_m">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AB14"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="otg_dir_m">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="Y16"/>
+ </pins>
+ </port>
+
+ <port dir="out" name="otg_next_m">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AA16"/>
+ </pins>
+ </port>
+
+ <port dir="in" name="otg_stop_m">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AA17"/>
+ </pins>
+ </port>
+
+ <port dir="in" left="7" name="otg_data_i" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS18" loc="AE14"/>
+ <pin index="1" iostandard="LVCMOS18" loc="AE15"/>
+ <pin index="2" iostandard="LVCMOS18" loc="AC15"/>
+ <pin index="3" iostandard="LVCMOS18" loc="AC16"/>
+ <pin index="4" iostandard="LVCMOS18" loc="AB15"/>
+ <pin index="5" iostandard="LVCMOS18" loc="AA15"/>
+ <pin index="6" iostandard="LVCMOS18" loc="AD14"/>
+ <pin index="7" iostandard="LVCMOS18" loc="AC14"/>
+ </pins>
+ </port>
+ <port dir="out" left="7" name="otg_data_o" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS18" loc="AE14"/>
+ <pin index="1" iostandard="LVCMOS18" loc="AE15"/>
+ <pin index="2" iostandard="LVCMOS18" loc="AC15"/>
+ <pin index="3" iostandard="LVCMOS18" loc="AC16"/>
+ <pin index="4" iostandard="LVCMOS18" loc="AB15"/>
+ <pin index="5" iostandard="LVCMOS18" loc="AA15"/>
+ <pin index="6" iostandard="LVCMOS18" loc="AD14"/>
+ <pin index="7" iostandard="LVCMOS18" loc="AC14"/>
+ </pins>
+ </port>
+ <port dir="out" name="otg_data_t">
+ <pins>
+ <pin iostandard="LVCMOS18" loc="AE14"/>
+ </pins>
+ </port>
+
+
+ </ports>
+
+</board_part>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/mig.prj b/quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/mig.prj
new file mode 100644
index 000000000..4aab5bcbb
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/kintex7/genesys2/H/mig.prj
@@ -0,0 +1,160 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>system_mig_7series_0_0</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Disabled</XADC_En>
+ <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
+ <Version>2.3</Version>
+ <SystemClock>Differential</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>0</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-107</MemoryDevice>
+ <TimePeriod>2500</TimePeriod>
+ <VccAuxIO>1.8V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>1</UIExtraClocks>
+ <MMCM_VCO>800</MMCM_VCO>
+ <MMCMClkOut0> 4.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>32</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>15</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Clock>
+ <Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />
+ </System_Clock>
+ <System_Control>
+ <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="5" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml b/quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml
new file mode 100644
index 000000000..1419a2db1
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/board_part.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<board_part board_name="zybo" board_revision="b" board_part="part0" schema_version="1.0" vendor="digilentinc.com" version="1.0">
+
+ <part_info part_name="xc7z010clg400-1" jtag_position="1" silicon_version="1.0" />
+
+ <board_info description="Zybo" display_name="Zybo" url="http://www.digilentinc.com"/>
+
+ <interfaces>
+ <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i"/>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o"/>
+ </port_maps>
+ </interface>
+ <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0">
+ <preset_file name="ps7.tcl"/>
+ </interface>
+ <interface mode="master" name="sws_4bits" type="xilinx.com:interface:gpio_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="TRI_I" physical_port="sws_4bits_tri_i"/>
+ </port_maps>
+ </interface>
+ <interface mode="slave" name="sys_clock" type="xilinx.com:interface:clock_rtl:1.0">
+ <port_maps>
+ <port_map logical_port="CLK" physical_port="sys_clk"/>
+ </port_maps>
+ <parameters>
+ <parameter name="frequency" value="125000000"/>
+ </parameters>
+ </interface>
+ </interfaces>
+
+ <ports>
+ <port dir="in" left="3" name="btns_4bits_tri_i" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="R18"/>
+ <pin index="1" iostandard="LVCMOS33" loc="P16"/>
+ <pin index="2" iostandard="LVCMOS33" loc="V16"/>
+ <pin index="3" iostandard="LVCMOS33" loc="Y16"/>
+ </pins>
+ </port>
+ <port dir="out" left="3" name="leds_4bits_tri_o" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="M14"/>
+ <pin index="1" iostandard="LVCMOS33" loc="M15"/>
+ <pin index="2" iostandard="LVCMOS33" loc="G14"/>
+ <pin index="3" iostandard="LVCMOS33" loc="D18"/>
+ </pins>
+ </port>
+ <port dir="in" left="3" name="sws_4bits_tri_i" right="0">
+ <pins>
+ <pin index="0" iostandard="LVCMOS33" loc="G15"/>
+ <pin index="1" iostandard="LVCMOS33" loc="P15"/>
+ <pin index="2" iostandard="LVCMOS33" loc="W13"/>
+ <pin index="3" iostandard="LVCMOS33" loc="T16"/>
+ </pins>
+ </port>
+ <port dir="in" name="sys_clk">
+ <pins>
+ <pin iostandard="LVCMOS33" loc="L16"/>
+ </pins>
+ </port>
+ </ports>
+
+</board_part>
diff --git a/quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl b/quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl
new file mode 100644
index 000000000..4527e7971
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/old/board_parts/zynq/zybo/1.0/ps7.tcl
@@ -0,0 +1,4 @@
+proc apply_ps7_board_setting { ps7_ip } {
+ set_property -dict [ list CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50.000000} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET0_RESET_ENABLE {0} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_MIO_0_PULLUP {enabled} CONFIG.PCW_MIO_10_PULLUP {enabled} CONFIG.PCW_MIO_11_PULLUP {enabled} CONFIG.PCW_MIO_12_PULLUP {enabled} CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_16_PULLUP {disabled} CONFIG.PCW_MIO_16_SLEW {fast} CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_17_PULLUP {disabled} CONFIG.PCW_MIO_17_SLEW {fast} CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_18_PULLUP {disabled} CONFIG.PCW_MIO_18_SLEW {fast} CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_19_PULLUP {disabled} CONFIG.PCW_MIO_19_SLEW {fast} CONFIG.PCW_MIO_1_PULLUP {disabled} CONFIG.PCW_MIO_1_SLEW {fast} CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_20_PULLUP {disabled} CONFIG.PCW_MIO_20_SLEW {fast} CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_21_PULLUP {disabled} CONFIG.PCW_MIO_21_SLEW {fast} CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_22_PULLUP {disabled} CONFIG.PCW_MIO_22_SLEW {fast} CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_23_PULLUP {disabled} CONFIG.PCW_MIO_23_SLEW {fast} CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_24_PULLUP {disabled} CONFIG.PCW_MIO_24_SLEW {fast} CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_25_PULLUP {disabled} CONFIG.PCW_MIO_25_SLEW {fast} CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_26_PULLUP {disabled} CONFIG.PCW_MIO_26_SLEW {fast} CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} CONFIG.PCW_MIO_27_PULLUP {disabled} CONFIG.PCW_MIO_27_SLEW {fast} CONFIG.PCW_MIO_28_PULLUP {disabled} CONFIG.PCW_MIO_28_SLEW {fast} CONFIG.PCW_MIO_29_PULLUP {disabled} CONFIG.PCW_MIO_29_SLEW {fast} CONFIG.PCW_MIO_2_SLEW {fast} CONFIG.PCW_MIO_30_PULLUP {disabled} CONFIG.PCW_MIO_30_SLEW {fast} CONFIG.PCW_MIO_31_PULLUP {disabled} CONFIG.PCW_MIO_31_SLEW {fast} CONFIG.PCW_MIO_32_PULLUP {disabled} CONFIG.PCW_MIO_32_SLEW {fast} CONFIG.PCW_MIO_33_PULLUP {disabled} CONFIG.PCW_MIO_33_SLEW {fast} CONFIG.PCW_MIO_34_PULLUP {disabled} CONFIG.PCW_MIO_34_SLEW {fast} CONFIG.PCW_MIO_35_PULLUP {disabled} CONFIG.PCW_MIO_35_SLEW {fast} CONFIG.PCW_MIO_36_PULLUP {disabled} CONFIG.PCW_MIO_36_SLEW {fast} CONFIG.PCW_MIO_37_PULLUP {disabled} CONFIG.PCW_MIO_37_SLEW {fast} CONFIG.PCW_MIO_38_PULLUP {disabled} CONFIG.PCW_MIO_38_SLEW {fast} CONFIG.PCW_MIO_39_PULLUP {disabled} CONFIG.PCW_MIO_39_SLEW {fast} CONFIG.PCW_MIO_3_SLEW {fast} CONFIG.PCW_MIO_40_PULLUP {disabled} CONFIG.PCW_MIO_40_SLEW {fast} CONFIG.PCW_MIO_41_PULLUP {disabled} CONFIG.PCW_MIO_41_SLEW {fast} CONFIG.PCW_MIO_42_PULLUP {disabled} CONFIG.PCW_MIO_42_SLEW {fast} CONFIG.PCW_MIO_43_PULLUP {disabled} CONFIG.PCW_MIO_43_SLEW {fast} CONFIG.PCW_MIO_44_PULLUP {disabled} CONFIG.PCW_MIO_44_SLEW {fast} CONFIG.PCW_MIO_45_PULLUP {disabled} CONFIG.PCW_MIO_45_SLEW {fast} CONFIG.PCW_MIO_47_PULLUP {disabled} CONFIG.PCW_MIO_48_PULLUP {disabled} CONFIG.PCW_MIO_49_PULLUP {disabled} CONFIG.PCW_MIO_4_SLEW {fast} CONFIG.PCW_MIO_50_DIRECTION {inout} CONFIG.PCW_MIO_50_PULLUP {disabled} CONFIG.PCW_MIO_51_DIRECTION {inout} CONFIG.PCW_MIO_51_PULLUP {disabled} CONFIG.PCW_MIO_52_PULLUP {disabled} CONFIG.PCW_MIO_52_SLEW {slow} CONFIG.PCW_MIO_53_PULLUP {disabled} CONFIG.PCW_MIO_53_SLEW {slow} CONFIG.PCW_MIO_5_SLEW {fast} CONFIG.PCW_MIO_6_SLEW {fast} CONFIG.PCW_MIO_8_SLEW {fast} CONFIG.PCW_MIO_9_PULLUP {enabled} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} CONFIG.PCW_SD0_GRP_WP_ENABLE {1} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.176} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.159} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.162} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.187} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.034} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.03} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.082} CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB0_RESET_ENABLE {1} CONFIG.PCW_USB0_RESET_IO {MIO 46} ] [get_bd_cells $ps7_ip]
+}
+
diff --git a/quad/vivado_workspace/vivado-boards-master/utility/Vivado_init.tcl b/quad/vivado_workspace/vivado-boards-master/utility/Vivado_init.tcl
new file mode 100644
index 000000000..50ca892f5
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/utility/Vivado_init.tcl
@@ -0,0 +1 @@
+set_param board.repoPaths [list "<extracted path>/vivado-boards/new/board_files"]
diff --git a/quad/vivado_workspace/vivado-boards-master/utility/init.tcl b/quad/vivado_workspace/vivado-boards-master/utility/init.tcl
new file mode 100644
index 000000000..50ca892f5
--- /dev/null
+++ b/quad/vivado_workspace/vivado-boards-master/utility/init.tcl
@@ -0,0 +1 @@
+set_param board.repoPaths [list "<extracted path>/vivado-boards/new/board_files"]
diff --git a/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc b/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc
new file mode 100644
index 000000000..9fb7c11b7
--- /dev/null
+++ b/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc
@@ -0,0 +1,198 @@
+## This file is a general .xdc for the Zybo Z7 Rev. B
+## It is compatible with the Zybo Z7-20 and Zybo Z7-10
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+##Clock signal
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
+
+
+##Buttons
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
+#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
+#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
+
+
+##LEDs
+#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
+#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
+#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
+#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
+
+
+##RGB LED 5 (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
+#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
+#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
+
+##RGB LED 6
+#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
+#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
+#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
+
+
+##Audio Codec
+#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
+#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
+#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
+#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
+#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
+#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
+#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
+#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
+#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
+
+
+##USB-OTG over-current detect pin
+#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
+
+
+##Fan (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
+
+
+##HDMI RX
+#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
+#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
+
+##HDMI RX CEC (Zybo Z7-20 only)
+#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
+
+
+##HDMI TX
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
+
+##HDMI TX CEC
+#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+
+
+##Pmod Header JB (Zybo Z7-20 only)
+set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb0 }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
+#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
+#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
+#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
+#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
+#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
+#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
+#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
+#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
+#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
+#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
+#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
+
+
+##Pcam MIPI CSI-2 Connector
+## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
+#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
+#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
+#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
+#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
+#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
+#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
+#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
+#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
+#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
+#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
+#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
+#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
+#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
+#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
+#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
+#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
+
+
+##Unloaded Crypto Chip SWI (for future use)
+#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
+
+
+##Unconnected Pins (Zybo Z7-20 only)
+#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
+#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
+#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
+#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
+#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
+#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
+#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
+#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
+#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
+#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
+#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
+#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
+
+
diff --git a/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd b/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
new file mode 100644
index 000000000..e61ab941a
--- /dev/null
+++ b/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
@@ -0,0 +1,256 @@
+--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2018.2.1 (lin64) Build 2288692 Thu Jul 26 18:23:50 MDT 2018
+--Date : Thu Sep 20 14:07:28 2018
+--Host : co3050-12.ece.iastate.edu running 64-bit Red Hat Enterprise Linux Workstation release 6.6 (Santiago)
+--Command : generate_target design_1_wrapper.bd
+--Design : design_1_wrapper
+--Purpose : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity design_1_wrapper is
+ port (
+ DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_cas_n : inout STD_LOGIC;
+ DDR_ck_n : inout STD_LOGIC;
+ DDR_ck_p : inout STD_LOGIC;
+ DDR_cke : inout STD_LOGIC;
+ DDR_cs_n : inout STD_LOGIC;
+ DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_odt : inout STD_LOGIC;
+ DDR_ras_n : inout STD_LOGIC;
+ DDR_reset_n : inout STD_LOGIC;
+ DDR_we_n : inout STD_LOGIC;
+ FIXED_IO_ddr_vrn : inout STD_LOGIC;
+ FIXED_IO_ddr_vrp : inout STD_LOGIC;
+ FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ FIXED_IO_ps_clk : inout STD_LOGIC;
+ FIXED_IO_ps_porb : inout STD_LOGIC;
+ FIXED_IO_ps_srstb : inout STD_LOGIC;
+ btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ jb0 : in STD_LOGIC;
+ leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ rgb_led_tri_io : inout STD_LOGIC_VECTOR ( 5 downto 0 );
+ sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
+ );
+end design_1_wrapper;
+
+architecture STRUCTURE of design_1_wrapper is
+ component design_1 is
+ port (
+ DDR_cas_n : inout STD_LOGIC;
+ DDR_cke : inout STD_LOGIC;
+ DDR_ck_n : inout STD_LOGIC;
+ DDR_ck_p : inout STD_LOGIC;
+ DDR_cs_n : inout STD_LOGIC;
+ DDR_reset_n : inout STD_LOGIC;
+ DDR_odt : inout STD_LOGIC;
+ DDR_ras_n : inout STD_LOGIC;
+ DDR_we_n : inout STD_LOGIC;
+ DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
+ DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
+ DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
+ DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
+ FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
+ FIXED_IO_ddr_vrn : inout STD_LOGIC;
+ FIXED_IO_ddr_vrp : inout STD_LOGIC;
+ FIXED_IO_ps_srstb : inout STD_LOGIC;
+ FIXED_IO_ps_clk : inout STD_LOGIC;
+ FIXED_IO_ps_porb : inout STD_LOGIC;
+ sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ rgb_led_tri_i : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ rgb_led_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ rgb_led_tri_t : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ jb0 : in STD_LOGIC
+ );
+ end component design_1;
+ component IOBUF is
+ port (
+ I : in STD_LOGIC;
+ O : out STD_LOGIC;
+ T : in STD_LOGIC;
+ IO : inout STD_LOGIC
+ );
+ end component IOBUF;
+ signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal rgb_led_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal rgb_led_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal rgb_led_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal rgb_led_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal rgb_led_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal rgb_led_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal rgb_led_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal rgb_led_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
+begin
+design_1_i: component design_1
+ port map (
+ DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
+ DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
+ DDR_cas_n => DDR_cas_n,
+ DDR_ck_n => DDR_ck_n,
+ DDR_ck_p => DDR_ck_p,
+ DDR_cke => DDR_cke,
+ DDR_cs_n => DDR_cs_n,
+ DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
+ DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
+ DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
+ DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
+ DDR_odt => DDR_odt,
+ DDR_ras_n => DDR_ras_n,
+ DDR_reset_n => DDR_reset_n,
+ DDR_we_n => DDR_we_n,
+ FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+ FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+ FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
+ FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+ FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+ FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+ btns_4bits_tri_i(3 downto 0) => btns_4bits_tri_i(3 downto 0),
+ jb0 => jb0,
+ leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),
+ leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),
+ leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),
+ leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),
+ leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),
+ leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),
+ leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),
+ leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),
+ leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),
+ leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),
+ leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),
+ leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0),
+ rgb_led_tri_i(5) => rgb_led_tri_i_5(5),
+ rgb_led_tri_i(4) => rgb_led_tri_i_4(4),
+ rgb_led_tri_i(3) => rgb_led_tri_i_3(3),
+ rgb_led_tri_i(2) => rgb_led_tri_i_2(2),
+ rgb_led_tri_i(1) => rgb_led_tri_i_1(1),
+ rgb_led_tri_i(0) => rgb_led_tri_i_0(0),
+ rgb_led_tri_o(5) => rgb_led_tri_o_5(5),
+ rgb_led_tri_o(4) => rgb_led_tri_o_4(4),
+ rgb_led_tri_o(3) => rgb_led_tri_o_3(3),
+ rgb_led_tri_o(2) => rgb_led_tri_o_2(2),
+ rgb_led_tri_o(1) => rgb_led_tri_o_1(1),
+ rgb_led_tri_o(0) => rgb_led_tri_o_0(0),
+ rgb_led_tri_t(5) => rgb_led_tri_t_5(5),
+ rgb_led_tri_t(4) => rgb_led_tri_t_4(4),
+ rgb_led_tri_t(3) => rgb_led_tri_t_3(3),
+ rgb_led_tri_t(2) => rgb_led_tri_t_2(2),
+ rgb_led_tri_t(1) => rgb_led_tri_t_1(1),
+ rgb_led_tri_t(0) => rgb_led_tri_t_0(0),
+ sws_4bits_tri_i(3 downto 0) => sws_4bits_tri_i(3 downto 0)
+ );
+leds_4bits_tri_iobuf_0: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_0(0),
+ IO => leds_4bits_tri_io(0),
+ O => leds_4bits_tri_i_0(0),
+ T => leds_4bits_tri_t_0(0)
+ );
+leds_4bits_tri_iobuf_1: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_1(1),
+ IO => leds_4bits_tri_io(1),
+ O => leds_4bits_tri_i_1(1),
+ T => leds_4bits_tri_t_1(1)
+ );
+leds_4bits_tri_iobuf_2: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_2(2),
+ IO => leds_4bits_tri_io(2),
+ O => leds_4bits_tri_i_2(2),
+ T => leds_4bits_tri_t_2(2)
+ );
+leds_4bits_tri_iobuf_3: component IOBUF
+ port map (
+ I => leds_4bits_tri_o_3(3),
+ IO => leds_4bits_tri_io(3),
+ O => leds_4bits_tri_i_3(3),
+ T => leds_4bits_tri_t_3(3)
+ );
+rgb_led_tri_iobuf_0: component IOBUF
+ port map (
+ I => rgb_led_tri_o_0(0),
+ IO => rgb_led_tri_io(0),
+ O => rgb_led_tri_i_0(0),
+ T => rgb_led_tri_t_0(0)
+ );
+rgb_led_tri_iobuf_1: component IOBUF
+ port map (
+ I => rgb_led_tri_o_1(1),
+ IO => rgb_led_tri_io(1),
+ O => rgb_led_tri_i_1(1),
+ T => rgb_led_tri_t_1(1)
+ );
+rgb_led_tri_iobuf_2: component IOBUF
+ port map (
+ I => rgb_led_tri_o_2(2),
+ IO => rgb_led_tri_io(2),
+ O => rgb_led_tri_i_2(2),
+ T => rgb_led_tri_t_2(2)
+ );
+rgb_led_tri_iobuf_3: component IOBUF
+ port map (
+ I => rgb_led_tri_o_3(3),
+ IO => rgb_led_tri_io(3),
+ O => rgb_led_tri_i_3(3),
+ T => rgb_led_tri_t_3(3)
+ );
+rgb_led_tri_iobuf_4: component IOBUF
+ port map (
+ I => rgb_led_tri_o_4(4),
+ IO => rgb_led_tri_io(4),
+ O => rgb_led_tri_i_4(4),
+ T => rgb_led_tri_t_4(4)
+ );
+rgb_led_tri_iobuf_5: component IOBUF
+ port map (
+ I => rgb_led_tri_o_5(5),
+ IO => rgb_led_tri_io(5),
+ O => rgb_led_tri_i_5(5),
+ T => rgb_led_tri_t_5(5)
+ );
+end STRUCTURE;
--
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