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ZYBO_zynq_def.html 3.10 KiB 
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<title>Zynq PS configuration detail</title>
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<dl><dt><b><font size="5">Description</font></b></dt><dd>Zynq board definition file for the ZYBO Rev. B. This file can be imported into XPS or Vivado IP Integrator to configure the PS7 core to work properly with the ZYBO's DDR3, microSD, UART, Ethernet, USB-OTG, and other onboard peripherals.</dd></dl>
<h2>Preset Info</h2>
<ul><table><tr><td>Device Size</td><td>xc7z010</td></tr>
<tr><td>Package</td><td>clg400</td></tr>
<tr><td>Speed Grade</td><td>-2</td></tr>
</table></ul>
<h2>Zynq PS configuration</h2>
<ul><table border="1" summary="Configuration Summary" >
<thead><tr>         <th>Peripheral</th>            <th>Status</th>         <th>Signal Group</th>         <th>MIO</th>          <th>Freq</th>          </tr></thead>
<tr><td>CAN0</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>CAN1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>ENET0</td><td>Enabled</td><td>default</td><td>MIO 16 .. 27</td><td>1000 MBPS</td></tr>
<tr><td></td><td></td><td>GRP_MDIO</td><td>MIO 52 .. 53</td><td></td></tr>
<tr><td>ENET1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>GPIO</td><td>Enabled</td><td>default</td><td>MIO</td><td></td></tr>
<tr><td>I2C0</td><td>Enabled</td><td>default</td><td>EMIO</td><td></td></tr>
<tr><td></td><td></td><td>GRP_INT</td><td>EMIO</td><td></td></tr>
<tr><td>I2C1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>MODE</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>NAND</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>NOR</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>PJTAG</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>QSPI</td><td>Enabled</td><td>default</td><td>MIO 1 .. 6</td><td>200.000000</td></tr>
<tr><td></td><td></td><td>GRP_FBCLK</td><td>MIO 8</td><td></td></tr>
<tr><td>SD0</td><td>Enabled</td><td>default</td><td>MIO 40 .. 45</td><td></td></tr>
<tr><td></td><td></td><td>GRP_CD</td><td>MIO 47</td><td></td></tr>
<tr><td></td><td></td><td>GRP_WP</td><td>EMIO</td><td></td></tr>
<tr><td>SD1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>SPI0</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>SPI1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>TRACE</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>TTC0</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>TTC1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>UART0</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>UART1</td><td>Enabled</td><td>default</td><td>MIO 48 .. 49</td><td>50</td></tr>
<tr><td>USB0</td><td>Enabled</td><td>default</td><td>MIO 28 .. 39</td><td></td></tr>
<tr><td>USB1</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>VCFG</td><td>Disabled</td><td></td><td></td><td></td></tr>
<tr><td>WDT</td><td>Disabled</td><td></td><td></td><td></td></tr>
</table></ul></body></html>