registerFile.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RegisterFile is
    Port (
        i_CLK      : in  std_logic;
        i_RST      : in  std_logic;
        i_WE       : in  std_logic;
        i_RD_ADDR1 : in  std_logic_vector(4 downto 0);
        i_RD_ADDR2 : in  std_logic_vector(4 downto 0);
        i_WR_ADDR  : in  std_logic_vector(4 downto 0);
        i_WR_DATA  : in  std_logic_vector(31 downto 0);
        o_RD_DATA1 : out std_logic_vector(31 downto 0);
        o_RD_DATA2 : out std_logic_vector(31 downto 0)
    );
end RegisterFile;

architecture Structural of RegisterFile is
    signal s_WR_DATA : std_logic_vector(31 downto 0);
    signal s_RD_DATA1 : std_logic_vector(31 downto 0);
    signal s_RD_DATA2 : std_logic_vector(31 downto 0);

    component reg is
        Port (
            CLK   : in std_logic;
            RESET : in std_logic;
            D     : in std_logic_vector(31 downto 0);
            Q     : out std_logic_vector(31 downto 0)
        );
    end component;

begin
    WR_REG1: reg
        port map (
            CLK   => i_CLK,
            RESET => i_RST,
            D     => i_WR_DATA,
            Q     => s_WR_DATA
        );

    RD_REG1: reg
        port map (
            CLK   => i_CLK,
            RESET => i_RST,
            D     => (others => '0'),
            Q     => s_RD_DATA1
        );

    RD_REG2: reg
        port map (
            CLK   => i_CLK,
            RESET => i_RST,
            D     => (others => '0'),
            Q     => s_RD_DATA2
        );

    o_RD_DATA1 <= s_RD_DATA1;
    o_RD_DATA2 <= s_RD_DATA2;
end Structural;