register_File

src/RegFile/registerFile.vhd

@@ -6,74 +6,54 @@ entity RegisterFile is
         i_CLK      : in  std_logic;
         i_RST      : in  std_logic;
         i_WE       : in  std_logic;
-        i_RD_ADDR1 : in  std_logic_vector(4 downto 0); -- Read address 1 (5 bits)
-        i_RD_ADDR2 : in  std_logic_vector(4 downto 0); -- Read address 2 (5 bits)
-        i_WR_ADDR  : in  std_logic_vector(4 downto 0); -- Write address (5 bits)
-        i_WR_DATA  : in  std_logic_vector(31 downto 0); -- Data to be written (32 bits)
-        o_RD_DATA1 : out std_logic_vector(31 downto 0); -- Read Data 1 (32 bits)
-        o_RD_DATA2 : out std_logic_vector(31 downto 0)  -- Read Data 2 (32 bits)
+        i_RD_ADDR1 : in  std_logic_vector(4 downto 0);
+        i_RD_ADDR2 : in  std_logic_vector(4 downto 0);
+        i_WR_ADDR  : in  std_logic_vector(4 downto 0);
+        i_WR_DATA  : in  std_logic_vector(31 downto 0);
+        o_RD_DATA1 : out std_logic_vector(31 downto 0);
+        o_RD_DATA2 : out std_logic_vector(31 downto 0)
     );
 end RegisterFile;
 
-architecture Dataflow of RegisterFile is
-    signal s_decoder_out : std_logic_vector(31 downto 0); -- Output of the decoder (32 bits)
-    signal s_decoder_match : std_logic; -- Decoder match signal
-    signal s_register_we : std_logic; -- Write enable signal for the selected register
-    signal s_register_q  : std_logic_vector(31 downto 0); -- Data output from the selected register
-
-begin
-    -- Decoder instantiation
-    Decoder: entity work.decoder_5x32
-        port map (
-            I => i_RD_ADDR1,
-            O => s_decoder_out
+architecture Structural of RegisterFile is
+    signal s_WR_DATA : std_logic_vector(31 downto 0);
+    signal s_RD_DATA1 : std_logic_vector(31 downto 0);
+    signal s_RD_DATA2 : std_logic_vector(31 downto 0);
+
+    component reg is
+        Port (
+            CLK   : in std_logic;
+            RESET : in std_logic;
+            D     : in std_logic_vector(31 downto 0);
+            Q     : out std_logic_vector(31 downto 0)
         );
+    end component;
 
-    -- Generate write enable signal for the selected register
-    s_decoder_match <= '1' when (s_decoder_out(4 downto 0) = i_WR_ADDR) else '0';
-    s_register_we <= i_WE when s_decoder_match = '1' else '0';
-
-    -- Register banks (32 registers)
-    Register0: entity work.NBitRegister
-        generic map (
-            N => 32
-        )
+begin
+    WR_REG1: reg
         port map (
-            i_CLK => i_CLK,
-            i_RST => i_RST,
-            i_WE  => s_register_we,
-            i_D   => i_WR_DATA,
-            o_Q   => s_register_q
+            CLK   => i_CLK,
+            RESET => i_RST,
+            D     => i_WR_DATA,
+            Q     => s_WR_DATA
         );
 
-    -- Assign the selected register's output to RD_DATA1
-    o_RD_DATA1 <= s_register_q;
-
-    -- Repeat the process for the second read address (i_RD_ADDR2) and output to RD_DATA2
-    Decoder2: entity work.decoder_5x32
+    RD_REG1: reg
         port map (
-            I => i_RD_ADDR2,
-            O => s_decoder_out
+            CLK   => i_CLK,
+            RESET => i_RST,
+            D     => (others => '0'),
+            Q     => s_RD_DATA1
         );
 
-    -- Generate write enable signal for the selected register
-    s_decoder_match <= '1' when (s_decoder_out(4 downto 0) = i_WR_ADDR) else '0';
-    s_register_we <= i_WE when s_decoder_match = '1' else '0';
-
-    -- Register banks (32 registers)
-    Register1: entity work.NBitRegister
-        generic map (
-            N => 32
-        )
+    RD_REG2: reg
         port map (
-            i_CLK => i_CLK,
-            i_RST => i_RST,
-            i_WE  => s_register_we,
-            i_D   => i_WR_DATA,
-            o_Q   => s_register_q
+            CLK   => i_CLK,
+            RESET => i_RST,
+            D     => (others => '0'),
+            Q     => s_RD_DATA2
         );
 
-    -- Assign the selected register's output to RD_DATA2
-    o_RD_DATA2 <= s_register_q;
-
-end Dataflow;
+    o_RD_DATA1 <= s_RD_DATA1;
+    o_RD_DATA2 <= s_RD_DATA2;
+end Structural;