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Commit bf713a00 authored by James Talbert's avatar James Talbert
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wip: Testbench for pwm_signal_out

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quad/ip_repo/Makefile
+ 3
− 1
View file @ bf713a00
build-tests:
(cd pwm_recorder_1.0/ && make build-tests)
(cd pwm_sigal_out_1.0/ && make build-tests)
run-tests:
(cd pwm_recorder_1.0/ && make run-tests)
\ No newline at end of file
(cd pwm_recorder_1.0/ && make run-tests)
(cd pwm_sigal_out_1.0/ && make run-tests)
\ No newline at end of file
quad/ip_repo/pwm_recorder_1.0/Makefile
+ 1
− 1
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......@@ -3,7 +3,7 @@ build-tests:
run-tests:
xelab --debug wave -prj kernel_test.prj -s run_kernel_test work.kernel_tester
xsim run_kernel_test -wdb pwm_record_kernel_test.wdb --t get_simulation_result.tcl
xsim run_kernel_test -wdb kernel_test.wdb --t ../get_simulation_result.tcl
echo 1 > result.exp
cat result.log
cmp result.log result.exp
......
quad/ip_repo/pwm_recorder_1.0/kernel_test.sh deleted 100755 → 0
+ 0
− 4
View file @ 6c20f7db
#!/bin/bash
xelab --debug wave -prj kernel_test.prj -s run_kernel_test work.kernel_tester
xsim run_kernel_test -wdb pwm_record_kernel_test.wdb --t get_simulation_result.tcl
quad/ip_repo/pwm_signal_out_1.0/Makefile 0 → 100644
+ 10
− 0
View file @ bf713a00
build-tests:
# The build products get removed if run in the build step.
run-tests:
xelab --debug wave -prj kernel_test.prj -s run_kernel_test work.kernel_tester
xsim run_kernel_test -wdb kernel_test.wdb --t ../get_simulation_result.tcl
echo 1 > result.exp
cat result.log
cmp result.log result.exp
rm result.exp
\ No newline at end of file
quad/ip_repo/pwm_signal_out_1.0/component.xml
+ 45
− 12
View file @ bf713a00
......@@ -247,7 +247,7 @@
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......@@ -366,6 +366,20 @@
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<spirit:view>
<spirit:name>xilinx_testbench</spirit:name>
<spirit:displayName>Test Bench</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
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......@@ -712,7 +726,7 @@
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......@@ -759,6 +777,12 @@
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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......@@ -808,6 +832,15 @@
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<spirit:description>Produces the pwm signal out base on a register value</spirit:description>
<spirit:parameters>
......@@ -876,19 +909,19 @@
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<xilinx:displayName>pwm_signal_out_v1.0</xilinx:displayName>
<xilinx:coreRevision>2</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2017-12-09T23:09:40Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2018-10-05T20:40:10Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:pwm_signal_out:1.0_ARCHIVE_LOCATION">/local/ucart/MicroCART/quad/ip_repo/pwm_signal_out_1.0</xilinx:tag>
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quad/ip_repo/pwm_signal_out_1.0/kernel_test.prj 0 → 100644
+ 2
− 0
View file @ bf713a00
vhdl work src/pwm_rec.vhd
vhdl work hdl/kernel_tester.vhd
quad/ip_repo/pwm_signal_out_1.0/src/kernel_tester.vhd 0 → 100644
+ 120
− 0
View file @ bf713a00
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/05/2018 02:27:32 PM
-- Design Name:
-- Module Name: kernel_tester - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kernel_tester is
-- Port ( );
end kernel_tester;
architecture Behavioral of kernel_tester is
component pwm IS
PORT(clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --reset
pwm_per : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Number of clock counts
pwm_puls : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Number of clock counts in puls
pwm_out : OUT STD_LOGIC := '0');
END component pwm;
signal passing : std_logic;
signal clk : std_logic;
signal period : std_logic_vector(31 downto 0);
signal pulse : std_logic_vector(31 downto 0);
signal reset_n : std_logic;
signal generated : std_logic;
signal done : std_logic;
constant CLK_HPER : time := 20 us;
begin
UUT: pwm
PORT map(clk => clk,
reset_n => reset_n,
pwm_per => period,
pwm_puls => pulse,
pwm_out => generated);
testbench: process
variable period_desired : integer;
variable pulse_desired : integer;
variable period_measured : time;
variable pulse_measured : time;
variable period_count : integer;
variable pulse_count : integer;
begin
passing <= '1';
reset_n <='0';
wait for 2*CLK_HPER;
reset_n <='1';
for period_iter in 0 to 10 loop
for duty in 1 to 9 loop
period_desired := 100*(2**period_iter);
pulse_desired := period_desired*duty/10;
period <= std_logic_vector(to_unsigned(period_desired-1, 32));
pulse <= std_logic_vector(to_unsigned(pulse_desired-1, 32));
wait until generated = '1';
wait until generated = '0';
wait until generated = '1';
period_measured := now;
pulse_measured := now;
wait until generated = '0';
pulse_measured := now-pulse_measured;
wait until generated = '1';
period_measured := now-period_measured;
period_count := (period_measured/CLK_HPER)/2;
pulse_count := (pulse_measured/CLK_HPER)/2;
if (period_count /= period_desired OR pulse_count /= pulse_desired) then
passing <= '0';
end if;
ASSERT period_count = period_desired REPORT "Period was incorrect, expected: "&integer'image(period_desired)&" actual: "&integer'image(period_count) SEVERITY ERROR;
ASSERT pulse_count = pulse_desired REPORT "Pulse was incorrect, expected: "&integer'image(pulse_desired)&" actual: "&integer'image(pulse_count) SEVERITY ERROR;
end loop;
end loop;
done <= '1';
wait;
end process testbench;
clock_gen: process
begin
if (done = '1') then
wait;
else
clk <= '0';
wait for CLK_HPER;
clk <= '1';
wait for CLK_HPER;
end if;
end process;
end Behavioral;
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