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Commit 63ea76f8 authored by bbartels's avatar bbartels Committed by dawehr
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wip: Start tracking FSBL makefiles

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quad/.gitignore
+ 0
− 2
View file @ 63ea76f8
zybo_fsbl_bsp/
zybo_fsbl/
test.log
inc/
obj/
......
quad/Makefile
+ 4
− 4
View file @ 63ea76f8
......@@ -5,11 +5,11 @@ WS = $(CURDIR)/xsdk_workspace
BOOT = $(OUTDIR)/BOOT.bin
.PHONY: all default zybo boot test clean deep-clean
.PHONY: all libs zybo boot test clean deep-clean
all: default zybo
all: libs zybo boot
default:
libs:
$(MAKE) -C src/test
$(MAKE) -C src/queue
$(MAKE) -C src/computation_graph
......@@ -25,7 +25,7 @@ test:
$(MAKE) -C src/computation_graph test
clean:
rm -rf $(INCDIR) $(LIBDIR)
rm -rf $(INCDIR) $(LIBDIR) $(OUTDIR)
deep-clean:
make clean
......
quad/scripts/build_zybo.sh
+ 2
− 0
View file @ 63ea76f8
......@@ -10,3 +10,5 @@ source settings64.sh
make -C $WS/system_bsp all
make -C $WS/modular_quad_pid/Release all
make -C $WS/zybo_fsbl_bsp all
make -C $WS/zybo_fsbl/Release all
quad/scripts/clean_xsdk_workspace.sh
+ 4
− 1
View file @ 63ea76f8
......@@ -7,4 +7,7 @@ WS=$QUADDIR/xsdk_workspace
make -C $WS/modular_quad_pid/Debug clean
make -C $WS/modular_quad_pid/Release clean
make -C $WS/system_bsp clean
\ No newline at end of file
make -C $WS/system_bsp clean
make -C $WS/zybo_fsbl/Debug clean
make -C $WS/zybo_fsbl/Release clean
make -C $WS/zybo_fsbl_bsp clean
quad/xsdk_workspace/.gitignore
+ 2
− 0
View file @ 63ea76f8
......@@ -3,4 +3,6 @@ test.log
.metadata/
system_bsp/ps7_cortexa9_0/
system_bsp/libgen.log
zybo_fsbl_bsp/ps7_cortexa9_0/
zybo_fsbl_bsp/libgen.log
TAGS
\ No newline at end of file
quad/xsdk_workspace/zybo_fsbl/.cproject 0 → 100644
+ 172
− 0
View file @ 63ea76f8
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quad/xsdk_workspace/zybo_fsbl/.gitignore 0 → 100644
+ 4
− 0
View file @ 63ea76f8
*.o
*.d
*.elf
*.size
quad/xsdk_workspace/zybo_fsbl/.project 0 → 100644
+ 26
− 0
View file @ 63ea76f8
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>zybo_fsbl</name>
<comment>zybo_fsbl_bsp - ps7_cortexa9_0</comment>
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quad/xsdk_workspace/zybo_fsbl/Debug/makefile 0 → 100644
+ 58
− 0
View file @ 63ea76f8
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include src/subdir.mk
-include subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
zybo_fsbl.elf.size \
# All Target
all: zybo_fsbl.elf secondary-outputs
# Tool invocations
zybo_fsbl.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: ARM gcc linker'
arm-xilinx-eabi-gcc -L"/local/ucart/MicroCART_17-18/quad/xsdk_workspace/zybo_fsbl/src" -Wl,-T -Wl,../src/lscript.ld -L../../zybo_fsbl_bsp/ps7_cortexa9_0/lib -o "zybo_fsbl.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
@echo ' '
zybo_fsbl.elf.size: zybo_fsbl.elf
@echo 'Invoking: ARM Print Size'
arm-xilinx-eabi-size zybo_fsbl.elf |tee "zybo_fsbl.elf.size"
@echo 'Finished building: $@'
@echo ' '
# Other Targets
clean:
-$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES)$(ELFSIZE)$(S_UPPER_DEPS) zybo_fsbl.elf
-@echo ' '
secondary-outputs: $(ELFSIZE)
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
quad/xsdk_workspace/zybo_fsbl/Debug/objects.mk 0 → 100644
+ 8
− 0
View file @ 63ea76f8
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS := -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
quad/xsdk_workspace/zybo_fsbl/Debug/sources.mk 0 → 100644
+ 20
− 0
View file @ 63ea76f8
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
O_SRCS :=
C_SRCS :=
LD_SRCS :=
S_UPPER_SRCS :=
S_SRCS :=
OBJ_SRCS :=
OBJS :=
C_DEPS :=
EXECUTABLES :=
ELFSIZE :=
S_UPPER_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
quad/xsdk_workspace/zybo_fsbl/Debug/src/subdir.mk 0 → 100644
+ 80
− 0
View file @ 63ea76f8
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../src/ddr_init.c \
../src/ff.c \
../src/fsbl_hooks.c \
../src/image_mover.c \
../src/main.c \
../src/md5.c \
../src/mmc.c \
../src/nand.c \
../src/nor.c \
../src/pcap.c \
../src/ps7_init.c \
../src/qspi.c \
../src/rsa.c \
../src/sd.c
LD_SRCS += \
../src/lscript.ld
S_UPPER_SRCS += \
../src/fsbl_handoff.S
OBJS += \
./src/ddr_init.o \
./src/ff.o \
./src/fsbl_handoff.o \
./src/fsbl_hooks.o \
./src/image_mover.o \
./src/main.o \
./src/md5.o \
./src/mmc.o \
./src/nand.o \
./src/nor.o \
./src/pcap.o \
./src/ps7_init.o \
./src/qspi.o \
./src/rsa.o \
./src/sd.o
C_DEPS += \
./src/ddr_init.d \
./src/ff.d \
./src/fsbl_hooks.d \
./src/image_mover.d \
./src/main.d \
./src/md5.d \
./src/mmc.d \
./src/nand.d \
./src/nor.d \
./src/pcap.d \
./src/ps7_init.d \
./src/qspi.d \
./src/rsa.d \
./src/sd.d
S_UPPER_DEPS += \
./src/fsbl_handoff.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.c
@echo 'Building file: $<'
@echo 'Invoking: ARM gcc compiler'
arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../zybo_fsbl_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
src/%.o: ../src/%.S
@echo 'Building file: $<'
@echo 'Invoking: ARM gcc compiler'
arm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../zybo_fsbl_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
quad/xsdk_workspace/zybo_fsbl/Release/makefile 0 → 100644
+ 58
− 0
View file @ 63ea76f8
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include src/subdir.mk
-include subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
zybo_fsbl.elf.size \
# All Target
all: zybo_fsbl.elf secondary-outputs
# Tool invocations
zybo_fsbl.elf: $(OBJS) ../src/lscript.ld $(USER_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: ARM gcc linker'
arm-xilinx-eabi-gcc -L"/local/ucart/MicroCART_17-18/quad/xsdk_workspace/zybo_fsbl/src" -Wl,-T -Wl,../src/lscript.ld -L../../zybo_fsbl_bsp/ps7_cortexa9_0/lib -o "zybo_fsbl.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
@echo ' '
zybo_fsbl.elf.size: zybo_fsbl.elf
@echo 'Invoking: ARM Print Size'
arm-xilinx-eabi-size zybo_fsbl.elf |tee "zybo_fsbl.elf.size"
@echo 'Finished building: $@'
@echo ' '
# Other Targets
clean:
-$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES)$(ELFSIZE)$(S_UPPER_DEPS) zybo_fsbl.elf
-@echo ' '
secondary-outputs: $(ELFSIZE)
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
quad/xsdk_workspace/zybo_fsbl/Release/objects.mk 0 → 100644
+ 8
− 0
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS := -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
quad/xsdk_workspace/zybo_fsbl/Release/sources.mk 0 → 100644
+ 20
− 0
View file @ 63ea76f8
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
O_SRCS :=
C_SRCS :=
LD_SRCS :=
S_UPPER_SRCS :=
S_SRCS :=
OBJ_SRCS :=
OBJS :=
C_DEPS :=
EXECUTABLES :=
ELFSIZE :=
S_UPPER_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
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+ 80
− 0
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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../src/ddr_init.c \
../src/ff.c \
../src/fsbl_hooks.c \
../src/image_mover.c \
../src/main.c \
../src/md5.c \
../src/mmc.c \
../src/nand.c \
../src/nor.c \
../src/pcap.c \
../src/ps7_init.c \
../src/qspi.c \
../src/rsa.c \
../src/sd.c
LD_SRCS += \
../src/lscript.ld
S_UPPER_SRCS += \
../src/fsbl_handoff.S
OBJS += \
./src/ddr_init.o \
./src/ff.o \
./src/fsbl_handoff.o \
./src/fsbl_hooks.o \
./src/image_mover.o \
./src/main.o \
./src/md5.o \
./src/mmc.o \
./src/nand.o \
./src/nor.o \
./src/pcap.o \
./src/ps7_init.o \
./src/qspi.o \
./src/rsa.o \
./src/sd.o
C_DEPS += \
./src/ddr_init.d \
./src/ff.d \
./src/fsbl_hooks.d \
./src/image_mover.d \
./src/main.d \
./src/md5.d \
./src/mmc.d \
./src/nand.d \
./src/nor.d \
./src/pcap.d \
./src/ps7_init.d \
./src/qspi.d \
./src/rsa.d \
./src/sd.d
S_UPPER_DEPS += \
./src/fsbl_handoff.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.c
@echo 'Building file: $<'
@echo 'Invoking: ARM gcc compiler'
arm-xilinx-eabi-gcc -Wall -O2 -c -fmessage-length=0 -I../../zybo_fsbl_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
src/%.o: ../src/%.S
@echo 'Building file: $<'
@echo 'Invoking: ARM gcc compiler'
arm-xilinx-eabi-gcc -Wall -O2 -c -fmessage-length=0 -I../../zybo_fsbl_bsp/ps7_cortexa9_0/include -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
quad/xsdk_workspace/zybo_fsbl/src/ddr_init.c 0 → 100644
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− 0
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/******************************************************************************
*
* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file ddr_init.c
*
* Initialize the DDR controller. When PCW is functioning, this would be gone.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 06/19/09 First release
* 2.00a jz 05/11/11 Changed register to #defines, updated to peep11
* 3.00a mb 30/05/12 included fsbl.h
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "fsbl.h"
/************************** Constant Definitions *****************************/
#define DDR_CONFIG_BASE (XPS_DDR_CTRL_BASEADDR + 0x000)
#define DDR_MSTR_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x000)
#define DDR_TWORANKPHY_REG (XPS_DDR_CTRL_BASEADDR + 0x004)
#define DDR_HPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x008)
#define DDR_LPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x00C)
#define DDR_W_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x010)
#define DDR_DRAM_PARAMS_1_REG (XPS_DDR_CTRL_BASEADDR + 0x014)
#define DDR_DRAM_PARAMS_2_REG (XPS_DDR_CTRL_BASEADDR + 0x018)
#define DDR_DRAM_PARAMS_3_REG (XPS_DDR_CTRL_BASEADDR + 0x01C)
#define DDR_DRAM_PARAMS_4_REG (XPS_DDR_CTRL_BASEADDR + 0x020)
#define DDR_DRAM_PARAMS_5_REG (XPS_DDR_CTRL_BASEADDR + 0x024)
#define DDR_DRAM_INIT_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x028)
#define DDR_DRAM_MODE_1_REG (XPS_DDR_CTRL_BASEADDR + 0x02C)
#define DDR_DRAM_MODE_2_REG (XPS_DDR_CTRL_BASEADDR + 0x030)
#define DDR_DRAM_BURST8_REG (XPS_DDR_CTRL_BASEADDR + 0x034)
#define DDR_DEBUG_REG (XPS_DDR_CTRL_BASEADDR + 0x038)
#define DDR_ADDR_MAP_1_REG (XPS_DDR_CTRL_BASEADDR + 0x03C)
#define DDR_ADDR_MAP_2_REG (XPS_DDR_CTRL_BASEADDR + 0x040)
#define DDR_ADDR_MAP_3_REG (XPS_DDR_CTRL_BASEADDR + 0x044)
#define DDR_ODT_RD_WR_REG (XPS_DDR_CTRL_BASEADDR + 0x048)
#define DDR_PHY_RDC_FIFO_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x04C)
#define DDR_REG_PHY_RDC_FIFO_CTRL (XPS_DDR_CTRL_BASEADDR + 0x050)
#define DDR_STATUS_REG (XPS_DDR_CTRL_BASEADDR + 0x054)
#define DDR_DLL_CALIB_REG (XPS_DDR_CTRL_BASEADDR + 0x058)
#define DDR_ODT_REG (XPS_DDR_CTRL_BASEADDR + 0x05C)
#define DDR_MISC_1_REG (XPS_DDR_CTRL_BASEADDR + 0x060)
#define DDR_MISC_2_REG (XPS_DDR_CTRL_BASEADDR + 0x064)
#define DDR_WR_DLL_FORCE (XPS_DDR_CTRL_BASEADDR + 0x068)
#define DDR_RD_DLL_FORCE0_REG (XPS_DDR_CTRL_BASEADDR + 0x06C)
#define DDR_RD_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x070)
#define DDR_WR_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x074)
#define DDR_RD_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x078)
#define DDR_MSTR_DLL_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x07C)
#define DDR_RD_SLAVE_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x080)
#define DDR_RD_SLAVE_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x084)
#define DDR_OF_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x088)
#define DDR_OF_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x08C)
#define DDR_OF_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x090)
#define DDR_OF_STATUS3_REG (XPS_DDR_CTRL_BASEADDR + 0x094)
#define DDR_MSTR_DLL_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x098)
#define DDR_Wr_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x09C)
#define DDR_REFRESH_TIMER01_REG (XPS_DDR_CTRL_BASEADDR + 0x0A0)
#define DDR_T_ZQ_REG (XPS_DDR_CTRL_BASEADDR + 0x0A4)
#define DDR_T_ZQ_SHORT_INTERVAL_REG (XPS_DDR_CTRL_BASEADDR + 0x0A8)
#define DDR_STATUS_DATA_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0AC)
#define DDR_STATUS_DATA_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B0)
#define DDR_STATUS_DQS_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0B4)
#define DDR_STATUS_DQS_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B8)
#define DDR_WR_DATA_SLV0_REG (XPS_DDR_CTRL_BASEADDR + 0x17c)
#define DDR_WR_DATA_SLV1_REG (XPS_DDR_CTRL_BASEADDR + 0x180)
#define DDR_WR_DATA_SLV2_REG (XPS_DDR_CTRL_BASEADDR + 0x184)
#define DDR_WR_DATA_SLV3_REG (XPS_DDR_CTRL_BASEADDR + 0x188)
#define DDR_ID_REG (XPS_DDR_CTRL_BASEADDR + 0x200)
#define DDR_DDR_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x204)
#define DDR_PRIO_WR_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x208)
#define DDR_PRIO_WR_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x20C)
#define DDR_PRIO_WR_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x210)
#define DDR_PRIO_WR_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x214)
#define DDR_PRIO_RD_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x218)
#define DDR_PRIO_RD_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x21C)
#define DDR_PRIO_RD_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x220)
#define DDR_PRIO_RD_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x224)
#define DDR_PERF_MON_1_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x228)
#define DDR_PERF_MON_1_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x22C)
#define DDR_PERF_MON_1_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x230)
#define DDR_PERF_MON_1_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x234)
#define DDR_PERF_MON_2_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x238)
#define DDR_PERF_MON_2_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x23C)
#define DDR_PERF_MON_2_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x240)
#define DDR_PERF_MON_2_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x244)
#define DDR_PERF_MON_3_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x248)
#define DDR_PERF_MON_3_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x24C)
#define DDR_PERF_MON_3_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x250)
#define DDR_PERF_MON_3_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x254)
#define DDR_TRUSTED_MEM_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x258)
#define DDR_EXCLACC_CFG_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x25C)
#define DDR_EXCLACC_CFG_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x260)
#define DDR_EXCLACC_CFG_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x264)
#define DDR_EXCLACC_CFG_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x268)
/* Trust zone configuration register */
#define SLCR_LOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x4)
#define SLCR_UNLOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x8)
#define TZ_DDR_RAM_REG (XPS_SYS_CTRL_BASEADDR + 0x430)
/* Mask defines */
#define DDR_OUT_RESET_MASK 0x1
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define DDRIn32 Xil_In32
#define DDROut32 Xil_Out32
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void init_ddr(void);
#define DDRIn32 Xil_In32
#define DDROut32 Xil_Out32
static int verify = 0;
static void NewDDROut32(u32 Address, u32 Value)
{
u32 Data;
if (verify) {
Data = DDRIn32(Address);
if (Data != Value) fsbl_printf(DEBUG_INFO,"Verify failed, Address = %08X, \
Data = %08X, Expected = %08X\n\r", Address, Data, Value);
} else
DDROut32(Address, Value);
}
#undef DDROut32
#define DDROut32 NewDDROut32
void init_ddr(void)
{
u32 RegValue;
RegValue = DDRIn32(DDR_MSTR_CTRL_REG);
/* If DDR is being taking out of reset, then it has been configured
*/
if (RegValue & DDR_OUT_RESET_MASK)
verify = 1;
/* Configure DDR */
DDROut32(DDR_MSTR_CTRL_REG, 0x00000200);
/* direct rip of the DDR init tcl for the PEEP startup */
DDROut32(DDR_TWORANKPHY_REG, 0x000C1061); /* # 0 */
DDROut32(DDR_LPR_PARAMS_REG, 0x03001001); //;#3
DDROut32(DDR_W_PARAMS_REG, 0x00014001); //;#4
DDROut32(DDR_DRAM_PARAMS_1_REG, 0x0004e020); //; #5
#ifdef PEEP_CODE
DDROut32(DDR_DRAM_PARAMS_2_REG, 0x36264ccf); //; #6
#else
DDROut32(DDR_DRAM_PARAMS_2_REG, 0x349B48CD); //; #6
#endif
DDROut32(DDR_DRAM_PARAMS_3_REG, 0x820158a4); //; #7
DDROut32(DDR_DRAM_PARAMS_4_REG, 0x250882c4); //; #8
DDROut32(DDR_DRAM_INIT_PARAMS_REG, 0x00809004); //; #10
DDROut32(DDR_DRAM_MODE_1_REG, 0x0); //; #11
DDROut32(DDR_DRAM_MODE_2_REG, 0x00040952); //; #12
DDROut32(DDR_DRAM_BURST8_REG, 0x00020022); //; #13
#ifdef PEEP_CODE
DDROut32(DDR_ADDR_MAP_1_REG, 0xF88); //; #15
#endif
#ifdef PALLADIUM
DDROut32(DDR_ADDR_MAP_1_REG, 0x777); //; #15
#endif
DDROut32(DDR_ADDR_MAP_2_REG, 0xFF000000); //; #16
DDROut32(DDR_ADDR_MAP_3_REG, 0x0FF66666); //; #17
DDROut32(DDR_REG_PHY_RDC_FIFO_CTRL, 0x256); //; #20
DDROut32(DDR_ODT_REG, 0x2223); //; #23
DDROut32(DDR_MISC_2_REG, 0x00020FE0); //; #25
DDROut32(DDR_T_ZQ_REG, 0x10200800); //; #41
DDROut32(DDR_STATUS_DQS_SL_DLL_23_REG, 0x200065); //; #46
DDROut32(DDR_WR_DATA_SLV0_REG, 0x50); //; #95
DDROut32(DDR_WR_DATA_SLV1_REG, 0x50); //; #96
DDROut32(DDR_WR_DATA_SLV2_REG, 0x50); //; #97
DDROut32(DDR_WR_DATA_SLV3_REG, 0x50); //; #98
DDROut32(DDR_ID_REG, 0x0); //; #128
/* Enable ddr controller by taking the controller out of reset */
DDROut32(DDR_MSTR_CTRL_REG,
DDRIn32(DDR_MSTR_CTRL_REG) | DDR_OUT_RESET_MASK);
#ifdef PALLADIUM
/* Workaround for early palladium, to be removed for 4.61 */
DDROut32(SLCR_UNLOCK_REG, 0xDF0D);
DDROut32(TZ_DDR_RAM_REG, 0xffffffff);
DDROut32(SLCR_LOCK_REG, 0x767B);
#endif /* PALLADIUM*/
}
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/*-----------------------------------------------------------------------
/ Low level disk interface modlue include file (C)ChaN, 2009
/-----------------------------------------------------------------------*/
#ifndef _DISKIO
#define _DISKIO
#include "integer.h"
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*---------------------------------------*/
/* Prototypes for disk control functions */
int assign_drives (int, int);
DSTATUS disk_initialize (BYTE);
DSTATUS disk_status (BYTE);
DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
DRESULT disk_ioctl (BYTE, BYTE, void*);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (mandatory for FatFs) */
#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
#endif
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− 0
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