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Commit 3417ca0d authored by James Talbert's avatar James Talbert
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Update quad_hw preoject with IP blocks, constraints, and addresses

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quad/vivado_workspace/quad_hw.tcl
+ 87
− 23
View file @ 3417ca0d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
# #
# quad_hw.tcl: Tcl script for re-creating project 'quad_hw' # quad_hw.tcl: Tcl script for re-creating project 'quad_hw'
# #
# Generated by Vivado on Fri Oct 05 16:26:16 CDT 2018 # Generated by Vivado on Fri Oct 05 17:15:40 CDT 2018
# IP Build 2289599 on Thu Jul 26 21:09:20 MDT 2018 # IP Build 2289599 on Thu Jul 26 21:09:20 MDT 2018
# #
# This file contains the Vivado Tcl commands for re-creating the project to the state* # This file contains the Vivado Tcl commands for re-creating the project to the state*
...@@ -161,20 +161,6 @@ update_ip_catalog -rebuild ...@@ -161,20 +161,6 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object # Set 'sources_1' fileset object
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/quad_hw/quad_hw.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]\
]
set imported_files [import_files -fileset sources_1 $files]
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
set file "hdl/design_1_wrapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
# Set 'sources_1' fileset properties # Set 'sources_1' fileset properties
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
...@@ -190,11 +176,7 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} { ...@@ -190,11 +176,7 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
set obj [get_filesets constrs_1] set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties # Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/quad_hw/src/constrs/Zybo-Z7-Master.xdc"]" add_files -fileset constrs_1 -norecurse ${origin_dir}/${_xil_proj_name_}/src/constrs/Zybo-Z7-Master.xdc
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "constrs/Zybo-Z7-Master.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj
# Set 'constrs_1' fileset properties # Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1] set obj [get_filesets constrs_1]
...@@ -236,7 +218,10 @@ proc cr_bd_design_1 { parentCell } { ...@@ -236,7 +218,10 @@ proc cr_bd_design_1 { parentCell } {
if { $bCheckIPs == 1 } { if { $bCheckIPs == 1 } {
set list_check_ips "\ set list_check_ips "\
xilinx.com:ip:axi_gpio:2.0\ xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_timer:2.0\
xilinx.com:ip:processing_system7:5.5\ xilinx.com:ip:processing_system7:5.5\
user.org:user:pwm_recorder:1.0\
user.org:user:pwm_signal_out:1.0\
xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:proc_sys_reset:5.0\
" "
...@@ -298,6 +283,16 @@ proc cr_bd_design_1 { parentCell } { ...@@ -298,6 +283,16 @@ proc cr_bd_design_1 { parentCell } {
set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ] set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ]
# Create ports # Create ports
set pwm_in_0 [ create_bd_port -dir I pwm_in_0 ]
set pwm_in_1 [ create_bd_port -dir I pwm_in_1 ]
set pwm_in_2 [ create_bd_port -dir I pwm_in_2 ]
set pwm_in_3 [ create_bd_port -dir I pwm_in_3 ]
set pwm_in_4 [ create_bd_port -dir I pwm_in_4 ]
set pwm_in_5 [ create_bd_port -dir I pwm_in_5 ]
set pwm_out_0 [ create_bd_port -dir O pwm_out_0 ]
set pwm_out_1 [ create_bd_port -dir O pwm_out_1 ]
set pwm_out_2 [ create_bd_port -dir O pwm_out_2 ]
set pwm_out_3 [ create_bd_port -dir O pwm_out_3 ]
# Create instance: axi_gpio_0, and set properties # Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
...@@ -327,6 +322,9 @@ proc cr_bd_design_1 { parentCell } { ...@@ -327,6 +322,9 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.USE_BOARD_FLOW {true} \ CONFIG.USE_BOARD_FLOW {true} \
] $axi_gpio_3 ] $axi_gpio_3
# Create instance: axi_timer_0, and set properties
set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
# Create instance: processing_system7_0, and set properties # Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \ set_property -dict [ list \
...@@ -803,9 +801,39 @@ proc cr_bd_design_1 { parentCell } { ...@@ -803,9 +801,39 @@ proc cr_bd_design_1 { parentCell } {
# Create instance: ps7_0_axi_periph, and set properties # Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.NUM_MI {5} \ CONFIG.NUM_MI {15} \
] $ps7_0_axi_periph ] $ps7_0_axi_periph
# Create instance: pwm_recorder_0, and set properties
set pwm_recorder_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_0 ]
# Create instance: pwm_recorder_1, and set properties
set pwm_recorder_1 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_1 ]
# Create instance: pwm_recorder_2, and set properties
set pwm_recorder_2 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_2 ]
# Create instance: pwm_recorder_3, and set properties
set pwm_recorder_3 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_3 ]
# Create instance: pwm_recorder_4, and set properties
set pwm_recorder_4 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_4 ]
# Create instance: pwm_recorder_5, and set properties
set pwm_recorder_5 [ create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_5 ]
# Create instance: pwm_signal_out_0, and set properties
set pwm_signal_out_0 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_0 ]
# Create instance: pwm_signal_out_1, and set properties
set pwm_signal_out_1 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_1 ]
# Create instance: pwm_signal_out_2, and set properties
set pwm_signal_out_2 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_2 ]
# Create instance: pwm_signal_out_3, and set properties
set pwm_signal_out_3 [ create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_3 ]
# Create instance: rst_ps7_0_50M, and set properties # Create instance: rst_ps7_0_50M, and set properties
set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ] set rst_ps7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M ]
...@@ -821,18 +849,50 @@ proc cr_bd_design_1 { parentCell } { ...@@ -821,18 +849,50 @@ proc cr_bd_design_1 { parentCell } {
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI] connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_gpio_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M03_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins ps7_0_axi_periph/M04_AXI] [get_bd_intf_pins pwm_recorder_0/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M05_AXI [get_bd_intf_pins ps7_0_axi_periph/M05_AXI] [get_bd_intf_pins pwm_recorder_1/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M06_AXI [get_bd_intf_pins ps7_0_axi_periph/M06_AXI] [get_bd_intf_pins pwm_recorder_2/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M07_AXI [get_bd_intf_pins ps7_0_axi_periph/M07_AXI] [get_bd_intf_pins pwm_recorder_3/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M08_AXI [get_bd_intf_pins ps7_0_axi_periph/M08_AXI] [get_bd_intf_pins pwm_recorder_4/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M09_AXI [get_bd_intf_pins ps7_0_axi_periph/M09_AXI] [get_bd_intf_pins pwm_recorder_5/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M10_AXI [get_bd_intf_pins ps7_0_axi_periph/M10_AXI] [get_bd_intf_pins pwm_signal_out_0/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M11_AXI [get_bd_intf_pins ps7_0_axi_periph/M11_AXI] [get_bd_intf_pins pwm_signal_out_1/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M12_AXI [get_bd_intf_pins ps7_0_axi_periph/M12_AXI] [get_bd_intf_pins pwm_signal_out_2/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M13_AXI [get_bd_intf_pins ps7_0_axi_periph/M13_AXI] [get_bd_intf_pins pwm_signal_out_3/S_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M14_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M14_AXI]
# Create port connections # Create port connections
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk] connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
connect_bd_net -net pwm_in_master_0_1 [get_bd_ports pwm_in_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
connect_bd_net -net pwm_in_master_1_1 [get_bd_ports pwm_in_1] [get_bd_pins pwm_recorder_1/pwm_in_master]
connect_bd_net -net pwm_in_master_2_1 [get_bd_ports pwm_in_2] [get_bd_pins pwm_recorder_2/pwm_in_master]
connect_bd_net -net pwm_in_master_3_1 [get_bd_ports pwm_in_3] [get_bd_pins pwm_recorder_3/pwm_in_master]
connect_bd_net -net pwm_in_master_4_1 [get_bd_ports pwm_in_4] [get_bd_pins pwm_recorder_4/pwm_in_master]
connect_bd_net -net pwm_in_master_5_1 [get_bd_ports pwm_in_5] [get_bd_pins pwm_recorder_5/pwm_in_master]
connect_bd_net -net pwm_signal_out_0_pwm_out_sm [get_bd_ports pwm_out_3] [get_bd_pins pwm_signal_out_0/pwm_out_sm]
connect_bd_net -net pwm_signal_out_1_pwm_out_sm [get_bd_ports pwm_out_2] [get_bd_pins pwm_signal_out_1/pwm_out_sm]
connect_bd_net -net pwm_signal_out_2_pwm_out_sm [get_bd_ports pwm_out_1] [get_bd_pins pwm_signal_out_2/pwm_out_sm]
connect_bd_net -net pwm_signal_out_3_pwm_out_sm [get_bd_ports pwm_out_0] [get_bd_pins pwm_signal_out_3/pwm_out_sm]
connect_bd_net -net rst_ps7_0_50M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_50M/interconnect_aresetn] connect_bd_net -net rst_ps7_0_50M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_50M/interconnect_aresetn]
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn] connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/M05_ARESETN] [get_bd_pins ps7_0_axi_periph/M06_ARESETN] [get_bd_pins ps7_0_axi_periph/M07_ARESETN] [get_bd_pins ps7_0_axi_periph/M08_ARESETN] [get_bd_pins ps7_0_axi_periph/M09_ARESETN] [get_bd_pins ps7_0_axi_periph/M10_ARESETN] [get_bd_pins ps7_0_axi_periph/M11_ARESETN] [get_bd_pins ps7_0_axi_periph/M12_ARESETN] [get_bd_pins ps7_0_axi_periph/M13_ARESETN] [get_bd_pins ps7_0_axi_periph/M14_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pwm_recorder_0/s_axi_aresetn] [get_bd_pins pwm_recorder_1/s_axi_aresetn] [get_bd_pins pwm_recorder_2/s_axi_aresetn] [get_bd_pins pwm_recorder_3/s_axi_aresetn] [get_bd_pins pwm_recorder_4/s_axi_aresetn] [get_bd_pins pwm_recorder_5/s_axi_aresetn] [get_bd_pins pwm_signal_out_0/s_axi_aresetn] [get_bd_pins pwm_signal_out_1/s_axi_aresetn] [get_bd_pins pwm_signal_out_2/s_axi_aresetn] [get_bd_pins pwm_signal_out_3/s_axi_aresetn] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
# Create address segments # Create address segments
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_2/S_AXI/Reg] SEG_axi_gpio_2_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_2/S_AXI/Reg] SEG_axi_gpio_2_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_3/S_AXI/Reg] SEG_axi_gpio_3_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x42800000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x76EA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_0/S_AXI/S_AXI_reg] SEG_pwm_recorder_0_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x76E80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_1/S_AXI/S_AXI_reg] SEG_pwm_recorder_1_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x76E60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_2/S_AXI/S_AXI_reg] SEG_pwm_recorder_2_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x76E40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_3/S_AXI/S_AXI_reg] SEG_pwm_recorder_3_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x76E20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_4/S_AXI/S_AXI_reg] SEG_pwm_recorder_4_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x76E00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_recorder_5/S_AXI/S_AXI_reg] SEG_pwm_recorder_5_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x79460000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_0/S_AXI/S_AXI_reg] SEG_pwm_signal_out_0_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x79440000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_1/S_AXI/S_AXI_reg] SEG_pwm_signal_out_1_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x79420000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_2/S_AXI/S_AXI_reg] SEG_pwm_signal_out_2_S_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x79400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pwm_signal_out_3/S_AXI/S_AXI_reg] SEG_pwm_signal_out_3_S_AXI_reg
# Restore current instance # Restore current instance
...@@ -1076,3 +1136,7 @@ set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj ...@@ -1076,3 +1136,7 @@ set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
current_run -implementation [get_runs impl_1] current_run -implementation [get_runs impl_1]
puts "INFO: Project created:${_xil_proj_name_}" puts "INFO: Project created:${_xil_proj_name_}"
make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
quad/vivado_workspace/quad_hw/src/constrs/Zybo-Z7-Master.xdc
+ 10
− 10
View file @ 3417ca0d
...@@ -138,21 +138,21 @@ ...@@ -138,21 +138,21 @@
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1] #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2] #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2] #set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3] set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_4 }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3] set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_5 }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4] #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4] #set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
##Pmod Header JE ##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1] set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_0 }]; #IO_L4P_T0_34 Sch=je[1]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2] set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_1 }]; #IO_L18N_T2_34 Sch=je[2]
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3] set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_2 }]; #IO_25_35 Sch=je[3]
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4] set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_3 }]; #IO_L19P_T3_35 Sch=je[4]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_0 }]; #IO_L3N_T0_DQS_34 Sch=je[7]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8] set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_1 }]; #IO_L9N_T1_DQS_34 Sch=je[8]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9] set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_2 }]; #IO_L20P_T3_34 Sch=je[9]
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10] set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_3 }]; #IO_L7N_T1_34 Sch=je[10]
##Pcam MIPI CSI-2 Connector ##Pcam MIPI CSI-2 Connector
......
vivado.jou deleted 100644 → 0
+ 0
− 102
View file @ 8372751e
#-----------------------------------------------------------
# Vivado v2017.1 (64-bit)
# SW Build 1846317 on Fri Apr 14 18:54:47 MDT 2017
# IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
# Start of session at: Sat Dec 9 17:33:42 2017
# Process ID: 3460
# Current directory: /local/ucart/MicroCART
# Command line: vivado
# Log file: /local/ucart/MicroCART/vivado.log
# Journal file: /local/ucart/MicroCART/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /local/ucart/MicroCART/quad/vivado_workspace/vivado_workspace.xpr
update_compile_order -fileset sources_1
open_bd_design {/local/ucart/MicroCART/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bd}
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M10_AXI] [get_bd_nets pwm_signal_out_wkillswitch_3_pwm_out_master] [get_bd_cells pwm_signal_out_wkillswitch_3]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M11_AXI] [get_bd_nets pwm_signal_out_wkillswitch_0_pwm_out_master] [get_bd_cells pwm_signal_out_wkillswitch_0]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M04_AXI] [get_bd_nets pwm_recorder_2_1] [get_bd_cells pwm_recorder_2]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M02_AXI] [get_bd_nets pwm_recorder_0_1] [get_bd_cells pwm_recorder_0]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M09_AXI] [get_bd_nets pwm_signal_out_wkillswitch_2_pwm_out_master] [get_bd_cells pwm_signal_out_wkillswitch_2]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M08_AXI] [get_bd_nets pwm_signal_out_wkillswitch_1_pwm_out_master] [get_bd_cells pwm_signal_out_wkillswitch_1]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M05_AXI] [get_bd_nets pwm_recorder_3_1] [get_bd_cells pwm_recorder_3]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M06_AXI] [get_bd_nets pwm_recorder_4_1] [get_bd_cells pwm_recorder_4]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M07_AXI] [get_bd_nets pwm_recorder_5_1] [get_bd_cells pwm_recorder_5]
startgroup
create_bd_cell -type ip -vlnv user.org:user:pwm_signal_out:1.0 pwm_signal_out_0
endgroup
copy_bd_objs / [get_bd_cells {pwm_signal_out_0}]
copy_bd_objs / [get_bd_cells {pwm_signal_out_0}]
copy_bd_objs / [get_bd_cells {pwm_signal_out_0}]
delete_bd_objs [get_bd_intf_nets ps7_0_axi_periph_M03_AXI] [get_bd_nets pwm_recorder_1_1] [get_bd_cells pwm_recorder_1]
connect_bd_net [get_bd_ports pwm_out_sm_3] [get_bd_pins pwm_signal_out_3/pwm_out_sm]
connect_bd_net [get_bd_ports pwm_out_sm_2] [get_bd_pins pwm_signal_out_2/pwm_out_sm]
connect_bd_net [get_bd_ports pwm_out_sm_1] [get_bd_pins pwm_signal_out_1/pwm_out_sm]
connect_bd_net [get_bd_ports pwm_out_sm_0] [get_bd_pins pwm_signal_out_0/pwm_out_sm]
startgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_signal_out_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_signal_out_1/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_signal_out_2/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_signal_out_3/S_AXI]
endgroup
regenerate_bd_layout
create_peripheral user.org user pwm_recorder 1.0 -dir /local/ucart/MicroCART/quad/ip_repo
add_peripheral_interface S_AXI -interface_mode slave -axi_type lite [ipx::find_open_core user.org:user:pwm_recorder:1.0]
generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core user.org:user:pwm_recorder:1.0]
write_peripheral [ipx::find_open_core user.org:user:pwm_recorder:1.0]
set_property ip_repo_paths {/local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_signal_out_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_signal_out_wkillswitch_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0 /local/ucart/MicroCART/quad/ip_repo/myip_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0 /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0} [current_project]
update_ip_catalog -rebuild
ipx::edit_ip_in_project -upgrade true -name edit_pwm_recorder_v1_0 -directory /local/ucart/MicroCART/quad/ip_repo /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0/component.xml
update_compile_order -fileset sources_1
add_files -norecurse -copy_to /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0/src /local/ucart/MicroCART/quad/xps_projects/system/pcores/pwm_recorder_v1_04_a/hdl/vhdl/pwm_rec.vhd
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
ipx::merge_project_changes hdl_parameters [ipx::current_core]
set_property core_revision 2 [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path /local/ucart/MicroCART/quad/ip_repo/pwm_recorder_1.0
startgroup
create_bd_cell -type ip -vlnv user.org:user:pwm_recorder:1.0 pwm_recorder_0
endgroup
copy_bd_objs / [get_bd_cells {pwm_recorder_0}]
copy_bd_objs / [get_bd_cells {pwm_recorder_0}]
copy_bd_objs / [get_bd_cells {pwm_recorder_0}]
copy_bd_objs / [get_bd_cells {pwm_recorder_0}]
copy_bd_objs / [get_bd_cells {pwm_recorder_0}]
copy_bd_objs / [get_bd_cells {pwm_recorder_0}]
connect_bd_net [get_bd_ports pwm_recorder_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
connect_bd_net [get_bd_ports pwm_recorder_1] [get_bd_pins pwm_recorder_1/pwm_in_master]
connect_bd_net [get_bd_ports pwm_recorder_2] [get_bd_pins pwm_recorder_2/pwm_in_master]
set_property location {-20 86} [get_bd_ports pwm_recorder_3]
connect_bd_net [get_bd_ports pwm_recorder_3] [get_bd_pins pwm_recorder_3/pwm_in_master]
delete_bd_objs [get_bd_cells pwm_recorder_6]
connect_bd_net [get_bd_ports pwm_recorder_4] [get_bd_pins pwm_recorder_4/pwm_in_master]
connect_bd_net [get_bd_ports pwm_recorder_5] [get_bd_pins pwm_recorder_5/pwm_in_master]
startgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_recorder_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_recorder_1/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_recorder_2/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_recorder_3/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_recorder_4/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" intc_ip "/ps7_0_axi_periph" Clk_xbar "Auto" Clk_master "Auto" Clk_slave "Auto" } [get_bd_intf_pins pwm_recorder_5/S_AXI]
endgroup
set_property location {1 97 -383} [get_bd_cells pwm_recorder_4]
regenerate_bd_layout
save_bd_design
reset_run synth_1
reset_run quad_xbar_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
wait_on_run impl_1
open_run impl_1
file copy -force /local/ucart/MicroCART/quad/vivado_workspace/vivado_workspace.runs/impl_1/quad_wrapper.sysdef /local/ucart/MicroCART/quad/xsdk_workspace_vivado/quad_wrapper.hdf
launch_sdk -workspace /local/ucart/MicroCART/quad/xsdk_workspace_vivado -hwspec /local/ucart/MicroCART/quad/xsdk_workspace_vivado/quad_wrapper.hdf
open_bd_design {/local/ucart/MicroCART/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bd}
file copy -force /local/ucart/MicroCART/quad/vivado_workspace/vivado_workspace.runs/impl_1/quad_wrapper.sysdef /local/ucart/MicroCART/quad/xsdk_workspace_vivado/quad_wrapper.hdf
launch_sdk -workspace /local/ucart/MicroCART/quad/xsdk_workspace_vivado -hwspec /local/ucart/MicroCART/quad/xsdk_workspace_vivado/quad_wrapper.hdf
launch_sdk -workspace /local/ucart/MicroCART/quad/xsdk_workspace_vivado -hwspec /local/ucart/MicroCART/quad/xsdk_workspace_vivado/quad_wrapper.hdf
vivado.log deleted 100644 → 0
+ 0
− 297
View file @ 8372751e
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