wip: checkpoint for testing project build script.

quad/vivado_workspace/PWM_Recorder_Tests.tcl

@@ -162,19 +162,11 @@ update_ip_catalog -rebuild
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
 # Import local files from the original project
-set files [list \
- [file normalize "${origin_dir}/PWM_Recorder_Tests/PWM_Recorder_Tests.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]\
-]
-set imported_files [import_files -fileset sources_1 $files]
 
 # Set 'sources_1' fileset file properties for remote files
 # None
 
 # Set 'sources_1' fileset file properties for local files
-set file "hdl/design_1_wrapper.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "file_type" -value "VHDL" -objects $file_obj
-
 
 # Set 'sources_1' fileset properties
 set obj [get_filesets sources_1]
@@ -1076,3 +1068,7 @@ set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
 current_run -implementation [get_runs impl_1]
 
 puts "INFO: Project created:${_xil_proj_name_}"
+
+make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/design_1.bd] -top
+add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
+

quad/vivado_workspace/project_tcl/zybo_blank.tcl

@@ -1069,3 +1069,4 @@ make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name
 add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
 
 regenerate_bd_layout
+write_project_tcl ${_xil_proj_name_}.tcl