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Commit 1e449921 authored by James Talbert's avatar James Talbert
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Fix issue with block diagram wrapper 

The diagram needed to be generated as part of the project tcl, not copied in. This allpies only to new projects, not saving the project tcl for existing projects.
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quad/vivado_workspace/project_tcl/createNew.sh 0 → 100755
+ 18
− 0
View file @ 1e449921
#!/bin/bash
folder=${PWD##*/}
if [[ $folder == project_tcl ]]
then
cd ..
fi
folder=${PWD##*/}
if [[ $folder != vivado_workspace ]]
then
printf "wrong folder\n"
else
mkdir -p $1/src/constrs
cp Zybo-Z7-Master.xdc $1/src/constrs/Zybo-Z7-Master.xdc
chmod +w $1/src/constrs/Zybo-Z7-Master.xdc
echo vivado -nojou -nolog -mode batch -source project_tcl/zybo_blank.tcl -tclargs --project_name $1
vivado -nojou -nolog -mode batch -source project_tcl/zybo_blank.tcl -tclargs --project_name $1
fi
quad/vivado_workspace/project_tcl/zybo_blank.tcl
+ 17
− 29
View file @ 1e449921
#*****************************************************************************************
# Vivado (TM) v2018.2.1 (64-bit)
#
# zybo_blank.tcl: Tcl script for re-creating project 'zybo_blank'
# zybo_blank_remote_srcs.tcl: Tcl script for re-creating project 'zybo_blank'
#
# Generated by Vivado on Thu Sep 20 15:24:38 CDT 2018
# Generated by Vivado on Mon Sep 24 16:42:21 CDT 2018
# IP Build 2289599 on Thu Jul 26 21:09:20 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
......@@ -18,13 +18,12 @@
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (zybo_blank.tcl) that was generated.
# 1. This project restoration tcl script (zybo_blank_remote_srcs.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "/local/ucart/MicroCART/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd"
# "/local/ucart/MicroCART/quad/vivado_workspace/zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc"
# "/local/ucart/MicroCART/quad/vivado_workspace/zybo_blank/src/constrs/Zybo-Z7-Master.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
......@@ -100,7 +99,7 @@ if { $::argc > 0 } {
set orig_proj_dir "[file normalize "$origin_dir/${_xil_proj_name_}"]"
# Create project
create_project ${_xil_proj_name_} ${_xil_proj_name_} -part xc7z020clg400-1 -force
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
......@@ -136,6 +135,7 @@ set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj
set_property -name "target_language" -value "VHDL" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "1" -objects $obj
......@@ -143,7 +143,6 @@ set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
......@@ -161,26 +160,16 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
# Import local files from the original project
exec mkdir -p "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/"
exec cp "project_tcl/zybo_blank_wrapper.vhd" "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd"
set files [list \
[file normalize "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd" ]\
]
set imported_files [import_files -fileset sources_1 $files]
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
set file "hdl/design_1_wrapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
# None
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "design_1_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
......@@ -191,13 +180,7 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
exec mkdir -p "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/constrs_1/imports/vivado_workspace/"
exec cp "Zybo-Z7-Master.xdc" "${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc"
set file "[file normalize ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc]"
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "vivado_workspace/Zybo-Z7-Master.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj
add_files -fileset constrs_1 -norecurse ${origin_dir}/${_xil_proj_name_}/src/constrs/Zybo-Z7-Master.xdc
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
......@@ -214,6 +197,7 @@ set obj [get_filesets sim_1]
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "design_1_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
......@@ -840,10 +824,7 @@ proc cr_bd_design_1 { parentCell } {
# Restore current instance
current_bd_instance $oldCurInst
regenerate_bd_layout
save_bd_design
common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
close_bd_design $design_name
}
# End of cr_bd_design_1()
......@@ -872,6 +853,7 @@ if { $obj != "" } {
}
set obj [get_runs synth_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
# set the current synth run
......@@ -1073,6 +1055,7 @@ if { $obj != "" } {
}
set obj [get_runs impl_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
......@@ -1081,3 +1064,8 @@ set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
current_run -implementation [get_runs impl_1]
puts "INFO: Project created:${_xil_proj_name_}"
make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
regenerate_bd_layout
quad/vivado_workspace/project_tcl/zybo_blank_wrapper.vhd deleted 100644 → 0
+ 0
− 256
View file @ 03e3dd53
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.2.1 (lin64) Build 2288692 Thu Jul 26 18:23:50 MDT 2018
--Date : Thu Sep 20 14:07:28 2018
--Host : co3050-12.ece.iastate.edu running 64-bit Red Hat Enterprise Linux Workstation release 6.6 (Santiago)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
jb0 : in STD_LOGIC;
leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 );
rgb_led_tri_io : inout STD_LOGIC_VECTOR ( 5 downto 0 );
sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
sws_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
rgb_led_tri_i : in STD_LOGIC_VECTOR ( 5 downto 0 );
rgb_led_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 );
rgb_led_tri_t : out STD_LOGIC_VECTOR ( 5 downto 0 );
jb0 : in STD_LOGIC
);
end component design_1;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
begin
design_1_i: component design_1
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
btns_4bits_tri_i(3 downto 0) => btns_4bits_tri_i(3 downto 0),
jb0 => jb0,
leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),
leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),
leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),
leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),
leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),
leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),
leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),
leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),
leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),
leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),
leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),
leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0),
rgb_led_tri_i(5) => rgb_led_tri_i_5(5),
rgb_led_tri_i(4) => rgb_led_tri_i_4(4),
rgb_led_tri_i(3) => rgb_led_tri_i_3(3),
rgb_led_tri_i(2) => rgb_led_tri_i_2(2),
rgb_led_tri_i(1) => rgb_led_tri_i_1(1),
rgb_led_tri_i(0) => rgb_led_tri_i_0(0),
rgb_led_tri_o(5) => rgb_led_tri_o_5(5),
rgb_led_tri_o(4) => rgb_led_tri_o_4(4),
rgb_led_tri_o(3) => rgb_led_tri_o_3(3),
rgb_led_tri_o(2) => rgb_led_tri_o_2(2),
rgb_led_tri_o(1) => rgb_led_tri_o_1(1),
rgb_led_tri_o(0) => rgb_led_tri_o_0(0),
rgb_led_tri_t(5) => rgb_led_tri_t_5(5),
rgb_led_tri_t(4) => rgb_led_tri_t_4(4),
rgb_led_tri_t(3) => rgb_led_tri_t_3(3),
rgb_led_tri_t(2) => rgb_led_tri_t_2(2),
rgb_led_tri_t(1) => rgb_led_tri_t_1(1),
rgb_led_tri_t(0) => rgb_led_tri_t_0(0),
sws_4bits_tri_i(3 downto 0) => sws_4bits_tri_i(3 downto 0)
);
leds_4bits_tri_iobuf_0: component IOBUF
port map (
I => leds_4bits_tri_o_0(0),
IO => leds_4bits_tri_io(0),
O => leds_4bits_tri_i_0(0),
T => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_1: component IOBUF
port map (
I => leds_4bits_tri_o_1(1),
IO => leds_4bits_tri_io(1),
O => leds_4bits_tri_i_1(1),
T => leds_4bits_tri_t_1(1)
);
leds_4bits_tri_iobuf_2: component IOBUF
port map (
I => leds_4bits_tri_o_2(2),
IO => leds_4bits_tri_io(2),
O => leds_4bits_tri_i_2(2),
T => leds_4bits_tri_t_2(2)
);
leds_4bits_tri_iobuf_3: component IOBUF
port map (
I => leds_4bits_tri_o_3(3),
IO => leds_4bits_tri_io(3),
O => leds_4bits_tri_i_3(3),
T => leds_4bits_tri_t_3(3)
);
rgb_led_tri_iobuf_0: component IOBUF
port map (
I => rgb_led_tri_o_0(0),
IO => rgb_led_tri_io(0),
O => rgb_led_tri_i_0(0),
T => rgb_led_tri_t_0(0)
);
rgb_led_tri_iobuf_1: component IOBUF
port map (
I => rgb_led_tri_o_1(1),
IO => rgb_led_tri_io(1),
O => rgb_led_tri_i_1(1),
T => rgb_led_tri_t_1(1)
);
rgb_led_tri_iobuf_2: component IOBUF
port map (
I => rgb_led_tri_o_2(2),
IO => rgb_led_tri_io(2),
O => rgb_led_tri_i_2(2),
T => rgb_led_tri_t_2(2)
);
rgb_led_tri_iobuf_3: component IOBUF
port map (
I => rgb_led_tri_o_3(3),
IO => rgb_led_tri_io(3),
O => rgb_led_tri_i_3(3),
T => rgb_led_tri_t_3(3)
);
rgb_led_tri_iobuf_4: component IOBUF
port map (
I => rgb_led_tri_o_4(4),
IO => rgb_led_tri_io(4),
O => rgb_led_tri_i_4(4),
T => rgb_led_tri_t_4(4)
);
rgb_led_tri_iobuf_5: component IOBUF
port map (
I => rgb_led_tri_o_5(5),
IO => rgb_led_tri_io(5),
O => rgb_led_tri_i_5(5),
T => rgb_led_tri_t_5(5)
);
end STRUCTURE;
quad/vivado_workspace/zybo_blank/zybo_blank.srcs/constrs_1/imports/vivado_workspace/Zybo-Z7-Master.xdc deleted 100644 → 0
+ 0
− 198
View file @ 03e3dd53
## This file is a general .xdc for the Zybo Z7 Rev. B
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
##Clock signal
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
##Switches
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
##Buttons
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
##LEDs
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
##RGB LED 5 (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
##RGB LED 6
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
##Audio Codec
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
##Additional Ethernet signals
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
##USB-OTG over-current detect pin
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
##Fan (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
##HDMI RX
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
##HDMI RX CEC (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
##HDMI TX
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
##HDMI TX CEC
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
##Pmod Header JA (XADC)
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
##Pmod Header JB (Zybo Z7-20 only)
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb0 }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
##Pmod Header JC
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
##Pmod Header JD
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
##Pcam MIPI CSI-2 Connector
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
##Unloaded Crypto Chip SWI (for future use)
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
##Unconnected Pins (Zybo Z7-20 only)
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
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