update to quad hw tcl

quad/vivado_workspace/quad_hw.tcl

@@ -283,6 +283,8 @@ proc cr_bd_design_1 { parentCell } {
   set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ]
 
   # Create ports
+  set UART0_RX_0 [ create_bd_port -dir I UART0_RX_0 ]
+  set UART0_TX_0 [ create_bd_port -dir O UART0_TX_0 ]
   set pwm_in_0 [ create_bd_port -dir I pwm_in_0 ]
   set pwm_in_1 [ create_bd_port -dir I pwm_in_1 ]
   set pwm_in_2 [ create_bd_port -dir I pwm_in_2 ]
@@ -294,6 +296,7 @@ proc cr_bd_design_1 { parentCell } {
   set pwm_out_2 [ create_bd_port -dir O pwm_out_2 ]
   set pwm_out_3 [ create_bd_port -dir O pwm_out_3 ]
 
+
   # Create instance: axi_gpio_0, and set properties
   set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
   set_property -dict [ list \
@@ -881,8 +884,10 @@ proc cr_bd_design_1 { parentCell } {
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M14_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M14_AXI]
 
   # Create port connections
+  connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins processing_system7_0/UART0_RX]
   connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
   connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
+  connect_bd_net -net processing_system7_0_UART0_TX [get_bd_ports UART0_TX_0] [get_bd_pins processing_system7_0/UART0_TX]
   connect_bd_net -net pwm_in_master_0_1 [get_bd_ports pwm_in_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
   connect_bd_net -net pwm_in_master_1_1 [get_bd_ports pwm_in_1] [get_bd_pins pwm_recorder_1/pwm_in_master]
   connect_bd_net -net pwm_in_master_2_1 [get_bd_ports pwm_in_2] [get_bd_pins pwm_recorder_2/pwm_in_master]
@@ -1159,3 +1164,4 @@ puts "INFO: Project created:${_xil_proj_name_}"
 make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/design_1.bd] -top
 add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
 
+