Petalinux-Hardware-Design.md

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-TODO explain how the demo hardware design was modified to support our additional hardware needs
+Hardware Design setup step Vivado Project Setup Hardware Design Process IP Core documentation and reference
+
+# Vivado Project Setup
+
+## 0. Project Clone from GIT
+
+- Download the project repo from git (if you run into xpfm path not found issue in Vitis, please see //TODO)
+
+## 1. Open Vivado
+
+- This project is made using Vivado 2020.1, please open this project from Vivado 2020.1 or later. If you are using a newer version, you might need to update the IP.
+
+## 2. Open Hardware Project
+
+- Go to File - Project - Open Project ![image](uploads/9f5aeaad5bb3f292f40b5126d01c35c9/image.png)
+- Navigate to the full firmware build folder under the project root folder
+- Open the full_firmware_build.xpr file ![image](uploads/ed863cc0077feb0c20750c78859ec549/image.png) ![image](uploads/71a5cc57eac050355d5a815fd89a8895/image.png)
+
+## 3. Project Layout
+
+- After the project initialization, go to the design sourse window ![image](uploads/d2fec127aa18e21981fcad34ca3ae844/image.png)
+- Doule click on the design_1_wrapper(vhdl wrapper), then double click the design_1_i: design_1 file(block desgin) ![image](uploads/9c54fd1abd9dd68b2496780bf2a41cd5/image.png)
+- Now the project is loaded and ready to go.
+
+# Hardware Design Process
+
+## 1. Validate design
+
+- After editing any IP, click the Validate design button(located on the top bar of the block diagram) or press F6
+
+![image](uploads/860d72a1a8ee18c89a7df0ec76f9a936/image.png)
+
+## 2. Generate Output Products
+
+- If you just modified a HLS IP or an custom IP, right click the block diagram file in the design source window, and selete generate output products
+
+![image](uploads/a1b063553c52facff51220f9d78b9a11/image.png)
+
+## 3. Submodule Run
+
+- If you are load a brand new project or just generated new output products, there is going to be a sub-module run before you can continue (if you run into Submodule run failed problem, please see Xilinx support center for any related patch such as patch y2k22 for VPSS)
+
+![image](uploads/9467e8f406580bcf606e102ec1d04316/image.png)
+
+## 4. Sythesis, Implementation, Generate Bitstream
+
+The design process has three parts: Sythesis, Implementation, Generate Bitstream in this order. For convience, you can just click generate Bitstream, and the two process will run automaticly if they are out-of-date.(make sure you have validated the design before doing this, many AXI bus IP auto-adjust their bitwith during that process)
+
+![image](uploads/d5dd62591c3dce5b8ce5f22049e46f02/image.png) ![image](uploads/b12f2b7ef01423133496b452373f6cd2/image.png) ![image](uploads/1a0b146d91ed1121218b341841cc4b39/image.png)
+
+## 5. After the Generate Bitstream process
+
+- After the Generate Bitstream process is finished, close the pop up window
+- Hardware Manager can be very helpful for hw/sw debug, but you need to setup ILA to probe wires ![image](uploads/5f93d0edb5384ece0c26304738752dab/image.png)
+
+## 6. Export Hardware
+
+- Go to File - Export - Export Hardware, in the pop up window, select Fixed, then click next. select Include bitstream, then click next. You shouldn't need to change the name of the xsa file, but if you do make sure to update that in your Vitis platform project or linux boot drive. Finally, click finish. ![image](uploads/235c305dcd182a0b7b2de5f9d1e1d709/image.png) ![image](uploads/62e8a56aab884b0fa53cb7cd6fc9b919/image.png) ![image](uploads/7e1f68246a2cbab24adec29ee73e9834/image.png) ![image](uploads/0f3c1d42b4f629f7337eea5c7df0ba6f/image.png)
+- the xsa file contains everything you have done in the hardware design, and that is how the FPGA reads the hardware configuration.
+
+# IP Core documentation and reference
+
+## Processor core
+
+### Zynq-7000 Processing System IP
+
+- Processing System 7 v5.5 Product Guide (PG082): https://docs.xilinx.com/v/u/en-US/pg082-processing-system7
+- Designing High-Performance Video Systems with the Zynq-7000 All Programmable SoC Using IP Integrator: https://docs.xilinx.com/v/u/en-US/xapp1205-high-performance-video-zynq
+
+## Connection cores:
+
+### Axis Subset Converter
+
+- AXI4-Stream Interconnect v1.1 Product Guide (PG035): https://docs.xilinx.com/v/u/en-US/pg035_axis_interconnect
+- AXI4-Stream Infrastructure IP Suite (PG085): https://docs.xilinx.com/r/en-US/pg085-axi4stream-infrastructure
+- AXI Reference Guide (UG761): https://docs.xilinx.com/v/u/en-US/ug761_axi_reference_guide
+
+### AXI Interconnect
+
+- LogiCORE IP AXI Interconnect (v1.06.a) Data Sheet (AXI)(DS768): https://docs.xilinx.com/v/u/en-US/ds768_axi_interconnect
+- AXI Interconnect LogiCORE IP Product Guide (PG059): https://docs.xilinx.com/r/en-US/pg059-axi-interconnect
+
+## Function cores
+
+### XADC Wizard
+
+- XADC Wizard v3.3 Product Guide (PG091): https://docs.xilinx.com/v/u/en-US/pg091-xadc-wiz
+- Xilinx UG772 LogiCORE IP XADC Wizard v2.2, User Guide: https://docs.xilinx.com/v/u/en-US/ug772_xadc_wiz
+
+### AXI GPIO
+
+- LogiCORE IP AXI GPIO (v1.01b) Data Sheet (AXI): https://docs.xilinx.com/v/u/1.01b-English/ds744_axi_gpio
+- AXI GPIO v2.0 LogiCORE IP Product Guide (PG144): https://docs.xilinx.com/v/u/en-US/pg144-axi-gpio
+
+### AXI Timer/Counter
+
+- LogiCORE IP AXI Timer (axi_timer) (v1.03.a) Data Sheet (AXI)(DS764): https://docs.xilinx.com/v/u/en-US/axi_timer_ds764
+- AXI Timer v2.0 Product Guide (PG079): https://docs.xilinx.com/v/u/en-US/pg079-axi-timer
+
+### AXI Quad SPI
+
+- LogiCORE IP AXI Quad Serial Peripheral Interface (axi_quad_spi) (v1.00a) Data Sheet: https://docs.xilinx.com/v/u/en-US/ds843_axi_quad_spi
+- PG153 AXI Quad SPI Product Guide: https://docs.xilinx.com/r/en-US/pg153-axi-quad-spi
+
+### AXI IIC
+
+- LogiCORE IP AXI IIC Bus Interface (v1.02a) Data Sheet (AXI): https://docs.xilinx.com/v/u/1.02a-English/axi_iic_ds756
+- AXI IIC Bus Interface v2.1 LogiCORE IP Product Guide (PG090): https://docs.xilinx.com/v/u/en-US/pg090-axi-iic
+
+### Processor System Reset Module
+
+- Processor System Reset Module v5.0 Product Guide (PG164): https://docs.xilinx.com/v/u/en-US/pg164-proc-sys-reset
+- PCI Express Endpoint-DMA Initiator Subsystem Application Note (XAPP1171): https://docs.xilinx.com/v/u/en-US/xapp1171-pcie-central-dma-subsystem
+
+## Memory cores
+
+### AXI Direct Memory Access:
+
+- AXI DMA LogiCORE IP Product Guide (PG021): https://docs.xilinx.com/r/en-US/pg021_axi_dma
+
+# Resource
+
+- Vivado Design Suite User Guide: Embedded: https://docs.xilinx.com/v/u/en-US/ug898-vivado-embedded-design
+- Vivado Design Suite Tutorial: https://docs.xilinx.com/v/u/2016.1-English/ug937-vivado-design-suite-simulation-tutorial
+- Zynq-7000 SoC: Embedded Design Tutorial: https://docs.xilinx.com/v/u/2020.1-English/ug1165-zynq-embedded-design-tutorial
+- Zynq-7000 All Programmable SoC Software Developers Guide: https://docs.xilinx.com/v/u/en-US/ug821-zynq-7000-swdev
+- Embedded System Tools Reference Manual: https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx14_7/est_rm.pdf
+- Synthesis and Simulation Design Guide: https://www.xilinx.com/htmldocs/xilinx14_7/sim.pdf
 
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