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Created with Raphaël 2.2.06Feb543216Dec9Nov722Sep8Jul28Jun27263May-Added some missing type hintsverilog_helperverilog_helper-Fixed blacklist issue in the verilog file presence checker function.-Made a package for the colors used in this project-Almost done adding the openlane config blacklist.-Fixed the issue where defines.v would be found if user_defines.v was in the file (thanks RegEx!)-Removing files now works-Removed type declaration since it is a feature added to python 3.12, which is more recent than the min python version required-Removed all clear statments so we keep terminal history-Finished include update code-Made the verilog file presence function provide a list of all files that the verilog file is NOT included in.-Fixed a small bug where if a verilog file is in all the includes files but not in the openlane config, it is shown as not being in the project at all-Got the "list" feature working-Reworked menus to be child classes of Menu instead of package global instances of Menu.-Added a basic project menu (mostly stubs for now)-Fixed submenu returning-Created the proper main menu and implemented a basic project structure check.-Created a menu class-Added the verilog helper command-Updated project to include some missing dependencies.Release 0.0.390.0.390.0.39Release 0.0.380.0.38 master0.0.38 masterRelease 0.0.370.0.370.0.37Release 0.0.360.0.360.0.36Release 0.0.350.0.350.0.35Release 0.0.340.0.340.0.34Release 0.0.330.0.330.0.33Added uart ports and bootingRelease 0.0.320.0.320.0.32FPGA update to use JTAG for hkspi, no external spi adapter needed anymoreRelease 0.0.310.0.310.0.31Release 0.0.30Update hk.pyRelease 0.0.300.0.300.0.30Release 0.0.290.0.290.0.29Release 0.0.280.0.280.0.28Release 0.0.270.0.270.0.27Release 0.0.260.0.260.0.26Release 0.0.250.0.250.0.25Release 0.0.240.0.240.0.24Release 0.0.230.0.230.0.23