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Created with Raphaël 2.2.029Nov2217151412131210765321212127Oct201819181918136Ready project for submissionmainmainAdd output to gitignoreAdd bubblesort testMerge branch 'main' of git.ece.iastate.edu:cpre-381-project-1/project1 into mainAdd stack frame testSynth DumpSynth LogFor Synth LogsSynthesis DoneAdd Proj1_base_test.sFix incorrect lw control signalsFix arithmetic shifts shifting in 0s regardless of sign bitMerge branch 'main' of git.ece.iastate.edu:cpre-381-project-1/project1 into mainFix missing overflow disable on subuAdd overflow enable controlBetter Arith TestFixed ArithUpdatedFix edge cases for sltFix incorrect jr condition, revert andi and ori regdst changesFix incorrect signals for swConnect regfile to reset lineFix incorrect signals for repl.qb and add opReplQb output signalFix incorrect input to repl.qbAdd mux to switch to repl.qb immFix wrong RegDst for repl.qbFix swapped inputs to barrel shifterFix placement of shift muxMerge branch 'main' of git.ece.iastate.edu:cpre-381-project-1/project1 into mainFix signextend for R and I type instrFix signextend being '0' for allFix PC reset addressFix incorrect regwrite output for jalAdd missing ALU op signals to control sigs spreadsheetFix missing beq and bne ALU opsFix misinterpretation of slt outputMove testbench files to external testbenches folderUpdatedThru Part 2Control Test