Commits · af914bb26654a2f21be71f03896564981ef74c2f · CprE 381 Project 1 / Project1

Nov 10, 2022
- Fix signextend for R and I type instr · af914bb2
  butler1 authored 2 years ago
  
  af914bb2
- Fix signextend being '0' for all · 884dcb80
  butler1 authored 2 years ago
  
  884dcb80
- Fix PC reset address · 940eed7c
  butler1 authored 2 years ago
  
  940eed7c
- Fix incorrect regwrite output for jal · c1190a45
  butler1 authored 2 years ago
  
  c1190a45
- Add missing ALU op signals to control sigs spreadsheet · 2b909837
  butler1 authored 2 years ago
  
  2b909837
- Fix missing beq and bne ALU ops · 565c783b
  butler1 authored 2 years ago
  
  565c783b
- Fix misinterpretation of slt output · ecfb3c43
  butler1 authored 2 years ago
  
  ecfb3c43
- Move testbench files to external testbenches folder · 3d7c20ea
  butler1 authored 2 years ago
  
  3d7c20ea
Nov 06, 2022
- Control Test · 095a9ff1
  tnd authored 2 years ago
  
  095a9ff1
- Barrel Test · ce719137
  tnd authored 2 years ago
  
  ce719137
- ALU Test · c8bbbf49
  tnd authored 2 years ago
  
  c8bbbf49
- Updated · 4112c537
  tnd authored 2 years ago
  
  4112c537
Nov 05, 2022
- Update report with fetch simulation · 23783c74
  butler1 authored 2 years ago
  
  23783c74
- Add unit test for fetch to increment PC by 4 · 1a13229b
  butler1 authored 2 years ago
  
  1a13229b
- Update report · 38742bfa
  butler1 authored 2 years ago
  
  38742bfa
Nov 03, 2022
- Update project report · 49d975c2
  butler1 authored 2 years ago
  
  49d975c2
- Fix bad mux, add sign_extend, make add_1.s work · 74cf2d93
  butler1 authored 2 years ago
  
  74cf2d93
- Add SignExtend signal and fix RegDst mapping · 16a242e5
  butler1 authored 2 years ago
  
  16a242e5
- Add additional fetch tests · 4c326b8f
  butler1 authored 2 years ago
  
  4c326b8f
- Fix ALU lui input port · 2d4f1321
  butler1 authored 2 years ago
  
  2d4f1321
- Updated Signals · 7ae08d19
  tnd authored 2 years ago
  
  7ae08d19
- Updated Signals · c75d0fa8
  tnd authored 2 years ago
  
  c75d0fa8
- TestBench For Control · 2cf68a42
  tnd authored 2 years ago
  
  2cf68a42
- Fixed Issues · 550b694b
  tnd authored 2 years ago
  
  550b694b
- Added subu · 676d576c
  tnd authored 2 years ago
  
  676d576c
Nov 02, 2022
- Report · daf19abb
  tnd authored 2 years ago
  
  daf19abb
- Add missing signals to top level · ba078069
  butler1 authored 2 years ago
  
  ba078069
- Get processor running in simulation · ecf020ea
  butler1 authored 2 years ago
  
  ecf020ea
- Update .gitignore · dab2acf5
  butler1 authored 2 years ago
  
  dab2acf5
- Merge branch 'main' of git.ece.iastate.edu:cpre-382-project-1/project1 into main · d82f64e3
  butler1 authored 2 years ago
  
  d82f64e3
- Replace barrelShifter.vhd · db4805fa
  tnd authored 2 years ago
  
  db4805fa
- Fix ALU zero output · d95a8ede
  butler1 authored 2 years ago
  
  d95a8ede
- Decompress updated files · 6a6af793
  butler1 authored 2 years ago
  
  6a6af793
- Merge branch 'main' of git.ece.iastate.edu:cpre-381-project-1/project1 into main · e0f4e4b0
  butler1 authored 2 years ago
  
  e0f4e4b0
- Add testbench for mux2to1_N · 64eb0773
  butler1 authored 2 years ago
  
  64eb0773
- Add inverter to logic · f90e29bf
  butler1 authored 2 years ago
  
  f90e29bf
- Get fetch testbench working · 63f0254d
  butler1 authored 2 years ago
  
  63f0254d
- Updated Files · 5ca4958d
  tnd authored 2 years ago
  
  5ca4958d
- Fix missing size on fetch vector, add fetch testbench · e6406c34
  butler1 authored 2 years ago
  
  e6406c34
- Fix missing control signals · 616f54c6
  butler1 authored 2 years ago
  
  616f54c6