Commits · 63e9cd1f6ea266a76dfdbde9b24d6efb719c1ed9 · CprE 381 Project 1 / Project1

Nov 14, 2022
- Merge branch 'main' of git.ece.iastate.edu:cpre-381-project-1/project1 into main · 63e9cd1f
  butler1 authored 2 years ago
  
  63e9cd1f
- Fix missing overflow disable on subu · 09ace652
  butler1 authored 2 years ago
  
  09ace652
Nov 13, 2022
- Add overflow enable control · 6470fd60
  butler1 authored 2 years ago
  
  6470fd60
- Better Arith Test · b15b2630
  tnd authored 2 years ago
  
  b15b2630
- Fixed Arith · 3bad5a2b
  tnd authored 2 years ago
  
  3bad5a2b
- Updated · 7a8c4b2b
  tnd authored 2 years ago
  
  7a8c4b2b
Nov 12, 2022
- Fix edge cases for slt · 33a43135
  butler1 authored 2 years ago
  
  33a43135
- Fix incorrect jr condition, revert andi and ori regdst changes · c5c955a2
  butler1 authored 2 years ago
  
  c5c955a2
- Fix incorrect signals for sw · 3ef68c85
  butler1 authored 2 years ago
  
  3ef68c85
- Connect regfile to reset line · d47be96e
  butler1 authored 2 years ago
  
  d47be96e
- Fix incorrect signals for repl.qb and add opReplQb output signal · 1a460e23
  butler1 authored 2 years ago
  
  1a460e23
- Fix incorrect input to repl.qb · 8681d00b
  butler1 authored 2 years ago
  
  8681d00b
- Add mux to switch to repl.qb imm · bebc4129
  butler1 authored 2 years ago
  
  bebc4129
- Fix wrong RegDst for repl.qb · d9fb2756
  butler1 authored 2 years ago
  
  d9fb2756
- Fix swapped inputs to barrel shifter · cdcf9623
  butler1 authored 2 years ago
  
  cdcf9623
- Fix placement of shift mux · fb0eaae4
  butler1 authored 2 years ago
  
  fb0eaae4
Nov 10, 2022
- Merge branch 'main' of git.ece.iastate.edu:cpre-381-project-1/project1 into main · c9441e85
  butler1 authored 2 years ago
  
  c9441e85
- Fix signextend for R and I type instr · af914bb2
  butler1 authored 2 years ago
  
  af914bb2
- Fix signextend being '0' for all · 884dcb80
  butler1 authored 2 years ago
  
  884dcb80
- Fix PC reset address · 940eed7c
  butler1 authored 2 years ago
  
  940eed7c
- Fix incorrect regwrite output for jal · c1190a45
  butler1 authored 2 years ago
  
  c1190a45
- Add missing ALU op signals to control sigs spreadsheet · 2b909837
  butler1 authored 2 years ago
  
  2b909837
- Fix missing beq and bne ALU ops · 565c783b
  butler1 authored 2 years ago
  
  565c783b
- Fix misinterpretation of slt output · ecfb3c43
  butler1 authored 2 years ago
  
  ecfb3c43
- Move testbench files to external testbenches folder · 3d7c20ea
  butler1 authored 2 years ago
  
  3d7c20ea
Nov 07, 2022
- Updated · 16600fde
  tnd authored 2 years ago
  
  16600fde
- Thru Part 2 · e35f7f46
  tnd authored 2 years ago
  
  e35f7f46
Nov 06, 2022
- Control Test · 095a9ff1
  tnd authored 2 years ago
  
  095a9ff1
- Barrel Test · ce719137
  tnd authored 2 years ago
  
  ce719137
- ALU Test · c8bbbf49
  tnd authored 2 years ago
  
  c8bbbf49
- Updated · 4112c537
  tnd authored 2 years ago
  
  4112c537
Nov 05, 2022
- Update report with fetch simulation · 23783c74
  butler1 authored 2 years ago
  
  23783c74
- Add unit test for fetch to increment PC by 4 · 1a13229b
  butler1 authored 2 years ago
  
  1a13229b
- Update report · 38742bfa
  butler1 authored 2 years ago
  
  38742bfa
Nov 03, 2022
- Update project report · 49d975c2
  butler1 authored 2 years ago
  
  49d975c2
- Fix bad mux, add sign_extend, make add_1.s work · 74cf2d93
  butler1 authored 2 years ago
  
  74cf2d93
- Add SignExtend signal and fix RegDst mapping · 16a242e5
  butler1 authored 2 years ago
  
  16a242e5
- Add additional fetch tests · 4c326b8f
  butler1 authored 2 years ago
  
  4c326b8f
- Fix ALU lui input port · 2d4f1321
  butler1 authored 2 years ago
  
  2d4f1321
- Updated Signals · 7ae08d19
  tnd authored 2 years ago
  
  7ae08d19