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WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_SRSTB_pin_IBUF" LOC = B10>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:58 - Constraint <TIMEGRP
axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match
any design objects.
WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does
not directly or indirectly drive any flip-flops, latches and/or RAMs and is
not actively used by any referencing constraint.
Done...
Processing BMM file "system.bmm" ...
WARNING::53 - File 'system.bmm' is empty or has no BMM content.
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver
WARNING:NgdBuild:452 - logical net 'N155' has no driver
WARNING:NgdBuild:452 - logical net 'N156' has no driver
WARNING:NgdBuild:452 - logical net 'N157' has no driver
WARNING:NgdBuild:452 - logical net 'N158' has no driver
WARNING:NgdBuild:452 - logical net 'N159' has no driver
WARNING:NgdBuild:452 - logical net 'N160' has no driver
WARNING:NgdBuild:452 - logical net 'N161' has no driver
WARNING:NgdBuild:452 - logical net 'N162' has no driver
WARNING:NgdBuild:452 - logical net 'N163' has no driver
WARNING:NgdBuild:452 - logical net 'N164' has no driver
WARNING:NgdBuild:452 - logical net 'N165' has no driver
WARNING:NgdBuild:452 - logical net 'N166' has no driver
WARNING:NgdBuild:452 - logical net 'N167' has no driver
WARNING:NgdBuild:452 - logical net 'N168' has no driver
WARNING:NgdBuild:452 - logical net 'N169' has no driver
WARNING:NgdBuild:452 - logical net 'N170' has no driver
WARNING:NgdBuild:452 - logical net 'N171' has no driver
WARNING:NgdBuild:452 - logical net 'N172' has no driver
WARNING:NgdBuild:452 - logical net 'N173' has no driver
WARNING:NgdBuild:452 - logical net 'N174' has no driver
WARNING:NgdBuild:452 - logical net 'N175' has no driver
WARNING:NgdBuild:452 - logical net 'N176' has no driver
WARNING:NgdBuild:452 - logical net 'N177' has no driver
WARNING:NgdBuild:452 - logical net 'N178' has no driver
WARNING:NgdBuild:452 - logical net 'N179' has no driver
WARNING:NgdBuild:452 - logical net 'N180' has no driver
WARNING:NgdBuild:452 - logical net 'N181' has no driver
WARNING:NgdBuild:452 - logical net 'N182' has no driver
WARNING:NgdBuild:452 - logical net 'N183' has no driver
WARNING:NgdBuild:452 - logical net 'N184' has no driver
WARNING:NgdBuild:452 - logical net 'N185' has no driver
WARNING:NgdBuild:452 - logical net 'N186' has no driver
WARNING:NgdBuild:452 - logical net 'N187' has no driver
WARNING:NgdBuild:452 - logical net 'N188' has no driver
WARNING:NgdBuild:452 - logical net 'N189' has no driver
WARNING:NgdBuild:452 - logical net 'N190' has no driver
WARNING:NgdBuild:452 - logical net 'N191' has no driver
WARNING:NgdBuild:452 - logical net 'N192' has no driver
WARNING:NgdBuild:452 - logical net 'N193' has no driver
WARNING:NgdBuild:452 - logical net 'N194' has no driver
WARNING:NgdBuild:452 - logical net 'N195' has no driver
WARNING:NgdBuild:452 - logical net 'N196' has no driver
WARNING:NgdBuild:452 - logical net 'N197' has no driver
WARNING:NgdBuild:452 - logical net 'N198' has no driver
WARNING:NgdBuild:452 - logical net 'N199' has no driver
WARNING:NgdBuild:452 - logical net 'N200' has no driver
WARNING:NgdBuild:452 - logical net 'N201' has no driver
WARNING:NgdBuild:452 - logical net 'N202' has no driver
WARNING:NgdBuild:452 - logical net 'N203' has no driver
WARNING:NgdBuild:452 - logical net 'N204' has no driver
WARNING:NgdBuild:452 - logical net 'N205' has no driver
WARNING:NgdBuild:452 - logical net 'N206' has no driver
WARNING:NgdBuild:452 - logical net 'N207' has no driver
WARNING:NgdBuild:452 - logical net 'N208' has no driver
WARNING:NgdBuild:452 - logical net 'N209' has no driver
WARNING:NgdBuild:452 - logical net 'N210' has no driver
WARNING:NgdBuild:452 - logical net 'N211' has no driver
WARNING:NgdBuild:452 - logical net 'N212' has no driver
WARNING:NgdBuild:452 - logical net 'N213' has no driver
WARNING:NgdBuild:452 - logical net 'N214' has no driver
WARNING:NgdBuild:452 - logical net 'N215' has no driver
WARNING:NgdBuild:452 - logical net 'N216' has no driver
WARNING:NgdBuild:452 - logical net 'N217' has no driver
WARNING:NgdBuild:452 - logical net 'N218' has no driver
WARNING:NgdBuild:452 - logical net 'N219' has no driver
WARNING:NgdBuild:452 - logical net 'N220' has no driver
WARNING:NgdBuild:452 - logical net 'N221' has no driver
WARNING:NgdBuild:452 - logical net 'N222' has no driver
WARNING:NgdBuild:452 - logical net 'N223' has no driver
WARNING:NgdBuild:452 - logical net 'N224' has no driver
WARNING:NgdBuild:452 - logical net 'N225' has no driver
WARNING:NgdBuild:452 - logical net 'N226' has no driver
WARNING:NgdBuild:452 - logical net 'N227' has no driver
WARNING:NgdBuild:452 - logical net 'N228' has no driver
WARNING:NgdBuild:452 - logical net 'N229' has no driver
WARNING:NgdBuild:452 - logical net 'N230' has no driver
WARNING:NgdBuild:452 - logical net 'N231' has no driver
WARNING:NgdBuild:452 - logical net 'N232' has no driver
WARNING:NgdBuild:452 - logical net 'N233' has no driver
WARNING:NgdBuild:452 - logical net 'N234' has no driver
WARNING:NgdBuild:452 - logical net 'N235' has no driver
WARNING:NgdBuild:452 - logical net 'N236' has no driver
WARNING:NgdBuild:452 - logical net 'N237' has no driver
WARNING:NgdBuild:452 - logical net 'N238' has no driver
WARNING:NgdBuild:452 - logical net 'N239' has no driver
WARNING:NgdBuild:452 - logical net 'N240' has no driver
WARNING:NgdBuild:452 - logical net 'N241' has no driver
WARNING:NgdBuild:452 - logical net 'N242' has no driver
WARNING:NgdBuild:452 - logical net 'N243' has no driver
WARNING:NgdBuild:452 - logical net 'N244' has no driver
WARNING:NgdBuild:452 - logical net 'N245' has no driver
WARNING:NgdBuild:452 - logical net 'N246' has no driver
WARNING:NgdBuild:452 - logical net 'N247' has no driver
WARNING:NgdBuild:452 - logical net 'N248' has no driver
WARNING:NgdBuild:452 - logical net 'N249' has no driver
WARNING:NgdBuild:452 - logical net 'N250' has no driver
WARNING:NgdBuild:452 - logical net 'N251' has no driver
WARNING:NgdBuild:452 - logical net 'N252' has no driver
WARNING:NgdBuild:452 - logical net 'N253' has no driver
WARNING:NgdBuild:452 - logical net 'N254' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 132
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 25 sec
Total CPU time to NGDBUILD completion: 25 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 14.7 - Map P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "7z010clg400-1".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
WARNING:LIT:701 - PAD symbol "CLK_N" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_N" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "CLK_P" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_P" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB_pin" has an
undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB_pin" is not
constrained (LOC) to a specific location.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal CLK_P connected to top level port CLK_P has been
removed.
WARNING:MapLib:701 - Signal CLK_N connected to top level port CLK_N has been
removed.
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 27 secs
Total CPU time at the beginning of Placer: 27 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:8310d50b) REAL time: 29 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:8310d50b) REAL time: 30 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:8310d50b) REAL time: 30 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:abb3fc01) REAL time: 34 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:abb3fc01) REAL time: 34 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:abb3fc01) REAL time: 34 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:abb3fc01) REAL time: 34 secs
Phase 8.8 Global Placement
................................
....................................................................................................................................
.........................................................................................................................................................
Phase 8.8 Global Placement (Checksum:e347f06c) REAL time: 40 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:e347f06c) REAL time: 40 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:ab7cf133) REAL time: 43 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:ab7cf133) REAL time: 43 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:ab7cf133) REAL time: 44 secs
Total REAL time to Placer completion: 44 secs
Total CPU time to Placer completion: 44 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 12
Slice Logic Utilization:
Number of Slice Registers: 2,373 out of 35,200 6%
Number used as Flip Flops: 2,116
Number used as Latches: 256
Number used as Latch-thrus: 0
Number used as AND/OR logics: 1
Number of Slice LUTs: 2,146 out of 17,600 12%
Number used as logic: 2,042 out of 17,600 11%
Number using O6 output only: 1,096
Number using O5 output only: 224
Number using O5 and O6: 722
Number used as ROM: 0
Number used as Memory: 4 out of 6,000 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 100
Number with same-slice register load: 96
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 938 out of 4,400 21%
Number of LUT Flip Flop pairs used: 3,038
Number with an unused Flip Flop: 983 out of 3,038 32%
Number with an unused LUT: 892 out of 3,038 29%
Number of fully used LUT-FF pairs: 1,163 out of 3,038 38%
Number of unique control sets: 106
Number of slice register sites lost
to control set restrictions: 432 out of 35,200 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 16 out of 100 16%
Number of LOCed IOBs: 16 out of 16 100%
Number of bonded IOPAD: 130 out of 130 100%
IOB Flip Flops: 6
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 60 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 120 0%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 5
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 100 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 6 out of 100 6%
Number used as ILOGICE2s: 6
Number used as ILOGICE3s: 0
Number used as ISERDESE2s: 0
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 100 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 8 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 8 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 48 0%
Number of BUFRs: 0 out of 8 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 80 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 2 0%
Number of IN_FIFOs: 0 out of 8 0%
Number of MMCME2_ADVs: 0 out of 2 0%
Number of OUT_FIFOs: 0 out of 8 0%
Number of PHASER_REFs: 0 out of 2 0%
Number of PHY_CONTROLs: 0 out of 2 0%
Number of PLLE2_ADVs: 0 out of 2 0%
Number of PS7s: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.25
Peak Memory Usage: 1270 MB
Total REAL time to MAP completion: 46 secs
Total CPU time to MAP completion: 46 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/14.7/ISE_DS/EDK/data/parBmgr.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/parBmgr.acd>
Constraints file: system.pcf.
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.08 2013-10-13".
Device Utilization Summary:
Number of BUFGs 5 out of 32 15%
Number of ILOGICE2s 6 out of 100 6%
Number of External IOB33s 16 out of 100 16%
Number of LOCed IOB33s 16 out of 16 100%
Number of External IOPADs 130 out of 130 100%
Number of LOCed IOPADs 127 out of 130 97%
Number of PS7s 1 out of 1 100%
Number of Slices 938 out of 4400 21%
Number of Slice Registers 2373 out of 35200 6%
Number used as Flip Flops 2117
Number used as Latches 256
Number used as LatchThrus 0
Number of Slice LUTS 2146 out of 17600 12%
Number of Slice LUT-Flip Flop pairs 2994 out of 17600 17%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 15 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1 : 13725 unrouted; REAL time: 16 secs
Phase 2 : 10227 unrouted; REAL time: 16 secs
Phase 3 : 3457 unrouted; REAL time: 20 secs
Phase 4 : 3457 unrouted; (Setup:0, Hold:13564, Component Switching Limit:0) REAL time: 21 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Total REAL time to Router completion: 26 secs
Total CPU time to Router completion: 26 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|processing_system7_0 | | | | | |
| _FCLK_CLK0 | BUFGCTRL_X0Y0| No | 611 | 0.133 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_0/pwm_signal_ | | | | | |
|out_wkillswitch_0/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y31| No | 16 | 0.022 | 1.657 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_1/pwm_signal_ | | | | | |
|out_wkillswitch_1/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y30| No | 16 | 0.018 | 1.667 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_3/pwm_signal_ | | | | | |
|out_wkillswitch_3/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y1| No | 16 | 0.018 | 1.665 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_2/pwm_signal_ | | | | | |
|out_wkillswitch_2/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y2| No | 16 | 0.012 | 1.670 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP | 0.453ns| 9.547ns| 0| 0
0" 100 MHz HIGH 50% | HOLD | 0.018ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_axi_interconnect_1_reset_resync_ | SETUP | N/A| 1.100ns| N/A| 0
path" TIG | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 27 secs
Total CPU time to PAR completion: 27 secs
Peak Memory Usage: 961 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -e 3 -xml system.twx
system.ncd system.pcf
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc7z010,-1 (PRODUCTION 1.08 2013-10-13)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in
the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of
this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 71514 paths, 0 nets, and 9934 connections
Design statistics:
Minimum period: 9.547ns (Maximum frequency: 104.745MHz)
Analysis completed Wed Oct 14 20:11:43 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 4
Total time: 15 secs
xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************
cd implementation ; bitgen -w -f bitgen.ut system ; cd ..
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
Opened constraints file system.pcf.
Wed Oct 14 20:11:55 2015
Running DRC.
DRC detected 0 errors and 0 warnings.
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Assigned Driver tmrctr 2.05.a for instance axi_timer_0
axi_timer_0 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_timer, INSTANCE: axi_timer_0, PARAMETER: C_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.
ERROR:EDK:4125 - IPNAME: axi_timer, INSTANCE: axi_timer_0, PARAMETER: C_HIGHADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.
WARNING:EDK:2137 - Peripheral axi_timer_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_timer_0
********************************************************************************
At Local date and time: Wed Dec 30 20:33:54 2015
make -f system.make hwclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
rm -rf __xps/ps7_instance.mhs
Done!
********************************************************************************
At Local date and time: Wed Dec 30 20:33:59 2015
make -f system.make netlistclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
Done!
********************************************************************************
At Local date and time: Wed Dec 30 20:34:03 2015
make -f system.make bitsclean started...
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
Done!
********************************************************************************
At Local date and time: Wed Dec 30 20:34:29 2015
make -f system.make exporttosdk started...
pscgen -mhs system.mhs -expdir SDK/SDK_Export/hw
Generating ps7_init code for Si version 1....
Generating ps7_init code for Si version 2....
Generating ps7_init code for Si version 3....
psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK/SDK_Export/hw/system.xml
Release 14.7 - psf2Edward EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000f281 is greater than
32
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0