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PARAMETER VERSION = 2.1.0
PORT CLK_N = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000, DIFFERENTIAL_POLARITY = N
PORT CLK_P = CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000, DIFFERENTIAL_POLARITY = P
PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
PORT pwm_recorder_0_pwm_in_master_pin = pwm_recorder_0_pwm_in_master, DIR = I
PORT pwm_recorder_1_pwm_in_master_pin = pwm_recorder_1_pwm_in_master, DIR = I
PORT pwm_recorder_2_pwm_in_master_pin = pwm_recorder_2_pwm_in_master, DIR = I
PORT pwm_recorder_3_pwm_in_master_pin = pwm_recorder_3_pwm_in_master, DIR = I
PORT pwm_recorder_4_pwm_in_master_pin = pwm_recorder_4_pwm_in_master, DIR = I
PORT pwm_recorder_5_pwm_in_master_pin = pwm_recorder_5_pwm_in_master, DIR = I
PORT BTNs_4Bits_TRI_IO_GPIO_IO_I_pin = BTNs_4Bits_TRI_IO_GPIO_IO_I, DIR = I, VEC = [3:0]
PORT processing_system7_0_UART0_TX_pin = processing_system7_0_UART0_TX, DIR = O
PORT processing_system7_0_UART0_RX_pin = processing_system7_0_UART0_RX, DIR = I
PORT pwm_signal_out_wkillswitch_0_pwm_out_sm_pin = pwm_signal_out_wkillswitch_0_pwm_out_sm, DIR = O
PORT pwm_signal_out_wkillswitch_1_pwm_out_sm_pin = pwm_signal_out_wkillswitch_1_pwm_out_sm, DIR = O
PORT pwm_signal_out_wkillswitch_2_pwm_out_sm_pin = pwm_signal_out_wkillswitch_2_pwm_out_sm, DIR = O
PORT pwm_signal_out_wkillswitch_3_pwm_out_sm_pin = pwm_signal_out_wkillswitch_3_pwm_out_sm, DIR = O
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PORT CLKIN = CLK
PORT LOCKED = clock_generator_0_LOCKED_0
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_0
PARAMETER HW_VER = 3.00.a
PORT Dcm_locked = clock_generator_0_LOCKED_0
END
BEGIN processing_system7
PARAMETER INSTANCE = processing_system7_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
PARAMETER C_EN_EMIO_CAN0 = 0
PARAMETER C_EN_EMIO_CAN1 = 0
PARAMETER C_EN_EMIO_ENET0 = 0
PARAMETER C_EN_EMIO_ENET1 = 0
PARAMETER C_EN_EMIO_I2C0 = 0
PARAMETER C_EN_EMIO_I2C1 = 0
PARAMETER C_EN_EMIO_PJTAG = 0
PARAMETER C_EN_EMIO_SDIO0 = 0
PARAMETER C_EN_EMIO_CD_SDIO0 = 0
PARAMETER C_EN_EMIO_WP_SDIO0 = 1
PARAMETER C_EN_EMIO_SDIO1 = 0
PARAMETER C_EN_EMIO_CD_SDIO1 = 0
PARAMETER C_EN_EMIO_WP_SDIO1 = 0
PARAMETER C_EN_EMIO_SPI0 = 0
PARAMETER C_EN_EMIO_SPI1 = 0
PARAMETER C_EN_EMIO_SRAM_INT = 0
PARAMETER C_EN_EMIO_TRACE = 0
PARAMETER C_EN_EMIO_TTC0 = 0
PARAMETER C_EN_EMIO_TTC1 = 0
PARAMETER C_EN_EMIO_UART0 = 1
PARAMETER C_EN_EMIO_UART1 = 0
PARAMETER C_EN_EMIO_MODEM_UART0 = 0
PARAMETER C_EN_EMIO_MODEM_UART1 = 0
PARAMETER C_EN_EMIO_WDT = 0
PARAMETER C_EN_EMIO_GPIO = 0
PARAMETER C_EMIO_GPIO_WIDTH = 64
PARAMETER C_EN_QSPI = 1
PARAMETER C_EN_SMC = 0
PARAMETER C_EN_CAN0 = 0
PARAMETER C_EN_CAN1 = 0
PARAMETER C_EN_ENET0 = 1
PARAMETER C_EN_ENET1 = 0
PARAMETER C_EN_I2C0 = 1
PARAMETER C_EN_I2C1 = 0
PARAMETER C_EN_PJTAG = 0
PARAMETER C_EN_SDIO0 = 1
PARAMETER C_EN_SDIO1 = 0
PARAMETER C_EN_SPI0 = 0
PARAMETER C_EN_SPI1 = 0
PARAMETER C_EN_TRACE = 0
PARAMETER C_EN_TTC0 = 0
PARAMETER C_EN_TTC1 = 0
PARAMETER C_EN_UART0 = 1
PARAMETER C_EN_UART1 = 1
PARAMETER C_EN_MODEM_UART0 = 0
PARAMETER C_EN_MODEM_UART1 = 0
PARAMETER C_EN_USB0 = 1
PARAMETER C_EN_USB1 = 0
PARAMETER C_EN_WDT = 0
PARAMETER C_EN_DDR = 1
PARAMETER C_EN_GPIO = 1
PARAMETER C_FCLK_CLK0_FREQ = 100000000
PARAMETER C_FCLK_CLK1_FREQ = 175000000
PARAMETER C_FCLK_CLK2_FREQ = 12264151
PARAMETER C_FCLK_CLK3_FREQ = 100000000
PARAMETER C_USE_CR_FABRIC = 1
PARAMETER C_USE_M_AXI_GP0 = 1
BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
PORT MIO = processing_system7_0_MIO
PORT PS_SRSTB = processing_system7_0_PS_SRSTB
PORT PS_CLK = processing_system7_0_PS_CLK
PORT PS_PORB = processing_system7_0_PS_PORB
PORT DDR_Clk = processing_system7_0_DDR_Clk
PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
PORT DDR_CKE = processing_system7_0_DDR_CKE
PORT DDR_CS_n = processing_system7_0_DDR_CS_n
PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
PORT DDR_WEB = processing_system7_0_DDR_WEB
PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
PORT DDR_Addr = processing_system7_0_DDR_Addr
PORT DDR_ODT = processing_system7_0_DDR_ODT
PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
PORT DDR_DQ = processing_system7_0_DDR_DQ
PORT DDR_DM = processing_system7_0_DDR_DM
PORT DDR_DQS = processing_system7_0_DDR_DQS
PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
PORT DDR_VRN = processing_system7_0_DDR_VRN
PORT DDR_VRP = processing_system7_0_DDR_VRP
PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
PORT UART0_TX = processing_system7_0_UART0_TX
PORT UART0_RX = processing_system7_0_UART0_RX
END
BEGIN pwm_recorder
PARAMETER INSTANCE = pwm_recorder_0
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x76ea0000
PARAMETER C_HIGHADDR = 0x76eaffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_in_master = pwm_recorder_0_pwm_in_master
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_1
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END
BEGIN pwm_recorder
PARAMETER INSTANCE = pwm_recorder_1
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x76e80000
PARAMETER C_HIGHADDR = 0x76e8ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_in_master = pwm_recorder_1_pwm_in_master
END
BEGIN pwm_recorder
PARAMETER INSTANCE = pwm_recorder_2
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x76e60000
PARAMETER C_HIGHADDR = 0x76e6ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_in_master = pwm_recorder_2_pwm_in_master
END
BEGIN pwm_recorder
PARAMETER INSTANCE = pwm_recorder_3
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x76e40000
PARAMETER C_HIGHADDR = 0x76e4ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_in_master = pwm_recorder_3_pwm_in_master
END
BEGIN pwm_recorder
PARAMETER INSTANCE = pwm_recorder_4
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x76e20000
PARAMETER C_HIGHADDR = 0x76e2ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_in_master = pwm_recorder_4_pwm_in_master
END
BEGIN pwm_recorder
PARAMETER INSTANCE = pwm_recorder_5
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x76e00000
PARAMETER C_HIGHADDR = 0x76e0ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_in_master = pwm_recorder_5_pwm_in_master
END
BEGIN axi_gpio
PARAMETER INSTANCE = BTNs_4Bits_TRI_IO
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT GPIO_IO_I = BTNs_4Bits_TRI_IO_GPIO_IO_I
END
BEGIN pwm_signal_out_wkillswitch
PARAMETER INSTANCE = pwm_signal_out_wkillswitch_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x79460000
PARAMETER C_HIGHADDR = 0x7946ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_out_sm = pwm_signal_out_wkillswitch_0_pwm_out_sm
END
BEGIN pwm_signal_out_wkillswitch
PARAMETER INSTANCE = pwm_signal_out_wkillswitch_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x79440000
PARAMETER C_HIGHADDR = 0x7944ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_out_sm = pwm_signal_out_wkillswitch_1_pwm_out_sm
END
BEGIN pwm_signal_out_wkillswitch
PARAMETER INSTANCE = pwm_signal_out_wkillswitch_2
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x79420000
PARAMETER C_HIGHADDR = 0x7942ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_out_sm = pwm_signal_out_wkillswitch_2_pwm_out_sm
END
BEGIN pwm_signal_out_wkillswitch
PARAMETER INSTANCE = pwm_signal_out_wkillswitch_3
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x79400000
PARAMETER C_HIGHADDR = 0x7940ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT pwm_out_sm = pwm_signal_out_wkillswitch_3_pwm_out_sm
END
BEGIN axi_timer
PARAMETER INSTANCE = axi_timer_0
PARAMETER HW_VER = 1.03.a
PARAMETER C_BASEADDR = 0x42800000
PARAMETER C_HIGHADDR = 0x4280ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
END