@@ -8,5 +8,22 @@ In this setup, the clock is started using an MCLK pin on the MSP430 to output th
The direction of data transfer is configured using the read-write line. If the read/write line is low when the SS pin goes low, then a read is occurring from the master's perspective (MISO, out from the FPGA). If the read/write line is high, then a write is occuring (MOSI, into the FPGA). The request-to-send line is purely for an indication or interrupt back to the MSP430 from the FPGA.
## Timing Explanations
The clock domain crossing was created custom for this component in order to
### fast2slow.vhd
The clock domain crossing was created custom for this component in order to match the DMA timing correctly. There are two separate modules for crossing the clock domain in each of the two directions: Fast to slow (FPGA to MSP430) or slow to fast (MSP430 to FPGA). These are clocked on 4MHz output from the spi logic component which divided and delayed the clock appropriately to account for the starting delay in the DMA transaction.
### Fast to slow
This assumes the fast clock is >2x the slow clock (at least 8MHz for the FPGA clock).
This module has two separate access patterns, it provides a fast enable line which will go high at the start of the FPGA clock cycle in which DIN will be latched, and DIN will be latched at the end of that clock cycle. It also provides an ack signal which will go high in the cycle following the DIN being latched. If the data to be sent is being calculated on-the-fly, FEN will be more useful as it can enable any computations, then latch the data at the end of the clock cycle. However, if the data is sitting in a buffer ready to be sent, an ack will be more useful as you can load the next byte of data during the ack for the previous byte.
The input data will be latched on the first fast rising edge where the slow clock is high. Since the DMA latches data on the rising edge of the slow clock, so long as we have two fast periods within one slow clock period, we are guaranteed to latch data before the DMA latches it.
### Slow to fast
This also assumes the fast clock is >3x the slow clock (at least 12MHz for the FPGA clock).
When data is available and known to be stable in DOUT, VALID will go high for exactly one fast cycle to allow the FPGA logic to save or use that data before it becomes unstable again.
The DMA latches data out on each falling edge of the slow clock.
The slow clock is sampled on each rising edge of the fast clock. When the slow clock is sampled as low, we will wait for one more fast clock cycle to ensure the data is stable, then declare the data is valid for one fast clock cycle. At that point, we are now between 2 and 3 fast clock cycles from the falling edge of the slow clock. We now wait until the slow clock is high and reset for the next byte. We need three fast clock cycles between DMA latches to ensure the data is stable while the other components on the FPGA read it during the valid fast cycle.
