The octospi module manages an 8-data-wire bidirectional SPI channel. It uses 8 data lines which are driven by either the master or slave depending on the direction of data flow, one clock line driven by the master, one active-low slave select line which indicates a valid transmission is starting, one request-to-send line driven by the slave when data is available to be sent back to the master, and one read/write line driven by the master to indicate direction of data. The read/write line could potentially be combined with the request-to-send line in a future revision.
This protocol is designed around the DMA on the MSP430, so all timing information is based on experimental data testing with the DMA. The DMA copies data at 1/2 of the clock frequency of the CPU and AHB bus and freezes the CPU while a copy is in progress. The DMA is significantly faster than the CPU, taking two cycles per transfer beat as opposed to the minimum of 5 cycles required to perform a CPU transfer. In this setup, the DMA is clocked at 8MHz (the maximum access speed of the FRAM without wait states), and outputs data at 4MHz on every other 8MHz clock cycle. For ease of timing later, we output the 8MHz clock as the octospi clock and effectively ignore every other edge. This could be improved to use a 4MHz clock in the future, but care would have to be taken that the phase matches the DMA transfer in all cases. I did not see an easy way to guarantee the phase of the 4MHz signal matches the phase of the DMA data transfer.
In this setup, the clock is started using an MCLK pin on the MSP430 to output the 8MHz system clock. the SS pin is driven low, then the DMA transfer begins. There is a delay of several clock periods before the DMA is configured and begins to send, but because the number of instructions between the SS pin being driven low and the DMA transfer configuration being written is constant, the pre-data number of clock cycles can be accounted for and ignored on the FPGA. For this reason, don't reorganize the code in the SPI send and receive functions on the MSP430.
The direction of data transfer is configured using the read-write line. If the read/write line is low when the SS pin goes low, then a read is occurring from the master's perspective (MISO, out from the FPGA). If the read/write line is high, then a write is occuring (MOSI, into the FPGA). The request-to-send line is purely for an indication or interrupt back to the MSP430 from the FPGA.
## Timing Explanations
The clock domain crossing was created custom for this component in order to
