From fa6a3465a2e19defd7acaad3c3a17dfb4cd82a5b Mon Sep 17 00:00:00 2001
From: "ucart@co3050-12" <dawehr@iastate.edu>
Date: Sat, 22 Apr 2017 01:17:57 -0500
Subject: [PATCH] Flying, not testing. Some BSP shuffling.
---
quad/xsdk_workspace/.gitignore | 5 +-
quad/xsdk_workspace/real_quad/src/main.c | 6 +-
quad/xsdk_workspace/system_bsp/.cproject | 4 +-
quad/xsdk_workspace/system_bsp/system.mss | 4 +-
quad/xsdk_workspace/zybo_fsbl/.cproject | 138 +-
quad/xsdk_workspace/zybo_fsbl/.gitignore | 5 -
quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c | 180 +-
.../zybo_fsbl/src/ps7_init.html | 8860 -----------------
.../xsdk_workspace/zybo_fsbl/src/ps7_init.tcl | 762 --
quad/xsdk_workspace/zybo_fsbl_bsp/.cproject | 4 +-
quad/xsdk_workspace/zybo_fsbl_bsp/.project | 2 +-
.../zybo_fsbl_bsp/libgen.options | 2 +-
quad/xsdk_workspace/zybo_fsbl_bsp/system.mss | 6 +
13 files changed, 180 insertions(+), 9798 deletions(-)
delete mode 100644 quad/xsdk_workspace/zybo_fsbl/.gitignore
delete mode 100644 quad/xsdk_workspace/zybo_fsbl/src/ps7_init.html
delete mode 100644 quad/xsdk_workspace/zybo_fsbl/src/ps7_init.tcl
diff --git a/quad/xsdk_workspace/.gitignore b/quad/xsdk_workspace/.gitignore
index 0deb2c3cf..ca597b529 100644
--- a/quad/xsdk_workspace/.gitignore
+++ b/quad/xsdk_workspace/.gitignore
@@ -5,4 +5,7 @@ system_bsp/ps7_cortexa9_0/
system_bsp/libgen.log
zybo_fsbl_bsp/ps7_cortexa9_0/
zybo_fsbl_bsp/libgen.log
-TAGS
\ No newline at end of file
+zybo_fsbl/Release
+zybo_fsbl/Debug
+zybo_fsbl/bootimage
+TAGS
diff --git a/quad/xsdk_workspace/real_quad/src/main.c b/quad/xsdk_workspace/real_quad/src/main.c
index f2562cb6f..6ae2ffb1c 100644
--- a/quad/xsdk_workspace/real_quad/src/main.c
+++ b/quad/xsdk_workspace/real_quad/src/main.c
@@ -4,7 +4,7 @@
#include "type_def.h"
#include "platform.h"
-#define RUN_TESTS
+//#define RUN_TESTS
int setup_hardware(hardware_t *hardware) {
hardware->rc_receiver = create_zybo_rc_receiver();
@@ -33,9 +33,9 @@ int main()
//test_zybo_i2c_imu();
//test_zybo_i2c_px4flow();
//test_zybo_i2c_lidar();
- test_zybo_i2c_all();
+ //test_zybo_i2c_all();
//test_zybo_rc_receiver();
- //test_zybo_motors();
+ test_zybo_motors();
//test_zybo_uart();
//test_zybo_axi_timer();
//test_zybo_uart();
diff --git a/quad/xsdk_workspace/system_bsp/.cproject b/quad/xsdk_workspace/system_bsp/.cproject
index 16d2fd27b..58ab3351c 100644
--- a/quad/xsdk_workspace/system_bsp/.cproject
+++ b/quad/xsdk_workspace/system_bsp/.cproject
@@ -3,8 +3,8 @@
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.2078347332">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.2078347332" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+ <cconfiguration id="org.eclipse.cdt.core.default.config.946402869">
+ <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.946402869" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
diff --git a/quad/xsdk_workspace/system_bsp/system.mss b/quad/xsdk_workspace/system_bsp/system.mss
index 901e54a47..2c47ed63f 100644
--- a/quad/xsdk_workspace/system_bsp/system.mss
+++ b/quad/xsdk_workspace/system_bsp/system.mss
@@ -6,8 +6,8 @@ BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 3.11.a
PARAMETER PROC_INSTANCE = ps7_cortexa9_0
- PARAMETER STDIN = ps7_uart_0
- PARAMETER STDOUT = ps7_uart_0
+ PARAMETER STDIN = ps7_uart_1
+ PARAMETER STDOUT = ps7_uart_1
END
diff --git a/quad/xsdk_workspace/zybo_fsbl/.cproject b/quad/xsdk_workspace/zybo_fsbl/.cproject
index 8047c6042..7ddad3fcb 100644
--- a/quad/xsdk_workspace/zybo_fsbl/.cproject
+++ b/quad/xsdk_workspace/zybo_fsbl/.cproject
@@ -3,8 +3,8 @@
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="xilinx.gnu.arm.exe.debug.563267343">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.563267343" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <cconfiguration id="xilinx.gnu.arm.exe.debug.1528513972">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.1528513972" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -16,68 +16,68 @@
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.563267343" name="Debug" parent="xilinx.gnu.arm.exe.debug">
- <folderInfo id="xilinx.gnu.arm.exe.debug.563267343." name="/" resourcePath="">
- <toolChain id="xilinx.gnu.arm.exe.debug.toolchain.1310213535" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.debug.toolchain">
- <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.920830407" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
- <builder buildPath="${workspace_loc:/zybo_fsbl}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.debug.454763412" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.arm.toolchain.builder.debug"/>
- <tool id="xilinx.gnu.arm.c.toolchain.assembler.debug.1540227256" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.debug">
- <inputType id="xilinx.gnu.assembler.input.13485298" superClass="xilinx.gnu.assembler.input"/>
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.1528513972" name="Debug" parent="xilinx.gnu.arm.exe.debug">
+ <folderInfo id="xilinx.gnu.arm.exe.debug.1528513972." name="/" resourcePath="">
+ <toolChain id="xilinx.gnu.arm.exe.debug.toolchain.620865263" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.debug.toolchain">
+ <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.1299613950" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
+ <builder buildPath="${workspace_loc:/zybo_fsbl}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.debug.1331514252" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.arm.toolchain.builder.debug"/>
+ <tool id="xilinx.gnu.arm.c.toolchain.assembler.debug.911778202" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.debug">
+ <inputType id="xilinx.gnu.assembler.input.2001882527" superClass="xilinx.gnu.assembler.input"/>
</tool>
- <tool id="xilinx.gnu.arm.c.toolchain.compiler.debug.457673602" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.debug">
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- <option id="xilinx.gnu.compiler.option.debugging.level.1888303961" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.780971215" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
+ <tool id="xilinx.gnu.arm.c.toolchain.compiler.debug.1840889584" name="ARM gcc compiler" superClass="xilinx.gnu.arm.c.toolchain.compiler.debug">
+ <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.2110622919" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.option.debugging.level.1324950494" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1010106927" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/include"/>
</option>
- <inputType id="xilinx.gnu.arm.c.compiler.input.940838417" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
+ <inputType id="xilinx.gnu.arm.c.compiler.input.164824730" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.debug.1067895073" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.208739742" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.option.debugging.level.623682590" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
- <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1087976457" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
+ <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.debug.247997005" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.debug">
+ <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1779591449" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.option.debugging.level.1320442366" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option id="xilinx.gnu.compiler.inferred.swplatform.includes.1122443388" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/include"/>
</option>
</tool>
- <tool id="xilinx.gnu.arm.toolchain.archiver.1485154551" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
- <tool id="xilinx.gnu.arm.c.toolchain.linker.debug.694524981" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.555585521" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.arm.toolchain.archiver.1400731677" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
+ <tool id="xilinx.gnu.arm.c.toolchain.linker.debug.345997425" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.debug">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1716168836" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.325777166" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1873644137" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
- <option id="xilinx.gnu.c.linker.option.lscript.704335692" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
- <option id="xilinx.gnu.c.link.option.libs.828267603" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
+ <option id="xilinx.gnu.c.linker.option.lscript.1950983133" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.link.option.libs.598950432" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
<listOptionValue builtIn="false" value="rsa"/>
</option>
- <option id="xilinx.gnu.c.link.option.paths.2031068232" superClass="xilinx.gnu.c.link.option.paths" valueType="libPaths">
+ <option id="xilinx.gnu.c.link.option.paths.58794466" superClass="xilinx.gnu.c.link.option.paths" valueType="libPaths">
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
</option>
- <inputType id="xilinx.gnu.linker.input.1097085627" superClass="xilinx.gnu.linker.input">
+ <inputType id="xilinx.gnu.linker.input.103080881" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.1428414389" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
+ <inputType id="xilinx.gnu.linker.input.lscript.428167088" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
- <tool id="xilinx.gnu.arm.cxx.toolchain.linker.debug.1114403279" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.debug">
- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.721160155" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
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+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1863640969" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.2127848659" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.2096513062" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
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- <option id="xilinx.gnu.c.linker.option.lscript.1094205127" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.linker.option.lscript.1103422420" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
- <tool id="xilinx.gnu.arm.size.debug.140413066" name="ARM Print Size" superClass="xilinx.gnu.arm.size.debug"/>
+ <tool id="xilinx.gnu.arm.size.debug.2048630709" name="ARM Print Size" superClass="xilinx.gnu.arm.size.debug"/>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
- <cconfiguration id="xilinx.gnu.arm.exe.release.876704639">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.release.876704639" moduleId="org.eclipse.cdt.core.settings" name="Release">
+ <cconfiguration id="xilinx.gnu.arm.exe.release.819164381">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.release.819164381" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -89,60 +89,60 @@
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.release.876704639" name="Release" parent="xilinx.gnu.arm.exe.release">
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- <builder buildPath="${workspace_loc:/zybo_fsbl}/Release" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.release.1683299044" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.arm.toolchain.builder.release"/>
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- <inputType id="xilinx.gnu.assembler.input.1832895311" superClass="xilinx.gnu.assembler.input"/>
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.release.819164381" name="Release" parent="xilinx.gnu.arm.exe.release">
+ <folderInfo id="xilinx.gnu.arm.exe.release.819164381." name="/" resourcePath="">
+ <toolChain id="xilinx.gnu.arm.exe.release.toolchain.1240523721" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.release.toolchain">
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+ <builder buildPath="${workspace_loc:/zybo_fsbl}/Release" enableAutoBuild="true" id="xilinx.gnu.arm.toolchain.builder.release.220781107" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.arm.toolchain.builder.release"/>
+ <tool id="xilinx.gnu.arm.c.toolchain.assembler.release.1719774153" name="ARM gcc assembler" superClass="xilinx.gnu.arm.c.toolchain.assembler.release">
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+ <tool id="xilinx.gnu.arm.cxx.toolchain.compiler.release.891744552" name="ARM g++ compiler" superClass="xilinx.gnu.arm.cxx.toolchain.compiler.release">
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</option>
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- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.2100658751" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.arm.toolchain.archiver.1118360987" name="ARM archiver" superClass="xilinx.gnu.arm.toolchain.archiver"/>
+ <tool id="xilinx.gnu.arm.c.toolchain.linker.release.1132751753" name="ARM gcc linker" superClass="xilinx.gnu.arm.c.toolchain.linker.release">
+ <option id="xilinx.gnu.linker.inferred.swplatform.lpath.1917836743" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.332840161" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.383672501" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
</option>
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- <option id="xilinx.gnu.c.link.option.libs.1570584843" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
+ <option id="xilinx.gnu.c.linker.option.lscript.1608063800" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.link.option.libs.1281241736" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
<listOptionValue builtIn="false" value="rsa"/>
</option>
- <option id="xilinx.gnu.c.link.option.paths.304586361" superClass="xilinx.gnu.c.link.option.paths" valueType="libPaths">
+ <option id="xilinx.gnu.c.link.option.paths.40091586" superClass="xilinx.gnu.c.link.option.paths" valueType="libPaths">
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
</option>
- <inputType id="xilinx.gnu.linker.input.568924798" superClass="xilinx.gnu.linker.input">
+ <inputType id="xilinx.gnu.linker.input.926037696" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
- <inputType id="xilinx.gnu.linker.input.lscript.78755099" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
+ <inputType id="xilinx.gnu.linker.input.lscript.1292679303" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
</tool>
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- <option id="xilinx.gnu.linker.inferred.swplatform.lpath.745005125" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
+ <tool id="xilinx.gnu.arm.cxx.toolchain.linker.release.823586348" name="ARM g++ linker" superClass="xilinx.gnu.arm.cxx.toolchain.linker.release">
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<listOptionValue builtIn="false" value="../../zybo_fsbl_bsp/ps7_cortexa9_0/lib"/>
</option>
- <option id="xilinx.gnu.linker.inferred.swplatform.flags.1911791627" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
+ <option id="xilinx.gnu.linker.inferred.swplatform.flags.1228570640" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
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- <option id="xilinx.gnu.c.linker.option.lscript.1735659922" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+ <option id="xilinx.gnu.c.linker.option.lscript.1403296691" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
</tool>
- <tool id="xilinx.gnu.arm.size.release.1178224723" name="ARM Print Size" superClass="xilinx.gnu.arm.size.release"/>
+ <tool id="xilinx.gnu.arm.size.release.1130359049" name="ARM Print Size" superClass="xilinx.gnu.arm.size.release"/>
</toolChain>
</folderInfo>
</configuration>
@@ -152,20 +152,20 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="zybo_fsbl.xilinx.gnu.arm.exe.2046878906" name="Xilinx ARM Executable" projectType="xilinx.gnu.arm.exe"/>
+ <project id="zybo_fsbl.xilinx.gnu.arm.exe.36875234" name="Xilinx ARM Executable" projectType="xilinx.gnu.arm.exe"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.876704639;xilinx.gnu.arm.exe.release.876704639.;xilinx.gnu.arm.c.toolchain.compiler.release.791004764;xilinx.gnu.arm.c.compiler.input.1024044361">
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.1528513972;xilinx.gnu.arm.exe.debug.1528513972.;xilinx.gnu.arm.c.toolchain.compiler.debug.1840889584;xilinx.gnu.arm.c.compiler.input.164824730">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
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+ <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.819164381;xilinx.gnu.arm.exe.release.819164381.;xilinx.gnu.arm.c.toolchain.compiler.release.2059219877;xilinx.gnu.arm.c.compiler.input.1631463841">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.563267343;xilinx.gnu.arm.exe.debug.563267343.">
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.819164381;xilinx.gnu.arm.exe.release.819164381.">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
</scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.876704639;xilinx.gnu.arm.exe.release.876704639.">
+ <scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.debug.1528513972;xilinx.gnu.arm.exe.debug.1528513972.">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
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diff --git a/quad/xsdk_workspace/zybo_fsbl/.gitignore b/quad/xsdk_workspace/zybo_fsbl/.gitignore
deleted file mode 100644
index a92e1611d..000000000
--- a/quad/xsdk_workspace/zybo_fsbl/.gitignore
+++ /dev/null
@@ -1,5 +0,0 @@
-*.o
-*.d
-*.elf
-*.size
-bootimage/
\ No newline at end of file
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c b/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c
index 182b94b57..2c7ad97ad 100644
--- a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c
+++ b/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.c
@@ -2512,23 +2512,23 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000730[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF8000730[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
// .. Speed = 0
// .. ==> 0XF8000730[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000730[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000730[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000734[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -2541,23 +2541,23 @@ unsigned long ps7_mio_init_data_1_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000734[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF8000734[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
// .. Speed = 0
// .. ==> 0XF8000734[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000734[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000734[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000738[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -3767,16 +3767,16 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
- // .. BDIV = 0x5
- // .. ==> 0XE0001034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0001018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x00000009U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -3829,16 +3829,16 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x5
- // .. ==> 0XE0000034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
+ // .. BDIV = 0x6
+ // .. ==> 0XE0000034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0000018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0000018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x00000009U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0000000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -6769,23 +6769,23 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000730[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF8000730[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
// .. Speed = 0
// .. ==> 0XF8000730[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000730[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000730[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000734[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -6798,23 +6798,23 @@ unsigned long ps7_mio_init_data_2_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000734[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF8000734[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
// .. Speed = 0
// .. ==> 0XF8000734[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000734[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000734[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000738[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -8024,16 +8024,16 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
- // .. BDIV = 0x5
- // .. ==> 0XE0001034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0001018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x00000009U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -8086,16 +8086,16 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x5
- // .. ==> 0XE0000034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
+ // .. BDIV = 0x6
+ // .. ==> 0XE0000034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0000018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0000018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x00000009U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0000000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -10716,23 +10716,23 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000730[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF8000730[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
// .. Speed = 0
// .. ==> 0XF8000730[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000730[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000730[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000734[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -10745,23 +10745,23 @@ unsigned long ps7_mio_init_data_3_0[] = {
// .. L2_SEL = 0
// .. ==> 0XF8000734[4:3] = 0x00000000U
// .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF8000734[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
// .. Speed = 0
// .. ==> 0XF8000734[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
// .. IO_Type = 3
// .. ==> 0XF8000734[11:9] = 0x00000003U
// .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
// .. DisableRcvr = 0
// .. ==> 0XF8000734[13:13] = 0x00000000U
// .. ==> MASK : 0x00002000U VAL : 0x00000000U
// ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
// .. TRI_ENABLE = 0
// .. ==> 0XF8000738[0:0] = 0x00000000U
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
@@ -11971,16 +11971,16 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. START: SRAM/NOR SET OPMODE
// .. FINISH: SRAM/NOR SET OPMODE
// .. START: UART REGISTERS
- // .. BDIV = 0x5
- // .. ==> 0XE0001034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0001018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x00000009U),
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0001000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
@@ -12027,16 +12027,16 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
// .. ==> MASK : 0x00000001U VAL : 0x00000000U
// ..
EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. BDIV = 0x5
- // .. ==> 0XE0000034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
+ // .. BDIV = 0x6
+ // .. ==> 0XE0000034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
// ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0000018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0000018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
// ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x00000009U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
// .. STPBRK = 0x0
// .. ==> 0XE0000000[8:8] = 0x00000000U
// .. ==> MASK : 0x00000100U VAL : 0x00000000U
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.html b/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.html
deleted file mode 100644
index e6b1a8a0b..000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.html
+++ /dev/null
@@ -1,8860 +0,0 @@
-<!DOCTYPE html>
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8"/>
-<title>Zynq PS configuration detail</title>
-<style type="text/css">
-.hex {font-family:monospace ; text-align : right}
-td { min-width : 80px ; }
-</style>
-</head>
-<body>
-<p style="height: 7px">Following peripherals are selected in the design. </p>
-<p><br /></p>
-<h2><a name="Top">Peripheral Selected</a></h2>
-<ul>
-<li>Quad SPI Flash</li>
-<li>Enet 0</li>
-<li>USB 0</li>
-<li>SD 0</li>
-<li>UART 0</li>
-<li>UART 1</li>
-<li>I2C 0</li>
-<li>I2C 1</li>
-<li>GPIO</li>
-</ul>
-<p>To see detailed information please follow below links:</p>
-<ul>
-<li><a href="#MIOConfTab">MIO Configuration Table</a></li>
-<li><a href="#ZynqPerTab">Zynq Peripheral Configuration</a></li>
-<li><a href="#DDRInfoTab">DDR Configuration Information</a></li>
-<li>SLCR settings</li>
-<ul>
-<li><a href="#ps7_pll_init_data">PLL Init Data</a></li>
-<li><a href="#ps7_clock_init_data">Clock Init Data</a></li>
-<li><a href="#ps7_ddr_init_data">DDR Init Data</a></li>
-<li><a href="#ps7_mio_init_data">MIO Init Data</a></li>
-</ul>
-</ul>
-<h2><a name="MIOConfTab">MIO configuration Table</a></h2>
-<ul><table border="1">
-<thead><tr> <th>MIO Pin</th> <th>Peripheral</th> <th>Signal</th> <th>IO type</th> <th>Speed</th> <th>Pullup</th> <th>Direction</th> </tr></thead>
-<tr bgcolor="#FA4A46"><td><a name="MIO 0">MIO 0</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[0]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 1">MIO 1</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_ss_b</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 2">MIO 2</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[0]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 3">MIO 3</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[1]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 4">MIO 4</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[2]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 5">MIO 5</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[3]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 6">MIO 6</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_sclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 7">MIO 7</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[7]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 8">MIO 8</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi_fbclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 9">MIO 9</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[9]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 10">MIO 10</a></td><td><a href="#I2C 0">I2C 0</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 11">MIO 11</a></td><td><a href="#I2C 0">I2C 0</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 12">MIO 12</a></td><td><a href="#I2C 1">I2C 1</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 13">MIO 13</a></td><td><a href="#I2C 1">I2C 1</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 14">MIO 14</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[14]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 15">MIO 15</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[15]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 16">MIO 16</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 17">MIO 17</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 18">MIO 18</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 19">MIO 19</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 20">MIO 20</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 21">MIO 21</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 22">MIO 22</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 23">MIO 23</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 24">MIO 24</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 25">MIO 25</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 26">MIO 26</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 27">MIO 27</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 28">MIO 28</a></td><td><a href="#USB 0">USB 0</a></td><td>data[4]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 29">MIO 29</a></td><td><a href="#USB 0">USB 0</a></td><td>dir</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 30">MIO 30</a></td><td><a href="#USB 0">USB 0</a></td><td>stp</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 31">MIO 31</a></td><td><a href="#USB 0">USB 0</a></td><td>nxt</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 32">MIO 32</a></td><td><a href="#USB 0">USB 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 33">MIO 33</a></td><td><a href="#USB 0">USB 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 34">MIO 34</a></td><td><a href="#USB 0">USB 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 35">MIO 35</a></td><td><a href="#USB 0">USB 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 36">MIO 36</a></td><td><a href="#USB 0">USB 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 37">MIO 37</a></td><td><a href="#USB 0">USB 0</a></td><td>data[5]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 38">MIO 38</a></td><td><a href="#USB 0">USB 0</a></td><td>data[6]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 39">MIO 39</a></td><td><a href="#USB 0">USB 0</a></td><td>data[7]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 40">MIO 40</a></td><td><a href="#SD 0">SD 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 41">MIO 41</a></td><td><a href="#SD 0">SD 0</a></td><td>cmd</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 42">MIO 42</a></td><td><a href="#SD 0">SD 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 43">MIO 43</a></td><td><a href="#SD 0">SD 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 44">MIO 44</a></td><td><a href="#SD 0">SD 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 45">MIO 45</a></td><td><a href="#SD 0">SD 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 46">MIO 46</a></td><td><a href="#USB 0">USB 0</a></td><td>reset</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 47">MIO 47</a></td><td><a href="#SD 0">SD 0</a></td><td>cd</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 48">MIO 48</a></td><td><a href="#UART 1">UART 1</a></td><td>tx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 49">MIO 49</a></td><td><a href="#UART 1">UART 1</a></td><td>rx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 50">MIO 50</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[50]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 51">MIO 51</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[51]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 52">MIO 52</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdc</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 53">MIO 53</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdio</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="ZynqPerTab">Zynq Peripheral Configuration</a></h2>
-<ul><table border="1">
-<tr><thead> <th>Peripheral</th> <th>Signal Group</th> <th>Signal</th> <th>MIO</th> </thead></tr>
-<tr bgcolor="#FAEBD7"><td><a name="Quad SPI Flash" >Quad SPI Flash</a></td> <td></td><td></td><td>MIO 1 .. 6</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (4 bit) </td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (Parallel 8 bit)</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Feedback Clk</td><td></td><td>MIO 8</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="nor" >SRAM/NOR Flash</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFE4C4"><td><a name="nand" >NAND Flash</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DEB887"><td><a name="Enet 0" >Enet 0</a></td> <td></td><td></td><td>MIO 16 .. 27</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_clk</td><td><a href="#MIO 16">MIO 16</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[3]</td><td><a href="#MIO 20">MIO 20</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[2]</td><td><a href="#MIO 19">MIO 19</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[1]</td><td><a href="#MIO 18">MIO 18</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[0]</td><td><a href="#MIO 17">MIO 17</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_ctl</td><td><a href="#MIO 21">MIO 21</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_clk</td><td><a href="#MIO 22">MIO 22</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[3]</td><td><a href="#MIO 26">MIO 26</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[2]</td><td><a href="#MIO 25">MIO 25</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[1]</td><td><a href="#MIO 24">MIO 24</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[0]</td><td><a href="#MIO 23">MIO 23</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_ctl</td><td><a href="#MIO 27">MIO 27</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td>MDIO</td><td></td><td>MIO 52 .. 53</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdc</td><td><a href="#MIO 52">MIO 52</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdio</td><td><a href="#MIO 53">MIO 53</a></td></tr>
-<tr bgcolor="#DEB887"><td><a name="enet1" >Enet 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="USB 0" >USB 0</a></td> <td></td><td></td><td>MIO 28 .. 39</td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>clk</td><td><a href="#MIO 36">MIO 36</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>dir</td><td><a href="#MIO 29">MIO 29</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>stp</td><td><a href="#MIO 30">MIO 30</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>nxt</td><td><a href="#MIO 31">MIO 31</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[0]</td><td><a href="#MIO 32">MIO 32</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[1]</td><td><a href="#MIO 33">MIO 33</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[2]</td><td><a href="#MIO 34">MIO 34</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[3]</td><td><a href="#MIO 35">MIO 35</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[4]</td><td><a href="#MIO 28">MIO 28</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[5]</td><td><a href="#MIO 37">MIO 37</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[6]</td><td><a href="#MIO 38">MIO 38</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[7]</td><td><a href="#MIO 39">MIO 39</a></td></tr>
-<tr bgcolor="#7FFF00"><td><a name="usb1" >USB 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="SD 0" >SD 0</a></td> <td></td><td></td><td>MIO 40 .. 45</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>CD</td><td></td><td>MIO 47</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>WP</td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>Power</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="sd1" >SD 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 0" >UART 0</a></td> <td></td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 1" >UART 1</a></td> <td></td><td></td><td>MIO 48 .. 49</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td><a href="#MIO 49">MIO 49</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td><a href="#MIO 48">MIO 48</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem Signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 0" >I2C 0</a></td> <td></td><td></td><td>MIO 10 .. 11</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 10">MIO 10</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 11">MIO 11</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 1" >I2C 1</a></td> <td></td><td></td><td>MIO 12 .. 13</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 12">MIO 12</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 13">MIO 13</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi0" >SPI 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi1" >SPI 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can0" >CAN 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can1" >CAN 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#ADD8E6"><td><a name="trace" >Trace</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc0" >Timer 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc1" >Timer 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FF6347"><td><a name="wdt" >Watchdog</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#EE82EE"><td><a name="pjtag" >PJTAG</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="GPIO" >GPIO</a></td> <td></td><td></td><td>MIO</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="mode" >Mode</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="vcfg" >VCfg</a></td> <td></td><td></td><td>Disabled</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="DDRInfoTab">DDR Memory information</a></h2>
-<h3><a name="DDRInfoTab">DDR Controller Configuration</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="Enable DDR">Enable DDR</a></td><td>1</td></tr>
-<tr> <td><a name="Memory Type">Memory Type</a></td><td>DDR 3</td></tr>
-<tr> <td><a name="Memory Part">Memory Part</a></td><td>MT41K128M16 JT-125</td></tr>
-<tr> <td><a name="DRAM bus width">DRAM bus width</a></td><td>32 Bit</td></tr>
-<tr> <td><a name="ECC">ECC</a></td><td>Disabled</td></tr>
-<tr> <td><a name="BURST Length (lppdr only)">BURST Length (lppdr only)</a></td><td>8</td></tr>
-<tr> <td><a name="Internal Vref">Internal Vref</a></td><td>0</td></tr>
-<tr> <td><a name="Operating Frequency (MHz)">Operating Frequency (MHz)</a></td><td>525.000000</td></tr>
-<tr> <td><a name="HIGH temperature">HIGH temperature</a></td><td>Normal (0-85)</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Memory Part Configuration</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="DRAM IC bus width">DRAM IC bus width</a></td><td>16 Bits</td></tr>
-<tr> <td><a name="DRAM Device Capacity">DRAM Device Capacity</a></td><td>2048 MBits</td></tr>
-<tr> <td><a name="Speed Bin">Speed Bin</a></td><td>DDR3_1066F</td></tr>
-<tr> <td><a name="BANK Address Count">BANK Address Count</a></td><td>3</td></tr>
-<tr> <td><a name="ROW Address Count">ROW Address Count</a></td><td>14</td></tr>
-<tr> <td><a name="COLUMN Address Count">COLUMN Address Count</a></td><td>10</td></tr>
-<tr> <td><a name="CAS Latency">CAS Latency</a></td><td>7</td></tr>
-<tr> <td><a name="CAS Write Latency">CAS Write Latency</a></td><td>6</td></tr>
-<tr> <td><a name="RAS to CAS Delay">RAS to CAS Delay</a></td><td>7</td></tr>
-<tr> <td><a name="RECHARGE Time">RECHARGE Time</a></td><td>7</td></tr>
-<tr> <td><a name="tRC (ns )">tRC (ns )</a></td><td>48.75</td></tr>
-<tr> <td><a name="tRASmin ( ns )">tRASmin ( ns )</a></td><td>35.0</td></tr>
-<tr> <td><a name="tFAW">tFAW</a></td><td>40.0</td></tr>
-<tr> <td><a name="ADDITIVE Latency">ADDITIVE Latency</a></td><td>0</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Training/Board Details</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="Write levelling">Write levelling</a></td><td>1</td></tr>
-<tr> <td><a name="Read gate">Read gate</a></td><td>1</td></tr>
-<tr> <td><a name="Read data eye">Read data eye</a></td><td>1</td></tr>
-<tr> <td><a name="DQS to Clock delay [0] (ns)">DQS to Clock delay [0] (ns)</a></td><td>-0.073</td></tr>
-<tr> <td><a name="DQS to Clock delay [1] (ns)">DQS to Clock delay [1] (ns)</a></td><td>-0.034</td></tr>
-<tr> <td><a name="DQS to Clock delay [2] (ns)">DQS to Clock delay [2] (ns)</a></td><td>-0.03</td></tr>
-<tr> <td><a name="DQS to Clock delay [3] (ns)">DQS to Clock delay [3] (ns)</a></td><td>-0.082</td></tr>
-<tr> <td><a name="Board delay [0] (ns)">Board delay [0] (ns)</a></td><td>0.176</td></tr>
-<tr> <td><a name="Board delay [1] (ns)">Board delay [1] (ns)</a></td><td>0.159</td></tr>
-<tr> <td><a name="Board delay [2] (ns)">Board delay [2] (ns)</a></td><td>0.162</td></tr>
-<tr> <td><a name="Board delay [3] (ns)">Board delay [3] (ns)</a></td><td>0.187</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h1><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>PLL SLCR REGISTERS</h2>
-<ul>
-<p>PLL SLCR REGISTERS</p>
-<h2>ARM PLL INIT</h2>
-<ul>
-<p>ARM PLL INIT</p>
-<li><p>Register : ARM_PLL_CFG @ 0XF8000110</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">177</td><td class="hex">177000</td></tr>
-<tr><td><b>ARM_PLL_CFG @ 0XF8000110</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1772c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">1a</td><td class="hex">1a000</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>1a000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ARM_PLL_LOCK</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : ARM_CLK_CTRL @ 0XF8000120</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >CPU_6OR4XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >CPU_3OR2XCLKACT</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">1</td><td class="hex">2000000</td></tr>
-<tr><td >CPU_2XCLKACT</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >CPU_1XCLKACT</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >CPU_PERI_CLKACT</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>ARM_CLK_CTRL @ 0XF8000120</td><td></td><td class="hex"><b>1f003f30</b></td><td></td><td class="hex"><b>1f000200</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR PLL INIT</h2>
-<ul>
-<p>DDR PLL INIT</p>
-<li><p>Register : DDR_PLL_CFG @ 0XF8000114</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1db</td><td class="hex">1db000</td></tr>
-<tr><td><b>DDR_PLL_CFG @ 0XF8000114</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1db2c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">15</td><td class="hex">15000</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>15000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_PLL_LOCK</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>2</b></td><td></td><td class="hex"><b>2</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDR_CLK_CTRL @ 0XF8000124</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_3XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DDR_2XCLKACT</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DDR_3XCLK_DIVISOR</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td >DDR_2XCLK_DIVISOR</td><td class="hex">31:26</td><td class="hex">fc000000</td><td class="hex">3</td><td class="hex">c000000</td></tr>
-<tr><td><b>DDR_CLK_CTRL @ 0XF8000124</td><td></td><td class="hex"><b>fff00003</b></td><td></td><td class="hex"><b>c200003</b></td></tr></table>
-</li>
-</ul>
-<h2>IO PLL INIT</h2>
-<ul>
-<p>IO PLL INIT</p>
-<li><p>Register : IO_PLL_CFG @ 0XF8000118</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1f4</td><td class="hex">1f4000</td></tr>
-<tr><td><b>IO_PLL_CFG @ 0XF8000118</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1f42c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">14</td><td class="hex">14000</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>14000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IO_PLL_LOCK</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>4</b></td><td></td><td class="hex"><b>4</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>CLOCK CONTROL SLCR REGISTERS</h2>
-<ul>
-<p>CLOCK CONTROL SLCR REGISTERS</p>
-<li><p>Register : DCI_CLK_CTRL @ 0XF8000128</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">34</td><td class="hex">3400</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>DCI_CLK_CTRL @ 0XF8000128</td><td></td><td class="hex"><b>3f03f01</b></td><td></td><td class="hex"><b>203401</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_RCLK_CTRL @ 0XF8000138</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GEM0_RCLK_CTRL @ 0XF8000138</td><td></td><td class="hex"><b>11</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_CLK_CTRL @ 0XF8000140</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>GEM0_CLK_CTRL @ 0XF8000140</td><td></td><td class="hex"><b>3f03f71</b></td><td></td><td class="hex"><b>100801</b></td></tr></table>
-</li>
-<li><p>Register : LQSPI_CLK_CTRL @ 0XF800014C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>LQSPI_CLK_CTRL @ 0XF800014C</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : SDIO_CLK_CTRL @ 0XF8000150</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>SDIO_CLK_CTRL @ 0XF8000150</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1401</b></td></tr></table>
-</li>
-<li><p>Register : UART_CLK_CTRL @ 0XF8000154</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>UART_CLK_CTRL @ 0XF8000154</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1403</b></td></tr></table>
-</li>
-<li><p>Register : PCAP_CLK_CTRL @ 0XF8000168</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>PCAP_CLK_CTRL @ 0XF8000168</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : FPGA0_CLK_CTRL @ 0XF8000170</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA0_CLK_CTRL @ 0XF8000170</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : FPGA1_CLK_CTRL @ 0XF8000180</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">3</td><td class="hex">30</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA1_CLK_CTRL @ 0XF8000180</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100630</b></td></tr></table>
-</li>
-<li><p>Register : FPGA2_CLK_CTRL @ 0XF8000190</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">35</td><td class="hex">3500</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>FPGA2_CLK_CTRL @ 0XF8000190</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>203520</b></td></tr></table>
-</li>
-<li><p>Register : FPGA3_CLK_CTRL @ 0XF80001A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA3_CLK_CTRL @ 0XF80001A0</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : CLK_621_TRUE @ 0XF80001C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLK_621_TRUE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>CLK_621_TRUE @ 0XF80001C4</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : APER_CLK_CTRL @ 0XF800012C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DMA_CPU_2XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >USB0_CPU_1XCLKACT</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USB1_CPU_1XCLKACT</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >GEM0_CPU_1XCLKACT</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >GEM1_CPU_1XCLKACT</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SDI0_CPU_1XCLKACT</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >SDI1_CPU_1XCLKACT</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI0_CPU_1XCLKACT</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI1_CPU_1XCLKACT</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN0_CPU_1XCLKACT</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN1_CPU_1XCLKACT</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >I2C0_CPU_1XCLKACT</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">1</td><td class="hex">40000</td></tr>
-<tr><td >I2C1_CPU_1XCLKACT</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >UART0_CPU_1XCLKACT</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >UART1_CPU_1XCLKACT</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >GPIO_CPU_1XCLKACT</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >LQSPI_CPU_1XCLKACT</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >SMC_CPU_1XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td><b>APER_CLK_CTRL @ 0XF800012C</td><td></td><td class="hex"><b>1ffcccd</b></td><td></td><td class="hex"><b>1fc044d</b></td></tr></table>
-</li>
-</ul>
-<h2>THIS SHOULD BE BLANK</h2>
-<ul>
-<p>THIS SHOULD BE BLANK</p>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></h1>
-<ul>
-<h2>DDR INITIALIZATION</h2>
-<ul>
-<p>DDR INITIALIZATION</p>
-<h2>LOCK DDR</h2>
-<ul>
-<p>LOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>80</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : Two_rank_cfg @ 0XF8006004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rfc_nom_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">7f</td><td class="hex">7f</td></tr>
-<tr><td >reg_ddrc_active_ranks</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit0</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_block</td><td class="hex">20:19</td><td class="hex">180000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_diff_rank_rd_2cycle_gap</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit1</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_open_bank</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_4bank_ram</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>Two_rank_cfg @ 0XF8006004</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>8107f</b></td></tr></table>
-</li>
-<li><p>Register : HPR_reg @ 0XF8006008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_hpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">f</td><td class="hex">f</td></tr>
-<tr><td >reg_ddrc_hpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">f</td><td class="hex">7800</td></tr>
-<tr><td >reg_ddrc_hpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">f</td><td class="hex">3c00000</td></tr>
-<tr><td><b>HPR_reg @ 0XF8006008</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>3c0780f</b></td></tr></table>
-</li>
-<li><p>Register : LPR_reg @ 0XF800600C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_lpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">2</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_lpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">8</td><td class="hex">2000000</td></tr>
-<tr><td><b>LPR_reg @ 0XF800600C</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>2001001</b></td></tr></table>
-</li>
-<li><p>Register : WR_reg @ 0XF8006010</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_w_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_w_xact_run_length</td><td class="hex">14:11</td><td class="hex">7800</td><td class="hex">8</td><td class="hex">4000</td></tr>
-<tr><td >reg_ddrc_w_max_starve_x32</td><td class="hex">25:15</td><td class="hex">3ff8000</td><td class="hex">2</td><td class="hex">10000</td></tr>
-<tr><td><b>WR_reg @ 0XF8006010</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>14001</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg0 @ 0XF8006014</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rc</td><td class="hex">5:0</td><td class="hex">3f</td><td class="hex">1a</td><td class="hex">1a</td></tr>
-<tr><td >reg_ddrc_t_rfc_min</td><td class="hex">13:6</td><td class="hex">3fc0</td><td class="hex">54</td><td class="hex">1500</td></tr>
-<tr><td >reg_ddrc_post_selfref_gap_x32</td><td class="hex">20:14</td><td class="hex">1fc000</td><td class="hex">10</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_param_reg0 @ 0XF8006014</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>4151a</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg1 @ 0XF8006018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wr2pre</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">12</td><td class="hex">12</td></tr>
-<tr><td >reg_ddrc_powerdown_to_x32</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_t_faw</td><td class="hex">15:10</td><td class="hex">fc00</td><td class="hex">15</td><td class="hex">5400</td></tr>
-<tr><td >reg_ddrc_t_ras_max</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">23</td><td class="hex">230000</td></tr>
-<tr><td >reg_ddrc_t_ras_min</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">13</td><td class="hex">4c00000</td></tr>
-<tr><td >reg_ddrc_t_cke</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">4</td><td class="hex">40000000</td></tr>
-<tr><td><b>DRAM_param_reg1 @ 0XF8006018</td><td></td><td class="hex"><b>f7ffffff</b></td><td></td><td class="hex"><b>44e354d2</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg2 @ 0XF800601C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_write_latency</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_rd2wr</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >reg_ddrc_wr2rd</td><td class="hex">14:10</td><td class="hex">7c00</td><td class="hex">e</td><td class="hex">3800</td></tr>
-<tr><td >reg_ddrc_t_xp</td><td class="hex">19:15</td><td class="hex">f8000</td><td class="hex">4</td><td class="hex">20000</td></tr>
-<tr><td >reg_ddrc_pad_pd</td><td class="hex">22:20</td><td class="hex">700000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd2pre</td><td class="hex">27:23</td><td class="hex">f800000</td><td class="hex">4</td><td class="hex">2000000</td></tr>
-<tr><td >reg_ddrc_t_rcd</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>DRAM_param_reg2 @ 0XF800601C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>720238e5</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg3 @ 0XF8006020</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ccd</td><td class="hex">4:2</td><td class="hex">1c</td><td class="hex">4</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_t_rrd</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_refresh_margin</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_rp</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">7</td><td class="hex">7000</td></tr>
-<tr><td >reg_ddrc_refresh_to_x32</td><td class="hex">20:16</td><td class="hex">1f0000</td><td class="hex">8</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_sdram</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_mobile</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_clock_stop_en</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_read_latency</td><td class="hex">28:24</td><td class="hex">1f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_mode_ddr1_ddr2</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">1</td><td class="hex">20000000</td></tr>
-<tr><td >reg_ddrc_dis_pad_pd</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_loopback</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg3 @ 0XF8006020</td><td></td><td class="hex"><b>fffffffc</b></td><td></td><td class="hex"><b>272872d0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg4 @ 0XF8006024</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_en_2t_timing_mode</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_prefer_write</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_max_rank_rd</td><td class="hex">5:2</td><td class="hex">3c</td><td class="hex">f</td><td class="hex">3c</td></tr>
-<tr><td >reg_ddrc_mr_wr</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_addr</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_data</td><td class="hex">24:9</td><td class="hex">1fffe00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_mr_wr_busy</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_type</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_rdata_valid</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg4 @ 0XF8006024</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>3c</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_init_param @ 0XF8006028</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_final_wait_x32</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_pre_ocd_x32</td><td class="hex">10:7</td><td class="hex">780</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_t_mrd</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">4</td><td class="hex">2000</td></tr>
-<tr><td><b>DRAM_init_param @ 0XF8006028</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2007</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_reg @ 0XF800602C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_emr2</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">8</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_emr3</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_EMR_reg @ 0XF800602C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_MR_reg @ 0XF8006030</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">930</td><td class="hex">930</td></tr>
-<tr><td >reg_ddrc_emr</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">4</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_EMR_MR_reg @ 0XF8006030</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>40930</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_burst8_rdwr @ 0XF8006034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_burst_rdwr</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">4</td><td class="hex">4</td></tr>
-<tr><td >reg_ddrc_pre_cke_x1024</td><td class="hex">13:4</td><td class="hex">3ff0</td><td class="hex">101</td><td class="hex">1010</td></tr>
-<tr><td >reg_ddrc_post_cke_x1024</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_ddrc_burstchop</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_burst8_rdwr @ 0XF8006034</td><td></td><td class="hex"><b>13ff3fff</b></td><td></td><td class="hex"><b>11014</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_disable_DQ @ 0XF8006038</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_force_low_pri_n</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_dq</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_debug_mode</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_level_start</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_level_start</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq0_wait_t</td><td class="hex">12:9</td><td class="hex">1e00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_disable_DQ @ 0XF8006038</td><td></td><td class="hex"><b>1fc3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_bank @ 0XF800603C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_bank_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">7</td><td class="hex">70</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b2</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">7</td><td class="hex">700</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b5</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b6</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_addr_map_bank @ 0XF800603C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>777</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_col @ 0XF8006040</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_col_b2</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b3</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b4</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b7</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b8</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b9</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b10</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b11</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">f</td><td class="hex">f0000000</td></tr>
-<tr><td><b>DRAM_addr_map_col @ 0XF8006040</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>fff00000</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_row @ 0XF8006044</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_row_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">6</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b2_11</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b12</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b13</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b14</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b15</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td><b>DRAM_addr_map_row @ 0XF8006044</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>ff66666</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_ODT_reg @ 0XF8006048</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rank0_rd_odt</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank0_wr_odt</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_rank1_rd_odt</td><td class="hex">8:6</td><td class="hex">1c0</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >reg_ddrc_rank1_wr_odt</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_phy_rd_local_odt</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_local_odt</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reg_phy_idle_local_odt</td><td class="hex">17:16</td><td class="hex">30000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td >reg_ddrc_rank2_rd_odt</td><td class="hex">20:18</td><td class="hex">1c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank2_wr_odt</td><td class="hex">23:21</td><td class="hex">e00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_rd_odt</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_wr_odt</td><td class="hex">29:27</td><td class="hex">38000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_ODT_reg @ 0XF8006048</td><td></td><td class="hex"><b>3fffffff</b></td><td></td><td class="hex"><b>3c248</b></td></tr></table>
-</li>
-<li><p>Register : phy_cmd_timeout_rddata_cpt @ 0XF8006050</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_cmd_to_data</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_cmd_to_data</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rdc_we_to_re_delay</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_disable</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_fixed_re</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_err_cnt_clr</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dis_phy_ctrl_rstn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_clk_stall_level</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_num_of_dq0</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_wrlvl_num_of_dq0</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>phy_cmd_timeout_rddata_cpt @ 0XF8006050</td><td></td><td class="hex"><b>ff0f8fff</b></td><td></td><td class="hex"><b>77010800</b></td></tr></table>
-</li>
-<li><p>Register : DLL_calib @ 0XF8006058</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dll_calib_to_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dll_calib_to_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_dis_dll_calib</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DLL_calib @ 0XF8006058</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>101</b></td></tr></table>
-</li>
-<li><p>Register : ODT_delay_hold @ 0XF800605C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rd_odt_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >reg_ddrc_wr_odt_delay</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd_odt_hold</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_hold</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>ODT_delay_hold @ 0XF800605C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>5003</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg1 @ 0XF8006060</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_pageclose</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_lpr_num_entries</td><td class="hex">6:1</td><td class="hex">7e</td><td class="hex">1f</td><td class="hex">3e</td></tr>
-<tr><td >reg_ddrc_auto_pre_en</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_refresh_update_level</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_wc</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_collision_page_opt</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_selfref_en</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ctrl_reg1 @ 0XF8006060</td><td></td><td class="hex"><b>17ff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg2 @ 0XF8006064</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_go2critical_hysteresis</td><td class="hex">12:5</td><td class="hex">1fe0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_go2critical_en</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td><b>ctrl_reg2 @ 0XF8006064</td><td></td><td class="hex"><b>21fe0</b></td><td></td><td class="hex"><b>20000</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg3 @ 0XF8006068</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wrlvl_ww</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">41</td><td class="hex">41</td></tr>
-<tr><td >reg_ddrc_rdlvl_rr</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">41</td><td class="hex">4100</td></tr>
-<tr><td >reg_ddrc_dfi_t_wlmrd</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">28</td><td class="hex">280000</td></tr>
-<tr><td><b>ctrl_reg3 @ 0XF8006068</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>284141</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg4 @ 0XF800606C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_t_ctrlupd_interval_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">10</td><td class="hex">10</td></tr>
-<tr><td >dfi_t_ctrlupd_interval_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">16</td><td class="hex">1600</td></tr>
-<tr><td><b>ctrl_reg4 @ 0XF800606C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>1610</b></td></tr></table>
-</li>
-<li><p>Register : CHE_REFRESH_TIMER01 @ 0XF80060A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >refresh_timer0_start_value_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >refresh_timer1_start_value_x32</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">8</td><td class="hex">8000</td></tr>
-<tr><td><b>CHE_REFRESH_TIMER01 @ 0XF80060A0</td><td></td><td class="hex"><b>ffffff</b></td><td></td><td class="hex"><b>8000</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ @ 0XF80060A4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_auto_zq</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_ddr3</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_mod</td><td class="hex">11:2</td><td class="hex">ffc</td><td class="hex">200</td><td class="hex">800</td></tr>
-<tr><td >reg_ddrc_t_zq_long_nop</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">200</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_t_zq_short_nop</td><td class="hex">31:22</td><td class="hex">ffc00000</td><td class="hex">40</td><td class="hex">10000000</td></tr>
-<tr><td><b>CHE_T_ZQ @ 0XF80060A4</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10200802</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >t_zq_short_interval_x1024</td><td class="hex">19:0</td><td class="hex">fffff</td><td class="hex">c845</td><td class="hex">c845</td></tr>
-<tr><td >dram_rstn_x1024</td><td class="hex">27:20</td><td class="hex">ff00000</td><td class="hex">67</td><td class="hex">6700000</td></tr>
-<tr><td><b>CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>670c845</b></td></tr></table>
-</li>
-<li><p>Register : deep_pwrdwn_reg @ 0XF80060AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >deeppowerdown_en</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >deeppowerdown_to_x1024</td><td class="hex">8:1</td><td class="hex">1fe</td><td class="hex">ff</td><td class="hex">1fe</td></tr>
-<tr><td><b>deep_pwrdwn_reg @ 0XF80060AC</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>1fe</b></td></tr></table>
-</li>
-<li><p>Register : reg_2c @ 0XF80060B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_wrlvl_max_x1024</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">fff</td><td class="hex">fff</td></tr>
-<tr><td >dfi_rdlvl_max_x1024</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">fff</td><td class="hex">fff000</td></tr>
-<tr><td >ddrc_reg_twrlvl_max_error</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_trdlvl_max_error</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dfi_wr_level_en</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_dqs_gate_level</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_data_eye_train</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>reg_2c @ 0XF80060B0</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>1cffffff</b></td></tr></table>
-</li>
-<li><p>Register : reg_2d @ 0XF80060B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_2t_delay</td><td class="hex">8:0</td><td class="hex">1ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_skip_ocd</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_dis_pre_bypass</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_2d @ 0XF80060B4</td><td></td><td class="hex"><b>7ff</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : dfi_timing @ 0XF80060B8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_rddata_en</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_min</td><td class="hex">14:5</td><td class="hex">7fe0</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_max</td><td class="hex">24:15</td><td class="hex">1ff8000</td><td class="hex">40</td><td class="hex">200000</td></tr>
-<tr><td><b>dfi_timing @ 0XF80060B8</td><td></td><td class="hex"><b>1ffffff</b></td><td></td><td class="hex"><b>200066</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>3</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ECC_CORRECTED_BIT_NUM</td><td class="hex">7:1</td><td class="hex">fe</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNCORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STAT_NUM_CORR_ERR</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STAT_NUM_UNCORR_ERR</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ECC_scrub @ 0XF80060F4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_ecc_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_scrub</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td><b>ECC_scrub @ 0XF80060F4</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : phy_rcvr_enable @ 0XF8006114</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_dif_on</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dif_off</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rcvr_enable @ 0XF8006114</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006118</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006118</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF800611C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF800611C</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006120</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006120</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006124</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006124</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF800612C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8f</td><td class="hex">23c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF800612C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>23c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006130</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8a</td><td class="hex">22800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006130</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22800</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006134</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8b</td><td class="hex">22c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006134</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006138</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">92</td><td class="hex">24800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006138</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>24800</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006140</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006140</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006144</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006144</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006148</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006148</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF800614C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF800614C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006154</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">77</td><td class="hex">77</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006154</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>77</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006158</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006158</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF800615C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF800615C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006160</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">75</td><td class="hex">75</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006160</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>75</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006168</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e4</td><td class="hex">e4</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006168</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e4</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF800616C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">df</td><td class="hex">df</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF800616C</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>df</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006170</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e0</td><td class="hex">e0</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006170</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e0</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006174</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e7</td><td class="hex">e7</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006174</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF800617C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b7</td><td class="hex">b7</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF800617C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006180</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006180</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006184</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006184</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006188</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b5</td><td class="hex">b5</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006188</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b5</b></td></tr></table>
-</li>
-<li><p>Register : reg_64 @ 0XF8006190</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_loopback</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bl2</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_at_spd_atpg</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_enable</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_force_err</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_mode</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_invert_clkout</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_all_dq_mpr_rd_resp</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_sel_logic</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">100</td><td class="hex">40000</td></tr>
-<tr><td >reg_phy_ctrl_slave_force</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">27:21</td><td class="hex">fe00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_rank0_delays</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td >reg_phy_lpddr</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_cmd_latency</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_int_lpbk</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_64 @ 0XF8006190</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10040080</b></td></tr></table>
-</li>
-<li><p>Register : reg_65 @ 0XF8006194</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_rl_delay</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_phy_rd_rl_delay</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_dll_lock_diff</td><td class="hex">13:10</td><td class="hex">3c00</td><td class="hex">f</td><td class="hex">3c00</td></tr>
-<tr><td >reg_phy_use_wr_level</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">1</td><td class="hex">4000</td></tr>
-<tr><td >reg_phy_use_rd_dqs_gate_level</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">1</td><td class="hex">8000</td></tr>
-<tr><td >reg_phy_use_rd_data_eye_level</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_dis_calib_rst</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_65 @ 0XF8006194</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>1fc82</b></td></tr></table>
-</li>
-<li><p>Register : page_mask @ 0XF8006204</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_page_addr_mask</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>page_mask @ 0XF8006204</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006208</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006208</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF800620C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF800620C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006210</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006210</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006214</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006214</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006218</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006218</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF800621C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF800621C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006220</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006220</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006224</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006224</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl0 @ 0XF80062A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpddr2</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_per_bank_refresh</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_derate_enable</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr4_margin</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl0 @ 0XF80062A8</td><td></td><td class="hex"><b>ff7</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl1 @ 0XF80062AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr4_read_interval</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl1 @ 0XF80062AC</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl2 @ 0XF80062B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_min_stable_clock_x1</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_idle_after_reset_x32</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">12</td><td class="hex">120</td></tr>
-<tr><td >reg_ddrc_t_mrw</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>lpddr_ctrl2 @ 0XF80062B0</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>5125</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl3 @ 0XF80062B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_max_auto_init_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">a6</td><td class="hex">a6</td></tr>
-<tr><td >reg_ddrc_dev_zqinit_x32</td><td class="hex">17:8</td><td class="hex">3ff00</td><td class="hex">12</td><td class="hex">1200</td></tr>
-<tr><td><b>lpddr_ctrl3 @ 0XF80062B4</td><td></td><td class="hex"><b>3ffff</b></td><td></td><td class="hex"><b>12a6</b></td></tr></table>
-</li>
-<h2>POLL ON DCI STATUS</h2>
-<ul>
-<p>POLL ON DCI STATUS</p>
-<li><p>Register : DDRIOB_DCI_STATUS @ 0XF8000B74</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DONE</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>DDRIOB_DCI_STATUS @ 0XF8000B74</td><td></td><td class="hex"><b>2000</b></td><td></td><td class="hex"><b>2000</b></td></tr></table>
-</li>
-</ul>
-<h2>UNLOCK DDR</h2>
-<ul>
-<p>UNLOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>81</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK DDR STATUS</h2>
-<ul>
-<p>CHECK DDR STATUS</p>
-<li><p>Register : mode_sts_reg @ 0XF8006054</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ddrc_reg_operating_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>mode_sts_reg @ 0XF8006054</td><td></td><td class="hex"><b>7</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>OCM REMAPPING</h2>
-<ul>
-<p>OCM REMAPPING</p>
-<li><p>Register : GPIOB_CTRL @ 0XF8000B00</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLK_PULLUP_EN</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRSTN_PULLUP_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GPIOB_CTRL @ 0XF8000B00</td><td></td><td class="hex"><b>303</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DDRIOB SETTINGS</h2>
-<ul>
-<p>DDRIOB SETTINGS</p>
-<li><p>Register : DDRIOB_ADDR0 @ 0XF8000B40</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR0 @ 0XF8000B40</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_ADDR1 @ 0XF8000B44</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR1 @ 0XF8000B44</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_CLOCK @ 0XF8000B58</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_CLOCK @ 0XF8000B58</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DDR_CTRL @ 0XF8000B6C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_INT_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">4:1</td><td class="hex">1e</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_EXT_EN</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >REFIO_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >REFIO_PULLUP_EN</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DRST_B_PULLUP_EN</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CKE_PULLUP_EN</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DDR_CTRL @ 0XF8000B6C</td><td></td><td class="hex"><b>73ff</b></td><td></td><td class="hex"><b>260</b></td></tr></table>
-</li>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>21</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >ENABLE</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >VRP_TRI</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_TRI</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRP_OUT</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td >NREF_OPT1</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT2</td><td class="hex">10:8</td><td class="hex">700</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT4</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >PREF_OPT1</td><td class="hex">16:14</td><td class="hex">1c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PREF_OPT2</td><td class="hex">19:17</td><td class="hex">e0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UPDATE_CONTROL</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INIT_COMPLETE</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_CLK</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLN</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLP</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_RST</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INT_DCI_EN</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>7ffffff</b></td><td></td><td class="hex"><b>823</b></td></tr></table>
-</li>
-</ul>
-<h2>MIO PROGRAMMING</h2>
-<ul>
-<p>MIO PROGRAMMING</p>
-<li><p>Register : MIO_PIN_00 @ 0XF8000700</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_00 @ 0XF8000700</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_01 @ 0XF8000704</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_01 @ 0XF8000704</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_02 @ 0XF8000708</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_02 @ 0XF8000708</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_03 @ 0XF800070C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_03 @ 0XF800070C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_04 @ 0XF8000710</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_04 @ 0XF8000710</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_05 @ 0XF8000714</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_05 @ 0XF8000714</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_06 @ 0XF8000718</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_06 @ 0XF8000718</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_07 @ 0XF800071C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_07 @ 0XF800071C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_08 @ 0XF8000720</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_08 @ 0XF8000720</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_09 @ 0XF8000724</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_09 @ 0XF8000724</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_10 @ 0XF8000728</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_10 @ 0XF8000728</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_11 @ 0XF800072C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_11 @ 0XF800072C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_12 @ 0XF8000730</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_12 @ 0XF8000730</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_13 @ 0XF8000734</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_13 @ 0XF8000734</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_14 @ 0XF8000738</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_14 @ 0XF8000738</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_15 @ 0XF800073C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_15 @ 0XF800073C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_16 @ 0XF8000740</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_16 @ 0XF8000740</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_17 @ 0XF8000744</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_17 @ 0XF8000744</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_18 @ 0XF8000748</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_18 @ 0XF8000748</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_19 @ 0XF800074C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_19 @ 0XF800074C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_20 @ 0XF8000750</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_20 @ 0XF8000750</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_21 @ 0XF8000754</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_21 @ 0XF8000754</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_22 @ 0XF8000758</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_22 @ 0XF8000758</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_23 @ 0XF800075C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_23 @ 0XF800075C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_24 @ 0XF8000760</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_24 @ 0XF8000760</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_25 @ 0XF8000764</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_25 @ 0XF8000764</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_26 @ 0XF8000768</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_26 @ 0XF8000768</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_27 @ 0XF800076C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_27 @ 0XF800076C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_28 @ 0XF8000770</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_28 @ 0XF8000770</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_29 @ 0XF8000774</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_29 @ 0XF8000774</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_30 @ 0XF8000778</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_30 @ 0XF8000778</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_31 @ 0XF800077C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_31 @ 0XF800077C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_32 @ 0XF8000780</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_32 @ 0XF8000780</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_33 @ 0XF8000784</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_33 @ 0XF8000784</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_34 @ 0XF8000788</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_34 @ 0XF8000788</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_35 @ 0XF800078C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_35 @ 0XF800078C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_36 @ 0XF8000790</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_36 @ 0XF8000790</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_37 @ 0XF8000794</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_37 @ 0XF8000794</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_38 @ 0XF8000798</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_38 @ 0XF8000798</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_39 @ 0XF800079C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_39 @ 0XF800079C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_40 @ 0XF80007A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_40 @ 0XF80007A0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_41 @ 0XF80007A4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_41 @ 0XF80007A4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_42 @ 0XF80007A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_42 @ 0XF80007A8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_43 @ 0XF80007AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_43 @ 0XF80007AC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_44 @ 0XF80007B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_44 @ 0XF80007B0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_45 @ 0XF80007B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_45 @ 0XF80007B4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_46 @ 0XF80007B8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_46 @ 0XF80007B8</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_47 @ 0XF80007BC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_47 @ 0XF80007BC</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_48 @ 0XF80007C0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_48 @ 0XF80007C0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e0</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_49 @ 0XF80007C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_49 @ 0XF80007C4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e1</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_50 @ 0XF80007C8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_50 @ 0XF80007C8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_51 @ 0XF80007CC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_51 @ 0XF80007CC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_52 @ 0XF80007D0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_52 @ 0XF80007D0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_53 @ 0XF80007D4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_53 @ 0XF80007D4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : SD0_WP_CD_SEL @ 0XF8000830</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SDIO0_CD_SEL</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">2f</td><td class="hex">2f0000</td></tr>
-<tr><td><b>SD0_WP_CD_SEL @ 0XF8000830</td><td></td><td class="hex"><b>3f0000</b></td><td></td><td class="hex"><b>2f0000</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR TERM/IBUF_DISABLE_MODE SETTINGS</h2>
-<ul>
-<p>DDR TERM/IBUF_DISABLE_MODE SETTINGS</p>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-<h2>SRAM/NOR SET OPMODE</h2>
-<ul>
-<p>SRAM/NOR SET OPMODE</p>
-</ul>
-<h2>UART REGISTERS</h2>
-<ul>
-<p>UART REGISTERS</p>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0001034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0001034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0001018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0001018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0001000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0001000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0001004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0001004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0000034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0000034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0000018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0000018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0000000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0000000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0000004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<h2>PL POWER ON RESET REGISTERS</h2>
-<ul>
-<p>PL POWER ON RESET REGISTERS</p>
-<li><p>Register : CTRL @ 0XF8007000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PCFG_POR_CNT_4K</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CTRL @ 0XF8007000</td><td></td><td class="hex"><b>20000000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>SMC TIMING CALCULATION REGISTER UPDATE</h2>
-<ul>
-<p>SMC TIMING CALCULATION REGISTER UPDATE</p>
-<h2>NAND SET CYCLE</h2>
-<ul>
-<p>NAND SET CYCLE</p>
-</ul>
-<h2>OPMODE</h2>
-<ul>
-<p>OPMODE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>SRAM/NOR CS0 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS0 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS0 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS0 BASE ADDRESS</p>
-</ul>
-<h2>SRAM/NOR CS1 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS1 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS1 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS1 BASE ADDRESS</p>
-</ul>
-<h2>USB RESET</h2>
-<ul>
-<p>USB RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-<li><p>Register : DIRM_1 @ 0XE000A244</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DIRECTION_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>DIRM_1 @ 0XE000A244</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-<li><p>Register : OEN_1 @ 0XE000A248</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >OP_ENABLE_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>OEN_1 @ 0XE000A248</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff0000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>ENET RESET</h2>
-<ul>
-<p>ENET RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>I2C RESET</h2>
-<ul>
-<p>I2C RESET</p>
-<h2>DIR MODE GPIO BANK0</h2>
-<ul>
-<p>DIR MODE GPIO BANK0</p>
-</ul>
-<h2>DIR MODE GPIO BANK1</h2>
-<ul>
-<p>DIR MODE GPIO BANK1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>ENABLING LEVEL SHIFTER</h2>
-<ul>
-<p>ENABLING LEVEL SHIFTER</p>
-<li><p>Register : LVL_SHFTR_EN @ 0XF8000900</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >USER_INP_ICT_EN_0</td><td class="hex">1:0</td><td class="hex">3</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >USER_INP_ICT_EN_1</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">3</td><td class="hex">c</td></tr>
-<tr><td><b>LVL_SHFTR_EN @ 0XF8000900</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>f</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 1</h2>
-<ul>
-<p>FPGA RESETS TO 1</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">7f</td><td class="hex">fe000000</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">3</td><td class="hex">c0000</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">f</td><td class="hex">f0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>ffffffff</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 0</h2>
-<ul>
-<p>FPGA RESETS TO 0</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>AFI REGISTERS</h2>
-<ul>
-<p>AFI REGISTERS</p>
-<h2>AFI0 REGISTERS</h2>
-<ul>
-<p>AFI0 REGISTERS</p>
-</ul>
-<h2>AFI1 REGISTERS</h2>
-<ul>
-<p>AFI1 REGISTERS</p>
-</ul>
-<h2>AFI2 REGISTERS</h2>
-<ul>
-<p>AFI2 REGISTERS</p>
-</ul>
-<h2>AFI3 REGISTERS</h2>
-<ul>
-<p>AFI3 REGISTERS</p>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-</body>
-</html>
-<!DOCTYPE html>
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8"/>
-<title>Zynq PS configuration detail</title>
-<style type="text/css">
-.hex {font-family:monospace ; text-align : right}
-td { min-width : 80px ; }
-</style>
-</head>
-<body>
-<p style="height: 7px">Following peripherals are selected in the design. </p>
-<p><br /></p>
-<h2><a name="Top">Peripheral Selected</a></h2>
-<ul>
-<li>Quad SPI Flash</li>
-<li>Enet 0</li>
-<li>USB 0</li>
-<li>SD 0</li>
-<li>UART 0</li>
-<li>UART 1</li>
-<li>I2C 0</li>
-<li>I2C 1</li>
-<li>GPIO</li>
-</ul>
-<p>To see detailed information please follow below links:</p>
-<ul>
-<li><a href="#MIOConfTab">MIO Configuration Table</a></li>
-<li><a href="#ZynqPerTab">Zynq Peripheral Configuration</a></li>
-<li><a href="#DDRInfoTab">DDR Configuration Information</a></li>
-<li>SLCR settings</li>
-<ul>
-<li><a href="#ps7_pll_init_data">PLL Init Data</a></li>
-<li><a href="#ps7_clock_init_data">Clock Init Data</a></li>
-<li><a href="#ps7_ddr_init_data">DDR Init Data</a></li>
-<li><a href="#ps7_mio_init_data">MIO Init Data</a></li>
-</ul>
-</ul>
-<h2><a name="MIOConfTab">MIO configuration Table</a></h2>
-<ul><table border="1">
-<thead><tr> <th>MIO Pin</th> <th>Peripheral</th> <th>Signal</th> <th>IO type</th> <th>Speed</th> <th>Pullup</th> <th>Direction</th> </tr></thead>
-<tr bgcolor="#FA4A46"><td><a name="MIO 0">MIO 0</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[0]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 1">MIO 1</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_ss_b</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 2">MIO 2</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[0]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 3">MIO 3</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[1]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 4">MIO 4</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[2]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 5">MIO 5</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[3]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 6">MIO 6</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_sclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 7">MIO 7</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[7]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 8">MIO 8</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi_fbclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 9">MIO 9</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[9]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 10">MIO 10</a></td><td><a href="#I2C 0">I2C 0</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 11">MIO 11</a></td><td><a href="#I2C 0">I2C 0</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 12">MIO 12</a></td><td><a href="#I2C 1">I2C 1</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 13">MIO 13</a></td><td><a href="#I2C 1">I2C 1</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 14">MIO 14</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[14]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 15">MIO 15</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[15]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 16">MIO 16</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 17">MIO 17</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 18">MIO 18</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 19">MIO 19</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 20">MIO 20</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 21">MIO 21</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 22">MIO 22</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 23">MIO 23</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 24">MIO 24</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 25">MIO 25</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 26">MIO 26</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 27">MIO 27</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 28">MIO 28</a></td><td><a href="#USB 0">USB 0</a></td><td>data[4]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 29">MIO 29</a></td><td><a href="#USB 0">USB 0</a></td><td>dir</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 30">MIO 30</a></td><td><a href="#USB 0">USB 0</a></td><td>stp</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 31">MIO 31</a></td><td><a href="#USB 0">USB 0</a></td><td>nxt</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 32">MIO 32</a></td><td><a href="#USB 0">USB 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 33">MIO 33</a></td><td><a href="#USB 0">USB 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 34">MIO 34</a></td><td><a href="#USB 0">USB 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 35">MIO 35</a></td><td><a href="#USB 0">USB 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 36">MIO 36</a></td><td><a href="#USB 0">USB 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 37">MIO 37</a></td><td><a href="#USB 0">USB 0</a></td><td>data[5]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 38">MIO 38</a></td><td><a href="#USB 0">USB 0</a></td><td>data[6]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 39">MIO 39</a></td><td><a href="#USB 0">USB 0</a></td><td>data[7]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 40">MIO 40</a></td><td><a href="#SD 0">SD 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 41">MIO 41</a></td><td><a href="#SD 0">SD 0</a></td><td>cmd</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 42">MIO 42</a></td><td><a href="#SD 0">SD 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 43">MIO 43</a></td><td><a href="#SD 0">SD 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 44">MIO 44</a></td><td><a href="#SD 0">SD 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 45">MIO 45</a></td><td><a href="#SD 0">SD 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 46">MIO 46</a></td><td><a href="#USB 0">USB 0</a></td><td>reset</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 47">MIO 47</a></td><td><a href="#SD 0">SD 0</a></td><td>cd</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 48">MIO 48</a></td><td><a href="#UART 1">UART 1</a></td><td>tx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 49">MIO 49</a></td><td><a href="#UART 1">UART 1</a></td><td>rx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 50">MIO 50</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[50]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 51">MIO 51</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[51]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 52">MIO 52</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdc</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 53">MIO 53</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdio</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="ZynqPerTab">Zynq Peripheral Configuration</a></h2>
-<ul><table border="1">
-<tr><thead> <th>Peripheral</th> <th>Signal Group</th> <th>Signal</th> <th>MIO</th> </thead></tr>
-<tr bgcolor="#FAEBD7"><td><a name="Quad SPI Flash" >Quad SPI Flash</a></td> <td></td><td></td><td>MIO 1 .. 6</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (4 bit) </td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (Parallel 8 bit)</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Feedback Clk</td><td></td><td>MIO 8</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="nor" >SRAM/NOR Flash</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFE4C4"><td><a name="nand" >NAND Flash</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DEB887"><td><a name="Enet 0" >Enet 0</a></td> <td></td><td></td><td>MIO 16 .. 27</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_clk</td><td><a href="#MIO 16">MIO 16</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[3]</td><td><a href="#MIO 20">MIO 20</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[2]</td><td><a href="#MIO 19">MIO 19</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[1]</td><td><a href="#MIO 18">MIO 18</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[0]</td><td><a href="#MIO 17">MIO 17</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_ctl</td><td><a href="#MIO 21">MIO 21</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_clk</td><td><a href="#MIO 22">MIO 22</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[3]</td><td><a href="#MIO 26">MIO 26</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[2]</td><td><a href="#MIO 25">MIO 25</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[1]</td><td><a href="#MIO 24">MIO 24</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[0]</td><td><a href="#MIO 23">MIO 23</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_ctl</td><td><a href="#MIO 27">MIO 27</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td>MDIO</td><td></td><td>MIO 52 .. 53</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdc</td><td><a href="#MIO 52">MIO 52</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdio</td><td><a href="#MIO 53">MIO 53</a></td></tr>
-<tr bgcolor="#DEB887"><td><a name="enet1" >Enet 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="USB 0" >USB 0</a></td> <td></td><td></td><td>MIO 28 .. 39</td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>clk</td><td><a href="#MIO 36">MIO 36</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>dir</td><td><a href="#MIO 29">MIO 29</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>stp</td><td><a href="#MIO 30">MIO 30</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>nxt</td><td><a href="#MIO 31">MIO 31</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[0]</td><td><a href="#MIO 32">MIO 32</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[1]</td><td><a href="#MIO 33">MIO 33</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[2]</td><td><a href="#MIO 34">MIO 34</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[3]</td><td><a href="#MIO 35">MIO 35</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[4]</td><td><a href="#MIO 28">MIO 28</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[5]</td><td><a href="#MIO 37">MIO 37</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[6]</td><td><a href="#MIO 38">MIO 38</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[7]</td><td><a href="#MIO 39">MIO 39</a></td></tr>
-<tr bgcolor="#7FFF00"><td><a name="usb1" >USB 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="SD 0" >SD 0</a></td> <td></td><td></td><td>MIO 40 .. 45</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>CD</td><td></td><td>MIO 47</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>WP</td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>Power</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="sd1" >SD 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 0" >UART 0</a></td> <td></td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 1" >UART 1</a></td> <td></td><td></td><td>MIO 48 .. 49</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td><a href="#MIO 49">MIO 49</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td><a href="#MIO 48">MIO 48</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem Signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 0" >I2C 0</a></td> <td></td><td></td><td>MIO 10 .. 11</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 10">MIO 10</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 11">MIO 11</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 1" >I2C 1</a></td> <td></td><td></td><td>MIO 12 .. 13</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 12">MIO 12</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 13">MIO 13</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi0" >SPI 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi1" >SPI 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can0" >CAN 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can1" >CAN 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#ADD8E6"><td><a name="trace" >Trace</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc0" >Timer 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc1" >Timer 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FF6347"><td><a name="wdt" >Watchdog</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#EE82EE"><td><a name="pjtag" >PJTAG</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="GPIO" >GPIO</a></td> <td></td><td></td><td>MIO</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="mode" >Mode</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="vcfg" >VCfg</a></td> <td></td><td></td><td>Disabled</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="DDRInfoTab">DDR Memory information</a></h2>
-<h3><a name="DDRInfoTab">DDR Controller Configuration</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="Enable DDR">Enable DDR</a></td><td>1</td></tr>
-<tr> <td><a name="Memory Type">Memory Type</a></td><td>DDR 3</td></tr>
-<tr> <td><a name="Memory Part">Memory Part</a></td><td>MT41K128M16 JT-125</td></tr>
-<tr> <td><a name="DRAM bus width">DRAM bus width</a></td><td>32 Bit</td></tr>
-<tr> <td><a name="ECC">ECC</a></td><td>Disabled</td></tr>
-<tr> <td><a name="BURST Length (lppdr only)">BURST Length (lppdr only)</a></td><td>8</td></tr>
-<tr> <td><a name="Internal Vref">Internal Vref</a></td><td>0</td></tr>
-<tr> <td><a name="Operating Frequency (MHz)">Operating Frequency (MHz)</a></td><td>525.000000</td></tr>
-<tr> <td><a name="HIGH temperature">HIGH temperature</a></td><td>Normal (0-85)</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Memory Part Configuration</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="DRAM IC bus width">DRAM IC bus width</a></td><td>16 Bits</td></tr>
-<tr> <td><a name="DRAM Device Capacity">DRAM Device Capacity</a></td><td>2048 MBits</td></tr>
-<tr> <td><a name="Speed Bin">Speed Bin</a></td><td>DDR3_1066F</td></tr>
-<tr> <td><a name="BANK Address Count">BANK Address Count</a></td><td>3</td></tr>
-<tr> <td><a name="ROW Address Count">ROW Address Count</a></td><td>14</td></tr>
-<tr> <td><a name="COLUMN Address Count">COLUMN Address Count</a></td><td>10</td></tr>
-<tr> <td><a name="CAS Latency">CAS Latency</a></td><td>7</td></tr>
-<tr> <td><a name="CAS Write Latency">CAS Write Latency</a></td><td>6</td></tr>
-<tr> <td><a name="RAS to CAS Delay">RAS to CAS Delay</a></td><td>7</td></tr>
-<tr> <td><a name="RECHARGE Time">RECHARGE Time</a></td><td>7</td></tr>
-<tr> <td><a name="tRC (ns )">tRC (ns )</a></td><td>48.75</td></tr>
-<tr> <td><a name="tRASmin ( ns )">tRASmin ( ns )</a></td><td>35.0</td></tr>
-<tr> <td><a name="tFAW">tFAW</a></td><td>40.0</td></tr>
-<tr> <td><a name="ADDITIVE Latency">ADDITIVE Latency</a></td><td>0</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Training/Board Details</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="Write levelling">Write levelling</a></td><td>1</td></tr>
-<tr> <td><a name="Read gate">Read gate</a></td><td>1</td></tr>
-<tr> <td><a name="Read data eye">Read data eye</a></td><td>1</td></tr>
-<tr> <td><a name="DQS to Clock delay [0] (ns)">DQS to Clock delay [0] (ns)</a></td><td>-0.073</td></tr>
-<tr> <td><a name="DQS to Clock delay [1] (ns)">DQS to Clock delay [1] (ns)</a></td><td>-0.034</td></tr>
-<tr> <td><a name="DQS to Clock delay [2] (ns)">DQS to Clock delay [2] (ns)</a></td><td>-0.03</td></tr>
-<tr> <td><a name="DQS to Clock delay [3] (ns)">DQS to Clock delay [3] (ns)</a></td><td>-0.082</td></tr>
-<tr> <td><a name="Board delay [0] (ns)">Board delay [0] (ns)</a></td><td>0.176</td></tr>
-<tr> <td><a name="Board delay [1] (ns)">Board delay [1] (ns)</a></td><td>0.159</td></tr>
-<tr> <td><a name="Board delay [2] (ns)">Board delay [2] (ns)</a></td><td>0.162</td></tr>
-<tr> <td><a name="Board delay [3] (ns)">Board delay [3] (ns)</a></td><td>0.187</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h1><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>PLL SLCR REGISTERS</h2>
-<ul>
-<p>PLL SLCR REGISTERS</p>
-<h2>ARM PLL INIT</h2>
-<ul>
-<p>ARM PLL INIT</p>
-<li><p>Register : ARM_PLL_CFG @ 0XF8000110</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">177</td><td class="hex">177000</td></tr>
-<tr><td><b>ARM_PLL_CFG @ 0XF8000110</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1772c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">1a</td><td class="hex">1a000</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>1a000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ARM_PLL_LOCK</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : ARM_CLK_CTRL @ 0XF8000120</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >CPU_6OR4XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >CPU_3OR2XCLKACT</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">1</td><td class="hex">2000000</td></tr>
-<tr><td >CPU_2XCLKACT</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >CPU_1XCLKACT</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >CPU_PERI_CLKACT</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>ARM_CLK_CTRL @ 0XF8000120</td><td></td><td class="hex"><b>1f003f30</b></td><td></td><td class="hex"><b>1f000200</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR PLL INIT</h2>
-<ul>
-<p>DDR PLL INIT</p>
-<li><p>Register : DDR_PLL_CFG @ 0XF8000114</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1db</td><td class="hex">1db000</td></tr>
-<tr><td><b>DDR_PLL_CFG @ 0XF8000114</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1db2c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">15</td><td class="hex">15000</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>15000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_PLL_LOCK</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>2</b></td><td></td><td class="hex"><b>2</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDR_CLK_CTRL @ 0XF8000124</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_3XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DDR_2XCLKACT</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DDR_3XCLK_DIVISOR</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td >DDR_2XCLK_DIVISOR</td><td class="hex">31:26</td><td class="hex">fc000000</td><td class="hex">3</td><td class="hex">c000000</td></tr>
-<tr><td><b>DDR_CLK_CTRL @ 0XF8000124</td><td></td><td class="hex"><b>fff00003</b></td><td></td><td class="hex"><b>c200003</b></td></tr></table>
-</li>
-</ul>
-<h2>IO PLL INIT</h2>
-<ul>
-<p>IO PLL INIT</p>
-<li><p>Register : IO_PLL_CFG @ 0XF8000118</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1f4</td><td class="hex">1f4000</td></tr>
-<tr><td><b>IO_PLL_CFG @ 0XF8000118</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1f42c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">14</td><td class="hex">14000</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>14000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IO_PLL_LOCK</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>4</b></td><td></td><td class="hex"><b>4</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>CLOCK CONTROL SLCR REGISTERS</h2>
-<ul>
-<p>CLOCK CONTROL SLCR REGISTERS</p>
-<li><p>Register : DCI_CLK_CTRL @ 0XF8000128</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">34</td><td class="hex">3400</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>DCI_CLK_CTRL @ 0XF8000128</td><td></td><td class="hex"><b>3f03f01</b></td><td></td><td class="hex"><b>203401</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_RCLK_CTRL @ 0XF8000138</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GEM0_RCLK_CTRL @ 0XF8000138</td><td></td><td class="hex"><b>11</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_CLK_CTRL @ 0XF8000140</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>GEM0_CLK_CTRL @ 0XF8000140</td><td></td><td class="hex"><b>3f03f71</b></td><td></td><td class="hex"><b>100801</b></td></tr></table>
-</li>
-<li><p>Register : LQSPI_CLK_CTRL @ 0XF800014C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>LQSPI_CLK_CTRL @ 0XF800014C</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : SDIO_CLK_CTRL @ 0XF8000150</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>SDIO_CLK_CTRL @ 0XF8000150</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1401</b></td></tr></table>
-</li>
-<li><p>Register : UART_CLK_CTRL @ 0XF8000154</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>UART_CLK_CTRL @ 0XF8000154</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1403</b></td></tr></table>
-</li>
-<li><p>Register : PCAP_CLK_CTRL @ 0XF8000168</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>PCAP_CLK_CTRL @ 0XF8000168</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : FPGA0_CLK_CTRL @ 0XF8000170</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA0_CLK_CTRL @ 0XF8000170</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : FPGA1_CLK_CTRL @ 0XF8000180</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">3</td><td class="hex">30</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA1_CLK_CTRL @ 0XF8000180</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100630</b></td></tr></table>
-</li>
-<li><p>Register : FPGA2_CLK_CTRL @ 0XF8000190</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">35</td><td class="hex">3500</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>FPGA2_CLK_CTRL @ 0XF8000190</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>203520</b></td></tr></table>
-</li>
-<li><p>Register : FPGA3_CLK_CTRL @ 0XF80001A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA3_CLK_CTRL @ 0XF80001A0</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : CLK_621_TRUE @ 0XF80001C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLK_621_TRUE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>CLK_621_TRUE @ 0XF80001C4</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : APER_CLK_CTRL @ 0XF800012C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DMA_CPU_2XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >USB0_CPU_1XCLKACT</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USB1_CPU_1XCLKACT</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >GEM0_CPU_1XCLKACT</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >GEM1_CPU_1XCLKACT</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SDI0_CPU_1XCLKACT</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >SDI1_CPU_1XCLKACT</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI0_CPU_1XCLKACT</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI1_CPU_1XCLKACT</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN0_CPU_1XCLKACT</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN1_CPU_1XCLKACT</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >I2C0_CPU_1XCLKACT</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">1</td><td class="hex">40000</td></tr>
-<tr><td >I2C1_CPU_1XCLKACT</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >UART0_CPU_1XCLKACT</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >UART1_CPU_1XCLKACT</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >GPIO_CPU_1XCLKACT</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >LQSPI_CPU_1XCLKACT</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >SMC_CPU_1XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td><b>APER_CLK_CTRL @ 0XF800012C</td><td></td><td class="hex"><b>1ffcccd</b></td><td></td><td class="hex"><b>1fc044d</b></td></tr></table>
-</li>
-</ul>
-<h2>THIS SHOULD BE BLANK</h2>
-<ul>
-<p>THIS SHOULD BE BLANK</p>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></h1>
-<ul>
-<h2>DDR INITIALIZATION</h2>
-<ul>
-<p>DDR INITIALIZATION</p>
-<h2>LOCK DDR</h2>
-<ul>
-<p>LOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>80</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : Two_rank_cfg @ 0XF8006004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rfc_nom_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">7f</td><td class="hex">7f</td></tr>
-<tr><td >reg_ddrc_active_ranks</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit0</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_block</td><td class="hex">20:19</td><td class="hex">180000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_diff_rank_rd_2cycle_gap</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit1</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_open_bank</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_4bank_ram</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>Two_rank_cfg @ 0XF8006004</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>8107f</b></td></tr></table>
-</li>
-<li><p>Register : HPR_reg @ 0XF8006008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_hpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">f</td><td class="hex">f</td></tr>
-<tr><td >reg_ddrc_hpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">f</td><td class="hex">7800</td></tr>
-<tr><td >reg_ddrc_hpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">f</td><td class="hex">3c00000</td></tr>
-<tr><td><b>HPR_reg @ 0XF8006008</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>3c0780f</b></td></tr></table>
-</li>
-<li><p>Register : LPR_reg @ 0XF800600C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_lpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">2</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_lpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">8</td><td class="hex">2000000</td></tr>
-<tr><td><b>LPR_reg @ 0XF800600C</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>2001001</b></td></tr></table>
-</li>
-<li><p>Register : WR_reg @ 0XF8006010</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_w_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_w_xact_run_length</td><td class="hex">14:11</td><td class="hex">7800</td><td class="hex">8</td><td class="hex">4000</td></tr>
-<tr><td >reg_ddrc_w_max_starve_x32</td><td class="hex">25:15</td><td class="hex">3ff8000</td><td class="hex">2</td><td class="hex">10000</td></tr>
-<tr><td><b>WR_reg @ 0XF8006010</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>14001</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg0 @ 0XF8006014</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rc</td><td class="hex">5:0</td><td class="hex">3f</td><td class="hex">1a</td><td class="hex">1a</td></tr>
-<tr><td >reg_ddrc_t_rfc_min</td><td class="hex">13:6</td><td class="hex">3fc0</td><td class="hex">54</td><td class="hex">1500</td></tr>
-<tr><td >reg_ddrc_post_selfref_gap_x32</td><td class="hex">20:14</td><td class="hex">1fc000</td><td class="hex">10</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_param_reg0 @ 0XF8006014</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>4151a</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg1 @ 0XF8006018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wr2pre</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">12</td><td class="hex">12</td></tr>
-<tr><td >reg_ddrc_powerdown_to_x32</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_t_faw</td><td class="hex">15:10</td><td class="hex">fc00</td><td class="hex">15</td><td class="hex">5400</td></tr>
-<tr><td >reg_ddrc_t_ras_max</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">23</td><td class="hex">230000</td></tr>
-<tr><td >reg_ddrc_t_ras_min</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">13</td><td class="hex">4c00000</td></tr>
-<tr><td >reg_ddrc_t_cke</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">4</td><td class="hex">40000000</td></tr>
-<tr><td><b>DRAM_param_reg1 @ 0XF8006018</td><td></td><td class="hex"><b>f7ffffff</b></td><td></td><td class="hex"><b>44e354d2</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg2 @ 0XF800601C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_write_latency</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_rd2wr</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >reg_ddrc_wr2rd</td><td class="hex">14:10</td><td class="hex">7c00</td><td class="hex">e</td><td class="hex">3800</td></tr>
-<tr><td >reg_ddrc_t_xp</td><td class="hex">19:15</td><td class="hex">f8000</td><td class="hex">4</td><td class="hex">20000</td></tr>
-<tr><td >reg_ddrc_pad_pd</td><td class="hex">22:20</td><td class="hex">700000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd2pre</td><td class="hex">27:23</td><td class="hex">f800000</td><td class="hex">4</td><td class="hex">2000000</td></tr>
-<tr><td >reg_ddrc_t_rcd</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>DRAM_param_reg2 @ 0XF800601C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>720238e5</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg3 @ 0XF8006020</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ccd</td><td class="hex">4:2</td><td class="hex">1c</td><td class="hex">4</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_t_rrd</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_refresh_margin</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_rp</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">7</td><td class="hex">7000</td></tr>
-<tr><td >reg_ddrc_refresh_to_x32</td><td class="hex">20:16</td><td class="hex">1f0000</td><td class="hex">8</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_sdram</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_mobile</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_clock_stop_en</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_read_latency</td><td class="hex">28:24</td><td class="hex">1f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_mode_ddr1_ddr2</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">1</td><td class="hex">20000000</td></tr>
-<tr><td >reg_ddrc_dis_pad_pd</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_loopback</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg3 @ 0XF8006020</td><td></td><td class="hex"><b>fffffffc</b></td><td></td><td class="hex"><b>272872d0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg4 @ 0XF8006024</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_en_2t_timing_mode</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_prefer_write</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_max_rank_rd</td><td class="hex">5:2</td><td class="hex">3c</td><td class="hex">f</td><td class="hex">3c</td></tr>
-<tr><td >reg_ddrc_mr_wr</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_addr</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_data</td><td class="hex">24:9</td><td class="hex">1fffe00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_mr_wr_busy</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_type</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_rdata_valid</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg4 @ 0XF8006024</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>3c</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_init_param @ 0XF8006028</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_final_wait_x32</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_pre_ocd_x32</td><td class="hex">10:7</td><td class="hex">780</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_t_mrd</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">4</td><td class="hex">2000</td></tr>
-<tr><td><b>DRAM_init_param @ 0XF8006028</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2007</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_reg @ 0XF800602C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_emr2</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">8</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_emr3</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_EMR_reg @ 0XF800602C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_MR_reg @ 0XF8006030</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">930</td><td class="hex">930</td></tr>
-<tr><td >reg_ddrc_emr</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">4</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_EMR_MR_reg @ 0XF8006030</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>40930</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_burst8_rdwr @ 0XF8006034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_burst_rdwr</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">4</td><td class="hex">4</td></tr>
-<tr><td >reg_ddrc_pre_cke_x1024</td><td class="hex">13:4</td><td class="hex">3ff0</td><td class="hex">101</td><td class="hex">1010</td></tr>
-<tr><td >reg_ddrc_post_cke_x1024</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_ddrc_burstchop</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_burst8_rdwr @ 0XF8006034</td><td></td><td class="hex"><b>13ff3fff</b></td><td></td><td class="hex"><b>11014</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_disable_DQ @ 0XF8006038</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_force_low_pri_n</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_dq</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_debug_mode</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_level_start</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_level_start</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq0_wait_t</td><td class="hex">12:9</td><td class="hex">1e00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_disable_DQ @ 0XF8006038</td><td></td><td class="hex"><b>1fc3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_bank @ 0XF800603C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_bank_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">7</td><td class="hex">70</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b2</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">7</td><td class="hex">700</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b5</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b6</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_addr_map_bank @ 0XF800603C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>777</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_col @ 0XF8006040</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_col_b2</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b3</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b4</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b7</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b8</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b9</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b10</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b11</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">f</td><td class="hex">f0000000</td></tr>
-<tr><td><b>DRAM_addr_map_col @ 0XF8006040</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>fff00000</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_row @ 0XF8006044</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_row_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">6</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b2_11</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b12</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b13</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b14</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b15</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td><b>DRAM_addr_map_row @ 0XF8006044</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>ff66666</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_ODT_reg @ 0XF8006048</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rank0_rd_odt</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank0_wr_odt</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_rank1_rd_odt</td><td class="hex">8:6</td><td class="hex">1c0</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >reg_ddrc_rank1_wr_odt</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_phy_rd_local_odt</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_local_odt</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reg_phy_idle_local_odt</td><td class="hex">17:16</td><td class="hex">30000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td >reg_ddrc_rank2_rd_odt</td><td class="hex">20:18</td><td class="hex">1c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank2_wr_odt</td><td class="hex">23:21</td><td class="hex">e00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_rd_odt</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_wr_odt</td><td class="hex">29:27</td><td class="hex">38000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_ODT_reg @ 0XF8006048</td><td></td><td class="hex"><b>3fffffff</b></td><td></td><td class="hex"><b>3c248</b></td></tr></table>
-</li>
-<li><p>Register : phy_cmd_timeout_rddata_cpt @ 0XF8006050</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_cmd_to_data</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_cmd_to_data</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rdc_we_to_re_delay</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_disable</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_fixed_re</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_err_cnt_clr</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dis_phy_ctrl_rstn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_clk_stall_level</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_num_of_dq0</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_wrlvl_num_of_dq0</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>phy_cmd_timeout_rddata_cpt @ 0XF8006050</td><td></td><td class="hex"><b>ff0f8fff</b></td><td></td><td class="hex"><b>77010800</b></td></tr></table>
-</li>
-<li><p>Register : DLL_calib @ 0XF8006058</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dll_calib_to_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dll_calib_to_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_dis_dll_calib</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DLL_calib @ 0XF8006058</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>101</b></td></tr></table>
-</li>
-<li><p>Register : ODT_delay_hold @ 0XF800605C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rd_odt_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >reg_ddrc_wr_odt_delay</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd_odt_hold</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_hold</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>ODT_delay_hold @ 0XF800605C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>5003</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg1 @ 0XF8006060</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_pageclose</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_lpr_num_entries</td><td class="hex">6:1</td><td class="hex">7e</td><td class="hex">1f</td><td class="hex">3e</td></tr>
-<tr><td >reg_ddrc_auto_pre_en</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_refresh_update_level</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_wc</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_collision_page_opt</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_selfref_en</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ctrl_reg1 @ 0XF8006060</td><td></td><td class="hex"><b>17ff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg2 @ 0XF8006064</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_go2critical_hysteresis</td><td class="hex">12:5</td><td class="hex">1fe0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_go2critical_en</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td><b>ctrl_reg2 @ 0XF8006064</td><td></td><td class="hex"><b>21fe0</b></td><td></td><td class="hex"><b>20000</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg3 @ 0XF8006068</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wrlvl_ww</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">41</td><td class="hex">41</td></tr>
-<tr><td >reg_ddrc_rdlvl_rr</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">41</td><td class="hex">4100</td></tr>
-<tr><td >reg_ddrc_dfi_t_wlmrd</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">28</td><td class="hex">280000</td></tr>
-<tr><td><b>ctrl_reg3 @ 0XF8006068</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>284141</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg4 @ 0XF800606C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_t_ctrlupd_interval_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">10</td><td class="hex">10</td></tr>
-<tr><td >dfi_t_ctrlupd_interval_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">16</td><td class="hex">1600</td></tr>
-<tr><td><b>ctrl_reg4 @ 0XF800606C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>1610</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg5 @ 0XF8006078</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_ctrl_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_disable</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_enable</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_t_cksre</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_t_cksrx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_t_ckesr</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">4</td><td class="hex">400000</td></tr>
-<tr><td><b>ctrl_reg5 @ 0XF8006078</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>466111</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg6 @ 0XF800607C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ckpde</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_ckpdx</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >reg_ddrc_t_ckdpde</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_ckdpdx</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">2</td><td class="hex">2000</td></tr>
-<tr><td >reg_ddrc_t_ckcsx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td><b>ctrl_reg6 @ 0XF800607C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>32222</b></td></tr></table>
-</li>
-<li><p>Register : CHE_REFRESH_TIMER01 @ 0XF80060A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >refresh_timer0_start_value_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >refresh_timer1_start_value_x32</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">8</td><td class="hex">8000</td></tr>
-<tr><td><b>CHE_REFRESH_TIMER01 @ 0XF80060A0</td><td></td><td class="hex"><b>ffffff</b></td><td></td><td class="hex"><b>8000</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ @ 0XF80060A4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_auto_zq</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_ddr3</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_mod</td><td class="hex">11:2</td><td class="hex">ffc</td><td class="hex">200</td><td class="hex">800</td></tr>
-<tr><td >reg_ddrc_t_zq_long_nop</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">200</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_t_zq_short_nop</td><td class="hex">31:22</td><td class="hex">ffc00000</td><td class="hex">40</td><td class="hex">10000000</td></tr>
-<tr><td><b>CHE_T_ZQ @ 0XF80060A4</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10200802</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >t_zq_short_interval_x1024</td><td class="hex">19:0</td><td class="hex">fffff</td><td class="hex">c845</td><td class="hex">c845</td></tr>
-<tr><td >dram_rstn_x1024</td><td class="hex">27:20</td><td class="hex">ff00000</td><td class="hex">67</td><td class="hex">6700000</td></tr>
-<tr><td><b>CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>670c845</b></td></tr></table>
-</li>
-<li><p>Register : deep_pwrdwn_reg @ 0XF80060AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >deeppowerdown_en</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >deeppowerdown_to_x1024</td><td class="hex">8:1</td><td class="hex">1fe</td><td class="hex">ff</td><td class="hex">1fe</td></tr>
-<tr><td><b>deep_pwrdwn_reg @ 0XF80060AC</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>1fe</b></td></tr></table>
-</li>
-<li><p>Register : reg_2c @ 0XF80060B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_wrlvl_max_x1024</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">fff</td><td class="hex">fff</td></tr>
-<tr><td >dfi_rdlvl_max_x1024</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">fff</td><td class="hex">fff000</td></tr>
-<tr><td >ddrc_reg_twrlvl_max_error</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_trdlvl_max_error</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dfi_wr_level_en</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_dqs_gate_level</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_data_eye_train</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>reg_2c @ 0XF80060B0</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>1cffffff</b></td></tr></table>
-</li>
-<li><p>Register : reg_2d @ 0XF80060B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_2t_delay</td><td class="hex">8:0</td><td class="hex">1ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_skip_ocd</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_dis_pre_bypass</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_2d @ 0XF80060B4</td><td></td><td class="hex"><b>7ff</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : dfi_timing @ 0XF80060B8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_rddata_en</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_min</td><td class="hex">14:5</td><td class="hex">7fe0</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_max</td><td class="hex">24:15</td><td class="hex">1ff8000</td><td class="hex">40</td><td class="hex">200000</td></tr>
-<tr><td><b>dfi_timing @ 0XF80060B8</td><td></td><td class="hex"><b>1ffffff</b></td><td></td><td class="hex"><b>200066</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>3</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ECC_CORRECTED_BIT_NUM</td><td class="hex">7:1</td><td class="hex">fe</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNCORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STAT_NUM_CORR_ERR</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STAT_NUM_UNCORR_ERR</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ECC_scrub @ 0XF80060F4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_ecc_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_scrub</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td><b>ECC_scrub @ 0XF80060F4</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : phy_rcvr_enable @ 0XF8006114</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_dif_on</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dif_off</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rcvr_enable @ 0XF8006114</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config0 @ 0XF8006118</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config0 @ 0XF8006118</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config1 @ 0XF800611C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config1 @ 0XF800611C</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config2 @ 0XF8006120</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config2 @ 0XF8006120</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config3 @ 0XF8006124</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config3 @ 0XF8006124</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio0 @ 0XF800612C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8f</td><td class="hex">23c00</td></tr>
-<tr><td><b>phy_init_ratio0 @ 0XF800612C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>23c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio1 @ 0XF8006130</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8a</td><td class="hex">22800</td></tr>
-<tr><td><b>phy_init_ratio1 @ 0XF8006130</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22800</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio2 @ 0XF8006134</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8b</td><td class="hex">22c00</td></tr>
-<tr><td><b>phy_init_ratio2 @ 0XF8006134</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio3 @ 0XF8006138</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">92</td><td class="hex">24800</td></tr>
-<tr><td><b>phy_init_ratio3 @ 0XF8006138</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>24800</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg0 @ 0XF8006140</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg0 @ 0XF8006140</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg1 @ 0XF8006144</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg1 @ 0XF8006144</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg2 @ 0XF8006148</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg2 @ 0XF8006148</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg3 @ 0XF800614C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg3 @ 0XF800614C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg0 @ 0XF8006154</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">77</td><td class="hex">77</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg0 @ 0XF8006154</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>77</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg1 @ 0XF8006158</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg1 @ 0XF8006158</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg2 @ 0XF800615C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg2 @ 0XF800615C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg3 @ 0XF8006160</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">75</td><td class="hex">75</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg3 @ 0XF8006160</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>75</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg0 @ 0XF8006168</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e4</td><td class="hex">e4</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg0 @ 0XF8006168</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e4</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg1 @ 0XF800616C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">df</td><td class="hex">df</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg1 @ 0XF800616C</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>df</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg2 @ 0XF8006170</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e0</td><td class="hex">e0</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg2 @ 0XF8006170</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e0</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg3 @ 0XF8006174</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e7</td><td class="hex">e7</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg3 @ 0XF8006174</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv0 @ 0XF800617C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b7</td><td class="hex">b7</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv0 @ 0XF800617C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv1 @ 0XF8006180</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv1 @ 0XF8006180</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv2 @ 0XF8006184</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv2 @ 0XF8006184</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv3 @ 0XF8006188</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b5</td><td class="hex">b5</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv3 @ 0XF8006188</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b5</b></td></tr></table>
-</li>
-<li><p>Register : reg_64 @ 0XF8006190</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_loopback</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bl2</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_at_spd_atpg</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_enable</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_force_err</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_mode</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_invert_clkout</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_all_dq_mpr_rd_resp</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_sel_logic</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">100</td><td class="hex">40000</td></tr>
-<tr><td >reg_phy_ctrl_slave_force</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">27:21</td><td class="hex">fe00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_rank0_delays</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td >reg_phy_lpddr</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_cmd_latency</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_int_lpbk</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_64 @ 0XF8006190</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10040080</b></td></tr></table>
-</li>
-<li><p>Register : reg_65 @ 0XF8006194</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_rl_delay</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_phy_rd_rl_delay</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_dll_lock_diff</td><td class="hex">13:10</td><td class="hex">3c00</td><td class="hex">f</td><td class="hex">3c00</td></tr>
-<tr><td >reg_phy_use_wr_level</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">1</td><td class="hex">4000</td></tr>
-<tr><td >reg_phy_use_rd_dqs_gate_level</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">1</td><td class="hex">8000</td></tr>
-<tr><td >reg_phy_use_rd_data_eye_level</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_dis_calib_rst</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_65 @ 0XF8006194</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>1fc82</b></td></tr></table>
-</li>
-<li><p>Register : page_mask @ 0XF8006204</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_page_addr_mask</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>page_mask @ 0XF8006204</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port0 @ 0XF8006208</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port0 @ 0XF8006208</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port1 @ 0XF800620C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port1 @ 0XF800620C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port2 @ 0XF8006210</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port2 @ 0XF8006210</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port3 @ 0XF8006214</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port3 @ 0XF8006214</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port0 @ 0XF8006218</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port0 @ 0XF8006218</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port1 @ 0XF800621C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port1 @ 0XF800621C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port2 @ 0XF8006220</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port2 @ 0XF8006220</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port3 @ 0XF8006224</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port3 @ 0XF8006224</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl0 @ 0XF80062A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpddr2</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_per_bank_refresh</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_derate_enable</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr4_margin</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl0 @ 0XF80062A8</td><td></td><td class="hex"><b>ff7</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl1 @ 0XF80062AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr4_read_interval</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl1 @ 0XF80062AC</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl2 @ 0XF80062B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_min_stable_clock_x1</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_idle_after_reset_x32</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">12</td><td class="hex">120</td></tr>
-<tr><td >reg_ddrc_t_mrw</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>lpddr_ctrl2 @ 0XF80062B0</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>5125</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl3 @ 0XF80062B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_max_auto_init_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">a6</td><td class="hex">a6</td></tr>
-<tr><td >reg_ddrc_dev_zqinit_x32</td><td class="hex">17:8</td><td class="hex">3ff00</td><td class="hex">12</td><td class="hex">1200</td></tr>
-<tr><td><b>lpddr_ctrl3 @ 0XF80062B4</td><td></td><td class="hex"><b>3ffff</b></td><td></td><td class="hex"><b>12a6</b></td></tr></table>
-</li>
-<h2>POLL ON DCI STATUS</h2>
-<ul>
-<p>POLL ON DCI STATUS</p>
-<li><p>Register : DDRIOB_DCI_STATUS @ 0XF8000B74</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DONE</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>DDRIOB_DCI_STATUS @ 0XF8000B74</td><td></td><td class="hex"><b>2000</b></td><td></td><td class="hex"><b>2000</b></td></tr></table>
-</li>
-</ul>
-<h2>UNLOCK DDR</h2>
-<ul>
-<p>UNLOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>81</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK DDR STATUS</h2>
-<ul>
-<p>CHECK DDR STATUS</p>
-<li><p>Register : mode_sts_reg @ 0XF8006054</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ddrc_reg_operating_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>mode_sts_reg @ 0XF8006054</td><td></td><td class="hex"><b>7</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>OCM REMAPPING</h2>
-<ul>
-<p>OCM REMAPPING</p>
-<li><p>Register : GPIOB_CTRL @ 0XF8000B00</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLK_PULLUP_EN</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRSTN_PULLUP_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GPIOB_CTRL @ 0XF8000B00</td><td></td><td class="hex"><b>303</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DDRIOB SETTINGS</h2>
-<ul>
-<p>DDRIOB SETTINGS</p>
-<li><p>Register : DDRIOB_ADDR0 @ 0XF8000B40</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR0 @ 0XF8000B40</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_ADDR1 @ 0XF8000B44</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR1 @ 0XF8000B44</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_CLOCK @ 0XF8000B58</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_CLOCK @ 0XF8000B58</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DDR_CTRL @ 0XF8000B6C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_INT_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">4:1</td><td class="hex">1e</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_EXT_EN</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >REFIO_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >REFIO_TEST</td><td class="hex">11:10</td><td class="hex">c00</td><td class="hex">3</td><td class="hex">c00</td></tr>
-<tr><td >REFIO_PULLUP_EN</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DRST_B_PULLUP_EN</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CKE_PULLUP_EN</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DDR_CTRL @ 0XF8000B6C</td><td></td><td class="hex"><b>7fff</b></td><td></td><td class="hex"><b>e60</b></td></tr></table>
-</li>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>21</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >ENABLE</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >VRP_TRI</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_TRI</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRP_OUT</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td >NREF_OPT1</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT2</td><td class="hex">10:8</td><td class="hex">700</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT4</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >PREF_OPT1</td><td class="hex">16:14</td><td class="hex">1c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PREF_OPT2</td><td class="hex">19:17</td><td class="hex">e0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UPDATE_CONTROL</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INIT_COMPLETE</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_CLK</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLN</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLP</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_RST</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INT_DCI_EN</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>7ffffff</b></td><td></td><td class="hex"><b>823</b></td></tr></table>
-</li>
-</ul>
-<h2>MIO PROGRAMMING</h2>
-<ul>
-<p>MIO PROGRAMMING</p>
-<li><p>Register : MIO_PIN_00 @ 0XF8000700</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_00 @ 0XF8000700</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_01 @ 0XF8000704</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_01 @ 0XF8000704</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_02 @ 0XF8000708</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_02 @ 0XF8000708</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_03 @ 0XF800070C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_03 @ 0XF800070C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_04 @ 0XF8000710</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_04 @ 0XF8000710</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_05 @ 0XF8000714</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_05 @ 0XF8000714</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_06 @ 0XF8000718</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_06 @ 0XF8000718</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_07 @ 0XF800071C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_07 @ 0XF800071C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_08 @ 0XF8000720</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_08 @ 0XF8000720</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_09 @ 0XF8000724</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_09 @ 0XF8000724</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_10 @ 0XF8000728</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_10 @ 0XF8000728</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_11 @ 0XF800072C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_11 @ 0XF800072C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_12 @ 0XF8000730</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_12 @ 0XF8000730</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_13 @ 0XF8000734</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_13 @ 0XF8000734</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_14 @ 0XF8000738</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_14 @ 0XF8000738</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_15 @ 0XF800073C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_15 @ 0XF800073C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_16 @ 0XF8000740</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_16 @ 0XF8000740</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_17 @ 0XF8000744</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_17 @ 0XF8000744</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_18 @ 0XF8000748</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_18 @ 0XF8000748</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_19 @ 0XF800074C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_19 @ 0XF800074C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_20 @ 0XF8000750</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_20 @ 0XF8000750</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_21 @ 0XF8000754</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_21 @ 0XF8000754</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_22 @ 0XF8000758</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_22 @ 0XF8000758</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_23 @ 0XF800075C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_23 @ 0XF800075C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_24 @ 0XF8000760</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_24 @ 0XF8000760</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_25 @ 0XF8000764</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_25 @ 0XF8000764</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_26 @ 0XF8000768</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_26 @ 0XF8000768</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_27 @ 0XF800076C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_27 @ 0XF800076C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_28 @ 0XF8000770</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_28 @ 0XF8000770</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_29 @ 0XF8000774</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_29 @ 0XF8000774</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_30 @ 0XF8000778</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_30 @ 0XF8000778</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_31 @ 0XF800077C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_31 @ 0XF800077C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_32 @ 0XF8000780</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_32 @ 0XF8000780</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_33 @ 0XF8000784</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_33 @ 0XF8000784</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_34 @ 0XF8000788</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_34 @ 0XF8000788</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_35 @ 0XF800078C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_35 @ 0XF800078C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_36 @ 0XF8000790</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_36 @ 0XF8000790</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_37 @ 0XF8000794</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_37 @ 0XF8000794</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_38 @ 0XF8000798</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_38 @ 0XF8000798</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_39 @ 0XF800079C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_39 @ 0XF800079C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_40 @ 0XF80007A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_40 @ 0XF80007A0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_41 @ 0XF80007A4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_41 @ 0XF80007A4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_42 @ 0XF80007A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_42 @ 0XF80007A8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_43 @ 0XF80007AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_43 @ 0XF80007AC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_44 @ 0XF80007B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_44 @ 0XF80007B0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_45 @ 0XF80007B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_45 @ 0XF80007B4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_46 @ 0XF80007B8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_46 @ 0XF80007B8</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_47 @ 0XF80007BC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_47 @ 0XF80007BC</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_48 @ 0XF80007C0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_48 @ 0XF80007C0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e0</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_49 @ 0XF80007C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_49 @ 0XF80007C4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e1</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_50 @ 0XF80007C8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_50 @ 0XF80007C8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_51 @ 0XF80007CC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_51 @ 0XF80007CC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_52 @ 0XF80007D0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_52 @ 0XF80007D0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_53 @ 0XF80007D4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_53 @ 0XF80007D4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : SD0_WP_CD_SEL @ 0XF8000830</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SDIO0_CD_SEL</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">2f</td><td class="hex">2f0000</td></tr>
-<tr><td><b>SD0_WP_CD_SEL @ 0XF8000830</td><td></td><td class="hex"><b>3f0000</b></td><td></td><td class="hex"><b>2f0000</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR TERM/IBUF_DISABLE_MODE SETTINGS</h2>
-<ul>
-<p>DDR TERM/IBUF_DISABLE_MODE SETTINGS</p>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-<h2>SRAM/NOR SET OPMODE</h2>
-<ul>
-<p>SRAM/NOR SET OPMODE</p>
-</ul>
-<h2>UART REGISTERS</h2>
-<ul>
-<p>UART REGISTERS</p>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0001034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0001034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0001018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0001018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0001000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0001000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0001004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0001004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0000034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0000034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0000018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0000018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0000000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0000000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0000004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<h2>QSPI REGISTERS</h2>
-<ul>
-<p>QSPI REGISTERS</p>
-<li><p>Register : Config_reg @ 0XE000D000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Holdb_dr</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>Config_reg @ 0XE000D000</td><td></td><td class="hex"><b>80000</b></td><td></td><td class="hex"><b>80000</b></td></tr></table>
-</li>
-</ul>
-<h2>PL POWER ON RESET REGISTERS</h2>
-<ul>
-<p>PL POWER ON RESET REGISTERS</p>
-<li><p>Register : CTRL @ 0XF8007000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PCFG_POR_CNT_4K</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CTRL @ 0XF8007000</td><td></td><td class="hex"><b>20000000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>SMC TIMING CALCULATION REGISTER UPDATE</h2>
-<ul>
-<p>SMC TIMING CALCULATION REGISTER UPDATE</p>
-<h2>NAND SET CYCLE</h2>
-<ul>
-<p>NAND SET CYCLE</p>
-</ul>
-<h2>OPMODE</h2>
-<ul>
-<p>OPMODE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>SRAM/NOR CS0 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS0 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS0 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS0 BASE ADDRESS</p>
-</ul>
-<h2>SRAM/NOR CS1 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS1 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS1 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS1 BASE ADDRESS</p>
-</ul>
-<h2>USB RESET</h2>
-<ul>
-<p>USB RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-<li><p>Register : DIRM_1 @ 0XE000A244</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DIRECTION_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>DIRM_1 @ 0XE000A244</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-<li><p>Register : OEN_1 @ 0XE000A248</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >OP_ENABLE_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>OEN_1 @ 0XE000A248</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff0000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>ENET RESET</h2>
-<ul>
-<p>ENET RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>I2C RESET</h2>
-<ul>
-<p>I2C RESET</p>
-<h2>DIR MODE GPIO BANK0</h2>
-<ul>
-<p>DIR MODE GPIO BANK0</p>
-</ul>
-<h2>DIR MODE GPIO BANK1</h2>
-<ul>
-<p>DIR MODE GPIO BANK1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>ENABLING LEVEL SHIFTER</h2>
-<ul>
-<p>ENABLING LEVEL SHIFTER</p>
-<li><p>Register : LVL_SHFTR_EN @ 0XF8000900</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >USER_INP_ICT_EN_0</td><td class="hex">1:0</td><td class="hex">3</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >USER_INP_ICT_EN_1</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">3</td><td class="hex">c</td></tr>
-<tr><td><b>LVL_SHFTR_EN @ 0XF8000900</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>f</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 1</h2>
-<ul>
-<p>FPGA RESETS TO 1</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">7f</td><td class="hex">fe000000</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">3</td><td class="hex">c0000</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">f</td><td class="hex">f0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>ffffffff</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 0</h2>
-<ul>
-<p>FPGA RESETS TO 0</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>AFI REGISTERS</h2>
-<ul>
-<p>AFI REGISTERS</p>
-<h2>AFI0 REGISTERS</h2>
-<ul>
-<p>AFI0 REGISTERS</p>
-</ul>
-<h2>AFI1 REGISTERS</h2>
-<ul>
-<p>AFI1 REGISTERS</p>
-</ul>
-<h2>AFI2 REGISTERS</h2>
-<ul>
-<p>AFI2 REGISTERS</p>
-</ul>
-<h2>AFI3 REGISTERS</h2>
-<ul>
-<p>AFI3 REGISTERS</p>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-</body>
-</html>
-<!DOCTYPE html>
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8"/>
-<title>Zynq PS configuration detail</title>
-<style type="text/css">
-.hex {font-family:monospace ; text-align : right}
-td { min-width : 80px ; }
-</style>
-</head>
-<body>
-<p style="height: 7px">Following peripherals are selected in the design. </p>
-<p><br /></p>
-<h2><a name="Top">Peripheral Selected</a></h2>
-<ul>
-<li>Quad SPI Flash</li>
-<li>Enet 0</li>
-<li>USB 0</li>
-<li>SD 0</li>
-<li>UART 0</li>
-<li>UART 1</li>
-<li>I2C 0</li>
-<li>I2C 1</li>
-<li>GPIO</li>
-</ul>
-<p>To see detailed information please follow below links:</p>
-<ul>
-<li><a href="#MIOConfTab">MIO Configuration Table</a></li>
-<li><a href="#ZynqPerTab">Zynq Peripheral Configuration</a></li>
-<li><a href="#DDRInfoTab">DDR Configuration Information</a></li>
-<li>SLCR settings</li>
-<ul>
-<li><a href="#ps7_pll_init_data">PLL Init Data</a></li>
-<li><a href="#ps7_clock_init_data">Clock Init Data</a></li>
-<li><a href="#ps7_ddr_init_data">DDR Init Data</a></li>
-<li><a href="#ps7_mio_init_data">MIO Init Data</a></li>
-</ul>
-</ul>
-<h2><a name="MIOConfTab">MIO configuration Table</a></h2>
-<ul><table border="1">
-<thead><tr> <th>MIO Pin</th> <th>Peripheral</th> <th>Signal</th> <th>IO type</th> <th>Speed</th> <th>Pullup</th> <th>Direction</th> </tr></thead>
-<tr bgcolor="#FA4A46"><td><a name="MIO 0">MIO 0</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[0]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 1">MIO 1</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_ss_b</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 2">MIO 2</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[0]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 3">MIO 3</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[1]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 4">MIO 4</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[2]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 5">MIO 5</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[3]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 6">MIO 6</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_sclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 7">MIO 7</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[7]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 8">MIO 8</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi_fbclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 9">MIO 9</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[9]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 10">MIO 10</a></td><td><a href="#I2C 0">I2C 0</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 11">MIO 11</a></td><td><a href="#I2C 0">I2C 0</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 12">MIO 12</a></td><td><a href="#I2C 1">I2C 1</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 13">MIO 13</a></td><td><a href="#I2C 1">I2C 1</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 14">MIO 14</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[14]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 15">MIO 15</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[15]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 16">MIO 16</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 17">MIO 17</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 18">MIO 18</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 19">MIO 19</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 20">MIO 20</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 21">MIO 21</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 22">MIO 22</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 23">MIO 23</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 24">MIO 24</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 25">MIO 25</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 26">MIO 26</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 27">MIO 27</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 28">MIO 28</a></td><td><a href="#USB 0">USB 0</a></td><td>data[4]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 29">MIO 29</a></td><td><a href="#USB 0">USB 0</a></td><td>dir</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 30">MIO 30</a></td><td><a href="#USB 0">USB 0</a></td><td>stp</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 31">MIO 31</a></td><td><a href="#USB 0">USB 0</a></td><td>nxt</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 32">MIO 32</a></td><td><a href="#USB 0">USB 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 33">MIO 33</a></td><td><a href="#USB 0">USB 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 34">MIO 34</a></td><td><a href="#USB 0">USB 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 35">MIO 35</a></td><td><a href="#USB 0">USB 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 36">MIO 36</a></td><td><a href="#USB 0">USB 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 37">MIO 37</a></td><td><a href="#USB 0">USB 0</a></td><td>data[5]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 38">MIO 38</a></td><td><a href="#USB 0">USB 0</a></td><td>data[6]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 39">MIO 39</a></td><td><a href="#USB 0">USB 0</a></td><td>data[7]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 40">MIO 40</a></td><td><a href="#SD 0">SD 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 41">MIO 41</a></td><td><a href="#SD 0">SD 0</a></td><td>cmd</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 42">MIO 42</a></td><td><a href="#SD 0">SD 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 43">MIO 43</a></td><td><a href="#SD 0">SD 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 44">MIO 44</a></td><td><a href="#SD 0">SD 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 45">MIO 45</a></td><td><a href="#SD 0">SD 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 46">MIO 46</a></td><td><a href="#USB 0">USB 0</a></td><td>reset</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 47">MIO 47</a></td><td><a href="#SD 0">SD 0</a></td><td>cd</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 48">MIO 48</a></td><td><a href="#UART 1">UART 1</a></td><td>tx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 49">MIO 49</a></td><td><a href="#UART 1">UART 1</a></td><td>rx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 50">MIO 50</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[50]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 51">MIO 51</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[51]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 52">MIO 52</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdc</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 53">MIO 53</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdio</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="ZynqPerTab">Zynq Peripheral Configuration</a></h2>
-<ul><table border="1">
-<tr><thead> <th>Peripheral</th> <th>Signal Group</th> <th>Signal</th> <th>MIO</th> </thead></tr>
-<tr bgcolor="#FAEBD7"><td><a name="Quad SPI Flash" >Quad SPI Flash</a></td> <td></td><td></td><td>MIO 1 .. 6</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (4 bit) </td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (Parallel 8 bit)</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Feedback Clk</td><td></td><td>MIO 8</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="nor" >SRAM/NOR Flash</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFE4C4"><td><a name="nand" >NAND Flash</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DEB887"><td><a name="Enet 0" >Enet 0</a></td> <td></td><td></td><td>MIO 16 .. 27</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_clk</td><td><a href="#MIO 16">MIO 16</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[3]</td><td><a href="#MIO 20">MIO 20</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[2]</td><td><a href="#MIO 19">MIO 19</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[1]</td><td><a href="#MIO 18">MIO 18</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[0]</td><td><a href="#MIO 17">MIO 17</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_ctl</td><td><a href="#MIO 21">MIO 21</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_clk</td><td><a href="#MIO 22">MIO 22</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[3]</td><td><a href="#MIO 26">MIO 26</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[2]</td><td><a href="#MIO 25">MIO 25</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[1]</td><td><a href="#MIO 24">MIO 24</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[0]</td><td><a href="#MIO 23">MIO 23</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_ctl</td><td><a href="#MIO 27">MIO 27</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td>MDIO</td><td></td><td>MIO 52 .. 53</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdc</td><td><a href="#MIO 52">MIO 52</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdio</td><td><a href="#MIO 53">MIO 53</a></td></tr>
-<tr bgcolor="#DEB887"><td><a name="enet1" >Enet 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="USB 0" >USB 0</a></td> <td></td><td></td><td>MIO 28 .. 39</td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>clk</td><td><a href="#MIO 36">MIO 36</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>dir</td><td><a href="#MIO 29">MIO 29</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>stp</td><td><a href="#MIO 30">MIO 30</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>nxt</td><td><a href="#MIO 31">MIO 31</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[0]</td><td><a href="#MIO 32">MIO 32</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[1]</td><td><a href="#MIO 33">MIO 33</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[2]</td><td><a href="#MIO 34">MIO 34</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[3]</td><td><a href="#MIO 35">MIO 35</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[4]</td><td><a href="#MIO 28">MIO 28</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[5]</td><td><a href="#MIO 37">MIO 37</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[6]</td><td><a href="#MIO 38">MIO 38</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[7]</td><td><a href="#MIO 39">MIO 39</a></td></tr>
-<tr bgcolor="#7FFF00"><td><a name="usb1" >USB 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="SD 0" >SD 0</a></td> <td></td><td></td><td>MIO 40 .. 45</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>CD</td><td></td><td>MIO 47</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>WP</td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>Power</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="sd1" >SD 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 0" >UART 0</a></td> <td></td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 1" >UART 1</a></td> <td></td><td></td><td>MIO 48 .. 49</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td><a href="#MIO 49">MIO 49</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td><a href="#MIO 48">MIO 48</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem Signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 0" >I2C 0</a></td> <td></td><td></td><td>MIO 10 .. 11</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 10">MIO 10</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 11">MIO 11</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 1" >I2C 1</a></td> <td></td><td></td><td>MIO 12 .. 13</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 12">MIO 12</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 13">MIO 13</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi0" >SPI 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi1" >SPI 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can0" >CAN 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can1" >CAN 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#ADD8E6"><td><a name="trace" >Trace</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc0" >Timer 0</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc1" >Timer 1</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FF6347"><td><a name="wdt" >Watchdog</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#EE82EE"><td><a name="pjtag" >PJTAG</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="GPIO" >GPIO</a></td> <td></td><td></td><td>MIO</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="mode" >Mode</a></td> <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="vcfg" >VCfg</a></td> <td></td><td></td><td>Disabled</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="DDRInfoTab">DDR Memory information</a></h2>
-<h3><a name="DDRInfoTab">DDR Controller Configuration</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="Enable DDR">Enable DDR</a></td><td>1</td></tr>
-<tr> <td><a name="Memory Type">Memory Type</a></td><td>DDR 3</td></tr>
-<tr> <td><a name="Memory Part">Memory Part</a></td><td>MT41K128M16 JT-125</td></tr>
-<tr> <td><a name="DRAM bus width">DRAM bus width</a></td><td>32 Bit</td></tr>
-<tr> <td><a name="ECC">ECC</a></td><td>Disabled</td></tr>
-<tr> <td><a name="BURST Length (lppdr only)">BURST Length (lppdr only)</a></td><td>8</td></tr>
-<tr> <td><a name="Internal Vref">Internal Vref</a></td><td>0</td></tr>
-<tr> <td><a name="Operating Frequency (MHz)">Operating Frequency (MHz)</a></td><td>525.000000</td></tr>
-<tr> <td><a name="HIGH temperature">HIGH temperature</a></td><td>Normal (0-85)</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Memory Part Configuration</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="DRAM IC bus width">DRAM IC bus width</a></td><td>16 Bits</td></tr>
-<tr> <td><a name="DRAM Device Capacity">DRAM Device Capacity</a></td><td>2048 MBits</td></tr>
-<tr> <td><a name="Speed Bin">Speed Bin</a></td><td>DDR3_1066F</td></tr>
-<tr> <td><a name="BANK Address Count">BANK Address Count</a></td><td>3</td></tr>
-<tr> <td><a name="ROW Address Count">ROW Address Count</a></td><td>14</td></tr>
-<tr> <td><a name="COLUMN Address Count">COLUMN Address Count</a></td><td>10</td></tr>
-<tr> <td><a name="CAS Latency">CAS Latency</a></td><td>7</td></tr>
-<tr> <td><a name="CAS Write Latency">CAS Write Latency</a></td><td>6</td></tr>
-<tr> <td><a name="RAS to CAS Delay">RAS to CAS Delay</a></td><td>7</td></tr>
-<tr> <td><a name="RECHARGE Time">RECHARGE Time</a></td><td>7</td></tr>
-<tr> <td><a name="tRC (ns )">tRC (ns )</a></td><td>48.75</td></tr>
-<tr> <td><a name="tRASmin ( ns )">tRASmin ( ns )</a></td><td>35.0</td></tr>
-<tr> <td><a name="tFAW">tFAW</a></td><td>40.0</td></tr>
-<tr> <td><a name="ADDITIVE Latency">ADDITIVE Latency</a></td><td>0</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Training/Board Details</a></h3>
-<ul><table border="1">
-<tr><thead> <th>Parameter</th> <th>Value</th> </thead></tr>
-<tr> <td><a name="Write levelling">Write levelling</a></td><td>1</td></tr>
-<tr> <td><a name="Read gate">Read gate</a></td><td>1</td></tr>
-<tr> <td><a name="Read data eye">Read data eye</a></td><td>1</td></tr>
-<tr> <td><a name="DQS to Clock delay [0] (ns)">DQS to Clock delay [0] (ns)</a></td><td>-0.073</td></tr>
-<tr> <td><a name="DQS to Clock delay [1] (ns)">DQS to Clock delay [1] (ns)</a></td><td>-0.034</td></tr>
-<tr> <td><a name="DQS to Clock delay [2] (ns)">DQS to Clock delay [2] (ns)</a></td><td>-0.03</td></tr>
-<tr> <td><a name="DQS to Clock delay [3] (ns)">DQS to Clock delay [3] (ns)</a></td><td>-0.082</td></tr>
-<tr> <td><a name="Board delay [0] (ns)">Board delay [0] (ns)</a></td><td>0.176</td></tr>
-<tr> <td><a name="Board delay [1] (ns)">Board delay [1] (ns)</a></td><td>0.159</td></tr>
-<tr> <td><a name="Board delay [2] (ns)">Board delay [2] (ns)</a></td><td>0.162</td></tr>
-<tr> <td><a name="Board delay [3] (ns)">Board delay [3] (ns)</a></td><td>0.187</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h1><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>PLL SLCR REGISTERS</h2>
-<ul>
-<p>PLL SLCR REGISTERS</p>
-<h2>ARM PLL INIT</h2>
-<ul>
-<p>ARM PLL INIT</p>
-<li><p>Register : ARM_PLL_CFG @ 0XF8000110</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">177</td><td class="hex">177000</td></tr>
-<tr><td><b>ARM_PLL_CFG @ 0XF8000110</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1772c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">1a</td><td class="hex">1a000</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>1a000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ARM_PLL_LOCK</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : ARM_CLK_CTRL @ 0XF8000120</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >CPU_6OR4XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >CPU_3OR2XCLKACT</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">1</td><td class="hex">2000000</td></tr>
-<tr><td >CPU_2XCLKACT</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >CPU_1XCLKACT</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >CPU_PERI_CLKACT</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>ARM_CLK_CTRL @ 0XF8000120</td><td></td><td class="hex"><b>1f003f30</b></td><td></td><td class="hex"><b>1f000200</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR PLL INIT</h2>
-<ul>
-<p>DDR PLL INIT</p>
-<li><p>Register : DDR_PLL_CFG @ 0XF8000114</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1db</td><td class="hex">1db000</td></tr>
-<tr><td><b>DDR_PLL_CFG @ 0XF8000114</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1db2c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">15</td><td class="hex">15000</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>15000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_PLL_LOCK</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>2</b></td><td></td><td class="hex"><b>2</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDR_CLK_CTRL @ 0XF8000124</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_3XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DDR_2XCLKACT</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DDR_3XCLK_DIVISOR</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td >DDR_2XCLK_DIVISOR</td><td class="hex">31:26</td><td class="hex">fc000000</td><td class="hex">3</td><td class="hex">c000000</td></tr>
-<tr><td><b>DDR_CLK_CTRL @ 0XF8000124</td><td></td><td class="hex"><b>fff00003</b></td><td></td><td class="hex"><b>c200003</b></td></tr></table>
-</li>
-</ul>
-<h2>IO PLL INIT</h2>
-<ul>
-<p>IO PLL INIT</p>
-<li><p>Register : IO_PLL_CFG @ 0XF8000118</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1f4</td><td class="hex">1f4000</td></tr>
-<tr><td><b>IO_PLL_CFG @ 0XF8000118</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1f42c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">14</td><td class="hex">14000</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>14000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IO_PLL_LOCK</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>4</b></td><td></td><td class="hex"><b>4</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>CLOCK CONTROL SLCR REGISTERS</h2>
-<ul>
-<p>CLOCK CONTROL SLCR REGISTERS</p>
-<li><p>Register : DCI_CLK_CTRL @ 0XF8000128</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">34</td><td class="hex">3400</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>DCI_CLK_CTRL @ 0XF8000128</td><td></td><td class="hex"><b>3f03f01</b></td><td></td><td class="hex"><b>203401</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_RCLK_CTRL @ 0XF8000138</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GEM0_RCLK_CTRL @ 0XF8000138</td><td></td><td class="hex"><b>11</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_CLK_CTRL @ 0XF8000140</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>GEM0_CLK_CTRL @ 0XF8000140</td><td></td><td class="hex"><b>3f03f71</b></td><td></td><td class="hex"><b>100801</b></td></tr></table>
-</li>
-<li><p>Register : LQSPI_CLK_CTRL @ 0XF800014C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>LQSPI_CLK_CTRL @ 0XF800014C</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : SDIO_CLK_CTRL @ 0XF8000150</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>SDIO_CLK_CTRL @ 0XF8000150</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1401</b></td></tr></table>
-</li>
-<li><p>Register : UART_CLK_CTRL @ 0XF8000154</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>UART_CLK_CTRL @ 0XF8000154</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1403</b></td></tr></table>
-</li>
-<li><p>Register : PCAP_CLK_CTRL @ 0XF8000168</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>PCAP_CLK_CTRL @ 0XF8000168</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : FPGA0_CLK_CTRL @ 0XF8000170</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA0_CLK_CTRL @ 0XF8000170</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : FPGA1_CLK_CTRL @ 0XF8000180</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">3</td><td class="hex">30</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA1_CLK_CTRL @ 0XF8000180</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100630</b></td></tr></table>
-</li>
-<li><p>Register : FPGA2_CLK_CTRL @ 0XF8000190</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">35</td><td class="hex">3500</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>FPGA2_CLK_CTRL @ 0XF8000190</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>203520</b></td></tr></table>
-</li>
-<li><p>Register : FPGA3_CLK_CTRL @ 0XF80001A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA3_CLK_CTRL @ 0XF80001A0</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : CLK_621_TRUE @ 0XF80001C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLK_621_TRUE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>CLK_621_TRUE @ 0XF80001C4</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : APER_CLK_CTRL @ 0XF800012C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DMA_CPU_2XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >USB0_CPU_1XCLKACT</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USB1_CPU_1XCLKACT</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >GEM0_CPU_1XCLKACT</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >GEM1_CPU_1XCLKACT</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SDI0_CPU_1XCLKACT</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >SDI1_CPU_1XCLKACT</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI0_CPU_1XCLKACT</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI1_CPU_1XCLKACT</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN0_CPU_1XCLKACT</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN1_CPU_1XCLKACT</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >I2C0_CPU_1XCLKACT</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">1</td><td class="hex">40000</td></tr>
-<tr><td >I2C1_CPU_1XCLKACT</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >UART0_CPU_1XCLKACT</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >UART1_CPU_1XCLKACT</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >GPIO_CPU_1XCLKACT</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >LQSPI_CPU_1XCLKACT</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >SMC_CPU_1XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td><b>APER_CLK_CTRL @ 0XF800012C</td><td></td><td class="hex"><b>1ffcccd</b></td><td></td><td class="hex"><b>1fc044d</b></td></tr></table>
-</li>
-</ul>
-<h2>THIS SHOULD BE BLANK</h2>
-<ul>
-<p>THIS SHOULD BE BLANK</p>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></h1>
-<ul>
-<h2>DDR INITIALIZATION</h2>
-<ul>
-<p>DDR INITIALIZATION</p>
-<h2>LOCK DDR</h2>
-<ul>
-<p>LOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>80</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : Two_rank_cfg @ 0XF8006004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rfc_nom_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">7f</td><td class="hex">7f</td></tr>
-<tr><td >reserved_reg_ddrc_active_ranks</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit0</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>Two_rank_cfg @ 0XF8006004</td><td></td><td class="hex"><b>7ffff</b></td><td></td><td class="hex"><b>107f</b></td></tr></table>
-</li>
-<li><p>Register : HPR_reg @ 0XF8006008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_hpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">f</td><td class="hex">f</td></tr>
-<tr><td >reg_ddrc_hpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">f</td><td class="hex">7800</td></tr>
-<tr><td >reg_ddrc_hpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">f</td><td class="hex">3c00000</td></tr>
-<tr><td><b>HPR_reg @ 0XF8006008</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>3c0780f</b></td></tr></table>
-</li>
-<li><p>Register : LPR_reg @ 0XF800600C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_lpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">2</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_lpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">8</td><td class="hex">2000000</td></tr>
-<tr><td><b>LPR_reg @ 0XF800600C</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>2001001</b></td></tr></table>
-</li>
-<li><p>Register : WR_reg @ 0XF8006010</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_w_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_w_xact_run_length</td><td class="hex">14:11</td><td class="hex">7800</td><td class="hex">8</td><td class="hex">4000</td></tr>
-<tr><td >reg_ddrc_w_max_starve_x32</td><td class="hex">25:15</td><td class="hex">3ff8000</td><td class="hex">2</td><td class="hex">10000</td></tr>
-<tr><td><b>WR_reg @ 0XF8006010</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>14001</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg0 @ 0XF8006014</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rc</td><td class="hex">5:0</td><td class="hex">3f</td><td class="hex">1a</td><td class="hex">1a</td></tr>
-<tr><td >reg_ddrc_t_rfc_min</td><td class="hex">13:6</td><td class="hex">3fc0</td><td class="hex">54</td><td class="hex">1500</td></tr>
-<tr><td >reg_ddrc_post_selfref_gap_x32</td><td class="hex">20:14</td><td class="hex">1fc000</td><td class="hex">10</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_param_reg0 @ 0XF8006014</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>4151a</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg1 @ 0XF8006018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wr2pre</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">12</td><td class="hex">12</td></tr>
-<tr><td >reg_ddrc_powerdown_to_x32</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_t_faw</td><td class="hex">15:10</td><td class="hex">fc00</td><td class="hex">15</td><td class="hex">5400</td></tr>
-<tr><td >reg_ddrc_t_ras_max</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">23</td><td class="hex">230000</td></tr>
-<tr><td >reg_ddrc_t_ras_min</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">13</td><td class="hex">4c00000</td></tr>
-<tr><td >reg_ddrc_t_cke</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">4</td><td class="hex">40000000</td></tr>
-<tr><td><b>DRAM_param_reg1 @ 0XF8006018</td><td></td><td class="hex"><b>f7ffffff</b></td><td></td><td class="hex"><b>44e354d2</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg2 @ 0XF800601C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_write_latency</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_rd2wr</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >reg_ddrc_wr2rd</td><td class="hex">14:10</td><td class="hex">7c00</td><td class="hex">e</td><td class="hex">3800</td></tr>
-<tr><td >reg_ddrc_t_xp</td><td class="hex">19:15</td><td class="hex">f8000</td><td class="hex">4</td><td class="hex">20000</td></tr>
-<tr><td >reg_ddrc_pad_pd</td><td class="hex">22:20</td><td class="hex">700000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd2pre</td><td class="hex">27:23</td><td class="hex">f800000</td><td class="hex">4</td><td class="hex">2000000</td></tr>
-<tr><td >reg_ddrc_t_rcd</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>DRAM_param_reg2 @ 0XF800601C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>720238e5</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg3 @ 0XF8006020</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ccd</td><td class="hex">4:2</td><td class="hex">1c</td><td class="hex">4</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_t_rrd</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_refresh_margin</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_rp</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">7</td><td class="hex">7000</td></tr>
-<tr><td >reg_ddrc_refresh_to_x32</td><td class="hex">20:16</td><td class="hex">1f0000</td><td class="hex">8</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_mobile</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_en_dfi_dram_clk_disable</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_read_latency</td><td class="hex">28:24</td><td class="hex">1f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_mode_ddr1_ddr2</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">1</td><td class="hex">20000000</td></tr>
-<tr><td >reg_ddrc_dis_pad_pd</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg3 @ 0XF8006020</td><td></td><td class="hex"><b>7fdffffc</b></td><td></td><td class="hex"><b>270872d0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg4 @ 0XF8006024</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_en_2t_timing_mode</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_prefer_write</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_wr</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_addr</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_data</td><td class="hex">24:9</td><td class="hex">1fffe00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_mr_wr_busy</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_type</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_rdata_valid</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg4 @ 0XF8006024</td><td></td><td class="hex"><b>fffffc3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_init_param @ 0XF8006028</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_final_wait_x32</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_pre_ocd_x32</td><td class="hex">10:7</td><td class="hex">780</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_t_mrd</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">4</td><td class="hex">2000</td></tr>
-<tr><td><b>DRAM_init_param @ 0XF8006028</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2007</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_reg @ 0XF800602C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_emr2</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">8</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_emr3</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_EMR_reg @ 0XF800602C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_MR_reg @ 0XF8006030</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">930</td><td class="hex">930</td></tr>
-<tr><td >reg_ddrc_emr</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">4</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_EMR_MR_reg @ 0XF8006030</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>40930</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_burst8_rdwr @ 0XF8006034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_burst_rdwr</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">4</td><td class="hex">4</td></tr>
-<tr><td >reg_ddrc_pre_cke_x1024</td><td class="hex">13:4</td><td class="hex">3ff0</td><td class="hex">101</td><td class="hex">1010</td></tr>
-<tr><td >reg_ddrc_post_cke_x1024</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_ddrc_burstchop</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_burst8_rdwr @ 0XF8006034</td><td></td><td class="hex"><b>13ff3fff</b></td><td></td><td class="hex"><b>11014</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_disable_DQ @ 0XF8006038</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_force_low_pri_n</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_dq</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_disable_DQ @ 0XF8006038</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_bank @ 0XF800603C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_bank_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">7</td><td class="hex">70</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b2</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">7</td><td class="hex">700</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b5</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b6</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_addr_map_bank @ 0XF800603C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>777</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_col @ 0XF8006040</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_col_b2</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b3</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b4</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b7</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b8</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b9</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b10</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b11</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">f</td><td class="hex">f0000000</td></tr>
-<tr><td><b>DRAM_addr_map_col @ 0XF8006040</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>fff00000</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_row @ 0XF8006044</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_row_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">6</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b2_11</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b12</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b13</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b14</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b15</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td><b>DRAM_addr_map_row @ 0XF8006044</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>ff66666</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_ODT_reg @ 0XF8006048</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_local_odt</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_local_odt</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reg_phy_idle_local_odt</td><td class="hex">17:16</td><td class="hex">30000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td><b>DRAM_ODT_reg @ 0XF8006048</td><td></td><td class="hex"><b>3f000</b></td><td></td><td class="hex"><b>3c000</b></td></tr></table>
-</li>
-<li><p>Register : phy_cmd_timeout_rddata_cpt @ 0XF8006050</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_cmd_to_data</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_cmd_to_data</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rdc_we_to_re_delay</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_disable</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_fixed_re</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_err_cnt_clr</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dis_phy_ctrl_rstn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_clk_stall_level</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_num_of_dq0</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_wrlvl_num_of_dq0</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>phy_cmd_timeout_rddata_cpt @ 0XF8006050</td><td></td><td class="hex"><b>ff0f8fff</b></td><td></td><td class="hex"><b>77010800</b></td></tr></table>
-</li>
-<li><p>Register : DLL_calib @ 0XF8006058</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_dll_calib</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DLL_calib @ 0XF8006058</td><td></td><td class="hex"><b>10000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ODT_delay_hold @ 0XF800605C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rd_odt_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >reg_ddrc_wr_odt_delay</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd_odt_hold</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_hold</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>ODT_delay_hold @ 0XF800605C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>5003</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg1 @ 0XF8006060</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_pageclose</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_lpr_num_entries</td><td class="hex">6:1</td><td class="hex">7e</td><td class="hex">1f</td><td class="hex">3e</td></tr>
-<tr><td >reg_ddrc_auto_pre_en</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_refresh_update_level</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_wc</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_collision_page_opt</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_selfref_en</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ctrl_reg1 @ 0XF8006060</td><td></td><td class="hex"><b>17ff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg2 @ 0XF8006064</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_go2critical_hysteresis</td><td class="hex">12:5</td><td class="hex">1fe0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_go2critical_en</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td><b>ctrl_reg2 @ 0XF8006064</td><td></td><td class="hex"><b>21fe0</b></td><td></td><td class="hex"><b>20000</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg3 @ 0XF8006068</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wrlvl_ww</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">41</td><td class="hex">41</td></tr>
-<tr><td >reg_ddrc_rdlvl_rr</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">41</td><td class="hex">4100</td></tr>
-<tr><td >reg_ddrc_dfi_t_wlmrd</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">28</td><td class="hex">280000</td></tr>
-<tr><td><b>ctrl_reg3 @ 0XF8006068</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>284141</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg4 @ 0XF800606C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_t_ctrlupd_interval_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">10</td><td class="hex">10</td></tr>
-<tr><td >dfi_t_ctrlupd_interval_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">16</td><td class="hex">1600</td></tr>
-<tr><td><b>ctrl_reg4 @ 0XF800606C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>1610</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg5 @ 0XF8006078</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_ctrl_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_disable</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_enable</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_t_cksre</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_t_cksrx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_t_ckesr</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">4</td><td class="hex">400000</td></tr>
-<tr><td><b>ctrl_reg5 @ 0XF8006078</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>466111</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg6 @ 0XF800607C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ckpde</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_ckpdx</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >reg_ddrc_t_ckdpde</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_ckdpdx</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">2</td><td class="hex">2000</td></tr>
-<tr><td >reg_ddrc_t_ckcsx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td><b>ctrl_reg6 @ 0XF800607C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>32222</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ @ 0XF80060A4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_auto_zq</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_ddr3</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_mod</td><td class="hex">11:2</td><td class="hex">ffc</td><td class="hex">200</td><td class="hex">800</td></tr>
-<tr><td >reg_ddrc_t_zq_long_nop</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">200</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_t_zq_short_nop</td><td class="hex">31:22</td><td class="hex">ffc00000</td><td class="hex">40</td><td class="hex">10000000</td></tr>
-<tr><td><b>CHE_T_ZQ @ 0XF80060A4</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10200802</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >t_zq_short_interval_x1024</td><td class="hex">19:0</td><td class="hex">fffff</td><td class="hex">c845</td><td class="hex">c845</td></tr>
-<tr><td >dram_rstn_x1024</td><td class="hex">27:20</td><td class="hex">ff00000</td><td class="hex">67</td><td class="hex">6700000</td></tr>
-<tr><td><b>CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>670c845</b></td></tr></table>
-</li>
-<li><p>Register : deep_pwrdwn_reg @ 0XF80060AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >deeppowerdown_en</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >deeppowerdown_to_x1024</td><td class="hex">8:1</td><td class="hex">1fe</td><td class="hex">ff</td><td class="hex">1fe</td></tr>
-<tr><td><b>deep_pwrdwn_reg @ 0XF80060AC</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>1fe</b></td></tr></table>
-</li>
-<li><p>Register : reg_2c @ 0XF80060B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_wrlvl_max_x1024</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">fff</td><td class="hex">fff</td></tr>
-<tr><td >dfi_rdlvl_max_x1024</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">fff</td><td class="hex">fff000</td></tr>
-<tr><td >ddrc_reg_twrlvl_max_error</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_trdlvl_max_error</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dfi_wr_level_en</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_dqs_gate_level</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_data_eye_train</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>reg_2c @ 0XF80060B0</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>1cffffff</b></td></tr></table>
-</li>
-<li><p>Register : reg_2d @ 0XF80060B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_skip_ocd</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td><b>reg_2d @ 0XF80060B4</td><td></td><td class="hex"><b>200</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : dfi_timing @ 0XF80060B8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_rddata_en</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_min</td><td class="hex">14:5</td><td class="hex">7fe0</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_max</td><td class="hex">24:15</td><td class="hex">1ff8000</td><td class="hex">40</td><td class="hex">200000</td></tr>
-<tr><td><b>dfi_timing @ 0XF80060B8</td><td></td><td class="hex"><b>1ffffff</b></td><td></td><td class="hex"><b>200066</b></td></tr></table>
-</li>
-<h2>RESET ECC ERROR</h2>
-<ul>
-<p>RESET ECC ERROR</p>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>3</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ECC_CORRECTED_BIT_NUM</td><td class="hex">7:1</td><td class="hex">fe</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNCORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STAT_NUM_CORR_ERR</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STAT_NUM_UNCORR_ERR</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ECC_scrub @ 0XF80060F4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_ecc_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_scrub</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td><b>ECC_scrub @ 0XF80060F4</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : phy_rcvr_enable @ 0XF8006114</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_dif_on</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dif_off</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rcvr_enable @ 0XF8006114</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006118</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006118</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF800611C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF800611C</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006120</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006120</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006124</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006124</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF800612C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8f</td><td class="hex">23c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF800612C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>23c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006130</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8a</td><td class="hex">22800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006130</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22800</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006134</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8b</td><td class="hex">22c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006134</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006138</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">92</td><td class="hex">24800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006138</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>24800</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006140</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006140</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006144</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006144</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006148</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006148</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF800614C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF800614C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006154</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">77</td><td class="hex">77</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006154</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>77</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006158</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006158</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF800615C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF800615C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006160</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">75</td><td class="hex">75</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006160</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>75</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006168</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e4</td><td class="hex">e4</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006168</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e4</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF800616C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">df</td><td class="hex">df</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF800616C</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>df</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006170</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e0</td><td class="hex">e0</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006170</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e0</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006174</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e7</td><td class="hex">e7</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006174</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF800617C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b7</td><td class="hex">b7</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF800617C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006180</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006180</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006184</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006184</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006188</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b5</td><td class="hex">b5</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006188</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b5</b></td></tr></table>
-</li>
-<li><p>Register : reg_64 @ 0XF8006190</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_bl2</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_at_spd_atpg</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_enable</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_force_err</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_mode</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_invert_clkout</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_sel_logic</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">100</td><td class="hex">40000</td></tr>
-<tr><td >reg_phy_ctrl_slave_force</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">27:21</td><td class="hex">fe00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_lpddr</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_cmd_latency</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_64 @ 0XF8006190</td><td></td><td class="hex"><b>6ffffefe</b></td><td></td><td class="hex"><b>40080</b></td></tr></table>
-</li>
-<li><p>Register : reg_65 @ 0XF8006194</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_rl_delay</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_phy_rd_rl_delay</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_dll_lock_diff</td><td class="hex">13:10</td><td class="hex">3c00</td><td class="hex">f</td><td class="hex">3c00</td></tr>
-<tr><td >reg_phy_use_wr_level</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">1</td><td class="hex">4000</td></tr>
-<tr><td >reg_phy_use_rd_dqs_gate_level</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">1</td><td class="hex">8000</td></tr>
-<tr><td >reg_phy_use_rd_data_eye_level</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_dis_calib_rst</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_65 @ 0XF8006194</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>1fc82</b></td></tr></table>
-</li>
-<li><p>Register : page_mask @ 0XF8006204</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_page_addr_mask</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>page_mask @ 0XF8006204</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006208</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006208</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF800620C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF800620C</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006210</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006210</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006214</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006214</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006218</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006218</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF800621C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF800621C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006220</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006220</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006224</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006224</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl0 @ 0XF80062A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpddr2</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_derate_enable</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr4_margin</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl0 @ 0XF80062A8</td><td></td><td class="hex"><b>ff5</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl1 @ 0XF80062AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr4_read_interval</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl1 @ 0XF80062AC</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl2 @ 0XF80062B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_min_stable_clock_x1</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_idle_after_reset_x32</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">12</td><td class="hex">120</td></tr>
-<tr><td >reg_ddrc_t_mrw</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>lpddr_ctrl2 @ 0XF80062B0</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>5125</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl3 @ 0XF80062B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_max_auto_init_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">a6</td><td class="hex">a6</td></tr>
-<tr><td >reg_ddrc_dev_zqinit_x32</td><td class="hex">17:8</td><td class="hex">3ff00</td><td class="hex">12</td><td class="hex">1200</td></tr>
-<tr><td><b>lpddr_ctrl3 @ 0XF80062B4</td><td></td><td class="hex"><b>3ffff</b></td><td></td><td class="hex"><b>12a6</b></td></tr></table>
-</li>
-<h2>POLL ON DCI STATUS</h2>
-<ul>
-<p>POLL ON DCI STATUS</p>
-<li><p>Register : DDRIOB_DCI_STATUS @ 0XF8000B74</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DONE</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>DDRIOB_DCI_STATUS @ 0XF8000B74</td><td></td><td class="hex"><b>2000</b></td><td></td><td class="hex"><b>2000</b></td></tr></table>
-</li>
-</ul>
-<h2>UNLOCK DDR</h2>
-<ul>
-<p>UNLOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>81</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK DDR STATUS</h2>
-<ul>
-<p>CHECK DDR STATUS</p>
-<li><p>Register : mode_sts_reg @ 0XF8006054</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ddrc_reg_operating_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>mode_sts_reg @ 0XF8006054</td><td></td><td class="hex"><b>7</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>OCM REMAPPING</h2>
-<ul>
-<p>OCM REMAPPING</p>
-<li><p>Register : GPIOB_CTRL @ 0XF8000B00</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GPIOB_CTRL @ 0XF8000B00</td><td></td><td class="hex"><b>71</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DDRIOB SETTINGS</h2>
-<ul>
-<p>DDRIOB SETTINGS</p>
-<li><p>Register : DDRIOB_ADDR0 @ 0XF8000B40</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR0 @ 0XF8000B40</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_ADDR1 @ 0XF8000B44</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR1 @ 0XF8000B44</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_CLOCK @ 0XF8000B58</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_CLOCK @ 0XF8000B58</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DDR_CTRL @ 0XF8000B6C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_INT_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">4:1</td><td class="hex">1e</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_EXT_EN</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >REFIO_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td><b>DDRIOB_DDR_CTRL @ 0XF8000B6C</td><td></td><td class="hex"><b>27f</b></td><td></td><td class="hex"><b>260</b></td></tr></table>
-</li>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >ENABLE</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >NREF_OPT1</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT2</td><td class="hex">10:8</td><td class="hex">700</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT4</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >PREF_OPT2</td><td class="hex">19:17</td><td class="hex">e0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UPDATE_CONTROL</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>1e3fc3</b></td><td></td><td class="hex"><b>803</b></td></tr></table>
-</li>
-</ul>
-<h2>MIO PROGRAMMING</h2>
-<ul>
-<p>MIO PROGRAMMING</p>
-<li><p>Register : MIO_PIN_00 @ 0XF8000700</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_00 @ 0XF8000700</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_01 @ 0XF8000704</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_01 @ 0XF8000704</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_02 @ 0XF8000708</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_02 @ 0XF8000708</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_03 @ 0XF800070C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_03 @ 0XF800070C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_04 @ 0XF8000710</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_04 @ 0XF8000710</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_05 @ 0XF8000714</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_05 @ 0XF8000714</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_06 @ 0XF8000718</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_06 @ 0XF8000718</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_07 @ 0XF800071C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_07 @ 0XF800071C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_08 @ 0XF8000720</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_08 @ 0XF8000720</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_09 @ 0XF8000724</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_09 @ 0XF8000724</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_10 @ 0XF8000728</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_10 @ 0XF8000728</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_11 @ 0XF800072C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_11 @ 0XF800072C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_12 @ 0XF8000730</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_12 @ 0XF8000730</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_13 @ 0XF8000734</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_13 @ 0XF8000734</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_14 @ 0XF8000738</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_14 @ 0XF8000738</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_15 @ 0XF800073C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_15 @ 0XF800073C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_16 @ 0XF8000740</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_16 @ 0XF8000740</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_17 @ 0XF8000744</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_17 @ 0XF8000744</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_18 @ 0XF8000748</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_18 @ 0XF8000748</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_19 @ 0XF800074C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_19 @ 0XF800074C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_20 @ 0XF8000750</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_20 @ 0XF8000750</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_21 @ 0XF8000754</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_21 @ 0XF8000754</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_22 @ 0XF8000758</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_22 @ 0XF8000758</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_23 @ 0XF800075C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_23 @ 0XF800075C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_24 @ 0XF8000760</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_24 @ 0XF8000760</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_25 @ 0XF8000764</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_25 @ 0XF8000764</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_26 @ 0XF8000768</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_26 @ 0XF8000768</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_27 @ 0XF800076C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_27 @ 0XF800076C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_28 @ 0XF8000770</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_28 @ 0XF8000770</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_29 @ 0XF8000774</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_29 @ 0XF8000774</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_30 @ 0XF8000778</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_30 @ 0XF8000778</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_31 @ 0XF800077C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_31 @ 0XF800077C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_32 @ 0XF8000780</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_32 @ 0XF8000780</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_33 @ 0XF8000784</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_33 @ 0XF8000784</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_34 @ 0XF8000788</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_34 @ 0XF8000788</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_35 @ 0XF800078C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_35 @ 0XF800078C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_36 @ 0XF8000790</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_36 @ 0XF8000790</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_37 @ 0XF8000794</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_37 @ 0XF8000794</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_38 @ 0XF8000798</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_38 @ 0XF8000798</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_39 @ 0XF800079C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_39 @ 0XF800079C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_40 @ 0XF80007A0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_40 @ 0XF80007A0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_41 @ 0XF80007A4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_41 @ 0XF80007A4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_42 @ 0XF80007A8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_42 @ 0XF80007A8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_43 @ 0XF80007AC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_43 @ 0XF80007AC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_44 @ 0XF80007B0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_44 @ 0XF80007B0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_45 @ 0XF80007B4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_45 @ 0XF80007B4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_46 @ 0XF80007B8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_46 @ 0XF80007B8</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_47 @ 0XF80007BC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_47 @ 0XF80007BC</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_48 @ 0XF80007C0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_48 @ 0XF80007C0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e0</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_49 @ 0XF80007C4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_49 @ 0XF80007C4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e1</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_50 @ 0XF80007C8</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_50 @ 0XF80007C8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_51 @ 0XF80007CC</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_51 @ 0XF80007CC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_52 @ 0XF80007D0</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_52 @ 0XF80007D0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_53 @ 0XF80007D4</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_53 @ 0XF80007D4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : SD0_WP_CD_SEL @ 0XF8000830</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SDIO0_CD_SEL</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">2f</td><td class="hex">2f0000</td></tr>
-<tr><td><b>SD0_WP_CD_SEL @ 0XF8000830</td><td></td><td class="hex"><b>3f0000</b></td><td></td><td class="hex"><b>2f0000</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR TERM/IBUF_DISABLE_MODE SETTINGS</h2>
-<ul>
-<p>DDR TERM/IBUF_DISABLE_MODE SETTINGS</p>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-<h2>SRAM/NOR SET OPMODE</h2>
-<ul>
-<p>SRAM/NOR SET OPMODE</p>
-</ul>
-<h2>UART REGISTERS</h2>
-<ul>
-<p>UART REGISTERS</p>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0001034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0001034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0001018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0001018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0001000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0001000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0001004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0001004</td><td></td><td class="hex"><b>3ff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0000034</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0000034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0000018</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0000018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0000000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0000000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0000004</td><td></td><td class="hex"><b>3ff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<h2>QSPI REGISTERS</h2>
-<ul>
-<p>QSPI REGISTERS</p>
-<li><p>Register : Config_reg @ 0XE000D000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Holdb_dr</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>Config_reg @ 0XE000D000</td><td></td><td class="hex"><b>80000</b></td><td></td><td class="hex"><b>80000</b></td></tr></table>
-</li>
-</ul>
-<h2>PL POWER ON RESET REGISTERS</h2>
-<ul>
-<p>PL POWER ON RESET REGISTERS</p>
-<li><p>Register : CTRL @ 0XF8007000</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PCFG_POR_CNT_4K</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CTRL @ 0XF8007000</td><td></td><td class="hex"><b>20000000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>SMC TIMING CALCULATION REGISTER UPDATE</h2>
-<ul>
-<p>SMC TIMING CALCULATION REGISTER UPDATE</p>
-<h2>NAND SET CYCLE</h2>
-<ul>
-<p>NAND SET CYCLE</p>
-</ul>
-<h2>OPMODE</h2>
-<ul>
-<p>OPMODE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>SRAM/NOR CS0 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS0 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS0 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS0 BASE ADDRESS</p>
-</ul>
-<h2>SRAM/NOR CS1 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS1 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS1 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS1 BASE ADDRESS</p>
-</ul>
-<h2>USB RESET</h2>
-<ul>
-<p>USB RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-<li><p>Register : DIRM_1 @ 0XE000A244</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DIRECTION_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>DIRM_1 @ 0XE000A244</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-<li><p>Register : OEN_1 @ 0XE000A248</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >OP_ENABLE_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>OEN_1 @ 0XE000A248</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff0000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>ENET RESET</h2>
-<ul>
-<p>ENET RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>I2C RESET</h2>
-<ul>
-<p>I2C RESET</p>
-<h2>DIR MODE GPIO BANK0</h2>
-<ul>
-<p>DIR MODE GPIO BANK0</p>
-</ul>
-<h2>DIR MODE GPIO BANK1</h2>
-<ul>
-<p>DIR MODE GPIO BANK1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>ENABLING LEVEL SHIFTER</h2>
-<ul>
-<p>ENABLING LEVEL SHIFTER</p>
-<li><p>Register : LVL_SHFTR_EN @ 0XF8000900</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >USER_LVL_INP_EN_0</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >USER_LVL_OUT_EN_0</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USER_LVL_INP_EN_1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >USER_LVL_OUT_EN_1</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>LVL_SHFTR_EN @ 0XF8000900</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>f</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 1</h2>
-<ul>
-<p>FPGA RESETS TO 1</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">7f</td><td class="hex">fe000000</td></tr>
-<tr><td >reserved_FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >reserved_FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >reserved_FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >reserved_FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >reserved_FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">3</td><td class="hex">c0000</td></tr>
-<tr><td >reserved_FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td >reserved_FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reserved_FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td >reserved_FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reserved_FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >reserved_FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >reserved_FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reserved_FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">f</td><td class="hex">f0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>ffffffff</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 0</h2>
-<ul>
-<p>FPGA RESETS TO 0</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>AFI REGISTERS</h2>
-<ul>
-<p>AFI REGISTERS</p>
-<h2>AFI0 REGISTERS</h2>
-<ul>
-<p>AFI0 REGISTERS</p>
-</ul>
-<h2>AFI1 REGISTERS</h2>
-<ul>
-<p>AFI1 REGISTERS</p>
-</ul>
-<h2>AFI2 REGISTERS</h2>
-<ul>
-<p>AFI2 REGISTERS</p>
-</ul>
-<h2>AFI3 REGISTERS</h2>
-<ul>
-<p>AFI3 REGISTERS</p>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1">
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-</body>
-</html>
diff --git a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.tcl b/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.tcl
deleted file mode 100644
index 496281373..000000000
--- a/quad/xsdk_workspace/zybo_fsbl/src/ps7_init.tcl
+++ /dev/null
@@ -1,762 +0,0 @@
-proc ps7_pll_init_data_1_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001772C0
- mask_write 0XF8000100 0x0007F000 0x0001A000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
- mask_write 0XF8000104 0x0007F000 0x00015000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x001F42C0
- mask_write 0XF8000108 0x0007F000 0x00014000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203401
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100801
- mask_write 0XF800014C 0x00003F31 0x00000501
- mask_write 0XF8000150 0x00003F33 0x00001401
- mask_write 0XF8000154 0x00003F33 0x00001403
- mask_write 0XF8000168 0x00003F31 0x00000501
- mask_write 0XF8000170 0x03F03F30 0x00100A00
- mask_write 0XF8000180 0x03F03F30 0x00100630
- mask_write 0XF8000190 0x03F03F30 0x00203520
- mask_write 0XF80001A0 0x03F03F30 0x00100A00
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000080
- mask_write 0XF8006004 0x1FFFFFFF 0x0008107F
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x0004151A
- mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011014
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000777
- mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
- mask_write 0XF80060AC 0x000001FF 0x000001FE
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000003
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000001
- mask_write 0XF8006124 0x7FFFFFFF 0x40000001
- mask_write 0XF800612C 0x000FFFFF 0x00023C00
- mask_write 0XF8006130 0x000FFFFF 0x00022800
- mask_write 0XF8006134 0x000FFFFF 0x00022C00
- mask_write 0XF8006138 0x000FFFFF 0x00024800
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000077
- mask_write 0XF8006158 0x000FFFFF 0x0000007C
- mask_write 0XF800615C 0x000FFFFF 0x0000007C
- mask_write 0XF8006160 0x000FFFFF 0x00000075
- mask_write 0XF8006168 0x001FFFFF 0x000000E4
- mask_write 0XF800616C 0x001FFFFF 0x000000DF
- mask_write 0XF8006170 0x001FFFFF 0x000000E0
- mask_write 0XF8006174 0x001FFFFF 0x000000E7
- mask_write 0XF800617C 0x000FFFFF 0x000000B7
- mask_write 0XF8006180 0x000FFFFF 0x000000BC
- mask_write 0XF8006184 0x000FFFFF 0x000000BC
- mask_write 0XF8006188 0x000FFFFF 0x000000B5
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005125
- mask_write 0XF80062B4 0x0003FFFF 0x000012A6
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000081
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000B00 0x00000303 0x00000001
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000672
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000674
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x00D6861C
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B68 0xFFFFFFFF 0x00D6861C
- mask_write 0XF8000B6C 0x000073FF 0x00000260
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00000600
- mask_write 0XF8000704 0x00003FFF 0x00000702
- mask_write 0XF8000708 0x00003FFF 0x00000702
- mask_write 0XF800070C 0x00003FFF 0x00000702
- mask_write 0XF8000710 0x00003FFF 0x00000702
- mask_write 0XF8000714 0x00003FFF 0x00000702
- mask_write 0XF8000718 0x00003FFF 0x00000702
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000702
- mask_write 0XF8000724 0x00003FFF 0x00000600
- mask_write 0XF8000728 0x00003FFF 0x00001640
- mask_write 0XF800072C 0x00003FFF 0x00001640
- mask_write 0XF8000730 0x00003FFF 0x00000640
- mask_write 0XF8000734 0x00003FFF 0x00000640
- mask_write 0XF8000738 0x00003FFF 0x00000600
- mask_write 0XF800073C 0x00003FFF 0x00000600
- mask_write 0XF8000740 0x00003FFF 0x00002902
- mask_write 0XF8000744 0x00003FFF 0x00002902
- mask_write 0XF8000748 0x00003FFF 0x00002902
- mask_write 0XF800074C 0x00003FFF 0x00002902
- mask_write 0XF8000750 0x00003FFF 0x00002902
- mask_write 0XF8000754 0x00003FFF 0x00002902
- mask_write 0XF8000758 0x00003FFF 0x00000903
- mask_write 0XF800075C 0x00003FFF 0x00000903
- mask_write 0XF8000760 0x00003FFF 0x00000903
- mask_write 0XF8000764 0x00003FFF 0x00000903
- mask_write 0XF8000768 0x00003FFF 0x00000903
- mask_write 0XF800076C 0x00003FFF 0x00000903
- mask_write 0XF8000770 0x00003FFF 0x00000304
- mask_write 0XF8000774 0x00003FFF 0x00000305
- mask_write 0XF8000778 0x00003FFF 0x00000304
- mask_write 0XF800077C 0x00003FFF 0x00000305
- mask_write 0XF8000780 0x00003FFF 0x00000304
- mask_write 0XF8000784 0x00003FFF 0x00000304
- mask_write 0XF8000788 0x00003FFF 0x00000304
- mask_write 0XF800078C 0x00003FFF 0x00000304
- mask_write 0XF8000790 0x00003FFF 0x00000305
- mask_write 0XF8000794 0x00003FFF 0x00000304
- mask_write 0XF8000798 0x00003FFF 0x00000304
- mask_write 0XF800079C 0x00003FFF 0x00000304
- mask_write 0XF80007A0 0x00003FFF 0x00000380
- mask_write 0XF80007A4 0x00003FFF 0x00000380
- mask_write 0XF80007A8 0x00003FFF 0x00000380
- mask_write 0XF80007AC 0x00003FFF 0x00000380
- mask_write 0XF80007B0 0x00003FFF 0x00000380
- mask_write 0XF80007B4 0x00003FFF 0x00000380
- mask_write 0XF80007B8 0x00003F01 0x00000200
- mask_write 0XF80007BC 0x00003F01 0x00000201
- mask_write 0XF80007C0 0x00003FFF 0x000002E0
- mask_write 0XF80007C4 0x00003FFF 0x000002E1
- mask_write 0XF80007C8 0x00003FFF 0x00000201
- mask_write 0XF80007CC 0x00003FFF 0x00000201
- mask_write 0XF80007D0 0x00003FFF 0x00000280
- mask_write 0XF80007D4 0x00003FFF 0x00000280
- mask_write 0XF8000830 0x003F0000 0x002F0000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000180
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000180
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000003E
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000003E
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XF8007000 0x20000000 0x00000000
- mask_write 0XE000A244 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_write 0XE000A248 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-}
-proc ps7_post_config_1_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0xFFFFFFFF
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_pll_init_data_2_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001772C0
- mask_write 0XF8000100 0x0007F000 0x0001A000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
- mask_write 0XF8000104 0x0007F000 0x00015000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x001F42C0
- mask_write 0XF8000108 0x0007F000 0x00014000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203401
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100801
- mask_write 0XF800014C 0x00003F31 0x00000501
- mask_write 0XF8000150 0x00003F33 0x00001401
- mask_write 0XF8000154 0x00003F33 0x00001403
- mask_write 0XF8000168 0x00003F31 0x00000501
- mask_write 0XF8000170 0x03F03F30 0x00100A00
- mask_write 0XF8000180 0x03F03F30 0x00100630
- mask_write 0XF8000190 0x03F03F30 0x00203520
- mask_write 0XF80001A0 0x03F03F30 0x00100A00
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000080
- mask_write 0XF8006004 0x1FFFFFFF 0x0008107F
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x0004151A
- mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011014
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000777
- mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00466111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
- mask_write 0XF80060AC 0x000001FF 0x000001FE
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000003
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000001
- mask_write 0XF8006124 0x7FFFFFFF 0x40000001
- mask_write 0XF800612C 0x000FFFFF 0x00023C00
- mask_write 0XF8006130 0x000FFFFF 0x00022800
- mask_write 0XF8006134 0x000FFFFF 0x00022C00
- mask_write 0XF8006138 0x000FFFFF 0x00024800
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000077
- mask_write 0XF8006158 0x000FFFFF 0x0000007C
- mask_write 0XF800615C 0x000FFFFF 0x0000007C
- mask_write 0XF8006160 0x000FFFFF 0x00000075
- mask_write 0XF8006168 0x001FFFFF 0x000000E4
- mask_write 0XF800616C 0x001FFFFF 0x000000DF
- mask_write 0XF8006170 0x001FFFFF 0x000000E0
- mask_write 0XF8006174 0x001FFFFF 0x000000E7
- mask_write 0XF800617C 0x000FFFFF 0x000000B7
- mask_write 0XF8006180 0x000FFFFF 0x000000BC
- mask_write 0XF8006184 0x000FFFFF 0x000000BC
- mask_write 0XF8006188 0x000FFFFF 0x000000B5
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005125
- mask_write 0XF80062B4 0x0003FFFF 0x000012A6
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000081
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000B00 0x00000303 0x00000001
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000672
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000674
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x00D6861C
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
- mask_write 0XF8000B68 0xFFFFFFFF 0x00D6861C
- mask_write 0XF8000B6C 0x00007FFF 0x00000E60
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00000600
- mask_write 0XF8000704 0x00003FFF 0x00000702
- mask_write 0XF8000708 0x00003FFF 0x00000702
- mask_write 0XF800070C 0x00003FFF 0x00000702
- mask_write 0XF8000710 0x00003FFF 0x00000702
- mask_write 0XF8000714 0x00003FFF 0x00000702
- mask_write 0XF8000718 0x00003FFF 0x00000702
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000702
- mask_write 0XF8000724 0x00003FFF 0x00000600
- mask_write 0XF8000728 0x00003FFF 0x00001640
- mask_write 0XF800072C 0x00003FFF 0x00001640
- mask_write 0XF8000730 0x00003FFF 0x00000640
- mask_write 0XF8000734 0x00003FFF 0x00000640
- mask_write 0XF8000738 0x00003FFF 0x00000600
- mask_write 0XF800073C 0x00003FFF 0x00000600
- mask_write 0XF8000740 0x00003FFF 0x00002902
- mask_write 0XF8000744 0x00003FFF 0x00002902
- mask_write 0XF8000748 0x00003FFF 0x00002902
- mask_write 0XF800074C 0x00003FFF 0x00002902
- mask_write 0XF8000750 0x00003FFF 0x00002902
- mask_write 0XF8000754 0x00003FFF 0x00002902
- mask_write 0XF8000758 0x00003FFF 0x00000903
- mask_write 0XF800075C 0x00003FFF 0x00000903
- mask_write 0XF8000760 0x00003FFF 0x00000903
- mask_write 0XF8000764 0x00003FFF 0x00000903
- mask_write 0XF8000768 0x00003FFF 0x00000903
- mask_write 0XF800076C 0x00003FFF 0x00000903
- mask_write 0XF8000770 0x00003FFF 0x00000304
- mask_write 0XF8000774 0x00003FFF 0x00000305
- mask_write 0XF8000778 0x00003FFF 0x00000304
- mask_write 0XF800077C 0x00003FFF 0x00000305
- mask_write 0XF8000780 0x00003FFF 0x00000304
- mask_write 0XF8000784 0x00003FFF 0x00000304
- mask_write 0XF8000788 0x00003FFF 0x00000304
- mask_write 0XF800078C 0x00003FFF 0x00000304
- mask_write 0XF8000790 0x00003FFF 0x00000305
- mask_write 0XF8000794 0x00003FFF 0x00000304
- mask_write 0XF8000798 0x00003FFF 0x00000304
- mask_write 0XF800079C 0x00003FFF 0x00000304
- mask_write 0XF80007A0 0x00003FFF 0x00000380
- mask_write 0XF80007A4 0x00003FFF 0x00000380
- mask_write 0XF80007A8 0x00003FFF 0x00000380
- mask_write 0XF80007AC 0x00003FFF 0x00000380
- mask_write 0XF80007B0 0x00003FFF 0x00000380
- mask_write 0XF80007B4 0x00003FFF 0x00000380
- mask_write 0XF80007B8 0x00003F01 0x00000200
- mask_write 0XF80007BC 0x00003F01 0x00000201
- mask_write 0XF80007C0 0x00003FFF 0x000002E0
- mask_write 0XF80007C4 0x00003FFF 0x000002E1
- mask_write 0XF80007C8 0x00003FFF 0x00000201
- mask_write 0XF80007CC 0x00003FFF 0x00000201
- mask_write 0XF80007D0 0x00003FFF 0x00000280
- mask_write 0XF80007D4 0x00003FFF 0x00000280
- mask_write 0XF8000830 0x003F0000 0x002F0000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000180
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000180
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000003E
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000003E
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
- mask_write 0XE000A244 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_write 0XE000A248 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-}
-proc ps7_post_config_2_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0xFFFFFFFF
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_pll_init_data_3_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001772C0
- mask_write 0XF8000100 0x0007F000 0x0001A000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
- mask_write 0XF8000104 0x0007F000 0x00015000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x001F42C0
- mask_write 0XF8000108 0x0007F000 0x00014000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203401
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100801
- mask_write 0XF800014C 0x00003F31 0x00000501
- mask_write 0XF8000150 0x00003F33 0x00001401
- mask_write 0XF8000154 0x00003F33 0x00001403
- mask_write 0XF8000168 0x00003F31 0x00000501
- mask_write 0XF8000170 0x03F03F30 0x00100A00
- mask_write 0XF8000180 0x03F03F30 0x00100630
- mask_write 0XF8000190 0x03F03F30 0x00203520
- mask_write 0XF80001A0 0x03F03F30 0x00100A00
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000080
- mask_write 0XF8006004 0x0007FFFF 0x0000107F
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x0004151A
- mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011014
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000777
- mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
- mask_write 0XF8006048 0x0003F000 0x0003C000
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00466111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
- mask_write 0XF80060AC 0x000001FF 0x000001FE
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000003
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000001
- mask_write 0XF8006124 0x7FFFFFCF 0x40000001
- mask_write 0XF800612C 0x000FFFFF 0x00023C00
- mask_write 0XF8006130 0x000FFFFF 0x00022800
- mask_write 0XF8006134 0x000FFFFF 0x00022C00
- mask_write 0XF8006138 0x000FFFFF 0x00024800
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000077
- mask_write 0XF8006158 0x000FFFFF 0x0000007C
- mask_write 0XF800615C 0x000FFFFF 0x0000007C
- mask_write 0XF8006160 0x000FFFFF 0x00000075
- mask_write 0XF8006168 0x001FFFFF 0x000000E4
- mask_write 0XF800616C 0x001FFFFF 0x000000DF
- mask_write 0XF8006170 0x001FFFFF 0x000000E0
- mask_write 0XF8006174 0x001FFFFF 0x000000E7
- mask_write 0XF800617C 0x000FFFFF 0x000000B7
- mask_write 0XF8006180 0x000FFFFF 0x000000BC
- mask_write 0XF8006184 0x000FFFFF 0x000000BC
- mask_write 0XF8006188 0x000FFFFF 0x000000B5
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005125
- mask_write 0XF80062B4 0x0003FFFF 0x000012A6
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000081
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000B00 0x00000071 0x00000001
- mask_write 0XF8000B40 0x00000FFE 0x00000600
- mask_write 0XF8000B44 0x00000FFE 0x00000600
- mask_write 0XF8000B48 0x00000FFE 0x00000672
- mask_write 0XF8000B4C 0x00000FFE 0x00000672
- mask_write 0XF8000B50 0x00000FFE 0x00000674
- mask_write 0XF8000B54 0x00000FFE 0x00000674
- mask_write 0XF8000B58 0x00000FFE 0x00000600
- mask_write 0XF8000B6C 0x0000027F 0x00000260
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000001 0x00000000
- mask_write 0XF8000B70 0x001E3FC3 0x00000803
- mask_write 0XF8000700 0x00003FFF 0x00000600
- mask_write 0XF8000704 0x00003FFF 0x00000702
- mask_write 0XF8000708 0x00003FFF 0x00000702
- mask_write 0XF800070C 0x00003FFF 0x00000702
- mask_write 0XF8000710 0x00003FFF 0x00000702
- mask_write 0XF8000714 0x00003FFF 0x00000702
- mask_write 0XF8000718 0x00003FFF 0x00000702
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000702
- mask_write 0XF8000724 0x00003FFF 0x00000600
- mask_write 0XF8000728 0x00003FFF 0x00001640
- mask_write 0XF800072C 0x00003FFF 0x00001640
- mask_write 0XF8000730 0x00003FFF 0x00000640
- mask_write 0XF8000734 0x00003FFF 0x00000640
- mask_write 0XF8000738 0x00003FFF 0x00000600
- mask_write 0XF800073C 0x00003FFF 0x00000600
- mask_write 0XF8000740 0x00003FFF 0x00002902
- mask_write 0XF8000744 0x00003FFF 0x00002902
- mask_write 0XF8000748 0x00003FFF 0x00002902
- mask_write 0XF800074C 0x00003FFF 0x00002902
- mask_write 0XF8000750 0x00003FFF 0x00002902
- mask_write 0XF8000754 0x00003FFF 0x00002902
- mask_write 0XF8000758 0x00003FFF 0x00000903
- mask_write 0XF800075C 0x00003FFF 0x00000903
- mask_write 0XF8000760 0x00003FFF 0x00000903
- mask_write 0XF8000764 0x00003FFF 0x00000903
- mask_write 0XF8000768 0x00003FFF 0x00000903
- mask_write 0XF800076C 0x00003FFF 0x00000903
- mask_write 0XF8000770 0x00003FFF 0x00000304
- mask_write 0XF8000774 0x00003FFF 0x00000305
- mask_write 0XF8000778 0x00003FFF 0x00000304
- mask_write 0XF800077C 0x00003FFF 0x00000305
- mask_write 0XF8000780 0x00003FFF 0x00000304
- mask_write 0XF8000784 0x00003FFF 0x00000304
- mask_write 0XF8000788 0x00003FFF 0x00000304
- mask_write 0XF800078C 0x00003FFF 0x00000304
- mask_write 0XF8000790 0x00003FFF 0x00000305
- mask_write 0XF8000794 0x00003FFF 0x00000304
- mask_write 0XF8000798 0x00003FFF 0x00000304
- mask_write 0XF800079C 0x00003FFF 0x00000304
- mask_write 0XF80007A0 0x00003FFF 0x00000380
- mask_write 0XF80007A4 0x00003FFF 0x00000380
- mask_write 0XF80007A8 0x00003FFF 0x00000380
- mask_write 0XF80007AC 0x00003FFF 0x00000380
- mask_write 0XF80007B0 0x00003FFF 0x00000380
- mask_write 0XF80007B4 0x00003FFF 0x00000380
- mask_write 0XF80007B8 0x00003F01 0x00000200
- mask_write 0XF80007BC 0x00003F01 0x00000201
- mask_write 0XF80007C0 0x00003FFF 0x000002E0
- mask_write 0XF80007C4 0x00003FFF 0x000002E1
- mask_write 0XF80007C8 0x00003FFF 0x00000201
- mask_write 0XF80007CC 0x00003FFF 0x00000201
- mask_write 0XF80007D0 0x00003FFF 0x00000280
- mask_write 0XF80007D4 0x00003FFF 0x00000280
- mask_write 0XF8000830 0x003F0000 0x002F0000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000180
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000180
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000003E
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000003E
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
- mask_write 0XE000A244 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
- mask_write 0XE000A248 0x003FFFFF 0x00004000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
- mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-}
-proc ps7_post_config_3_0 {} {
- mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0xFFFFFFFF
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-
-
-
-proc mask_poll { addr mask } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- }
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
-}
-
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject b/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject
index d01a3047c..5129f789a 100644
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject
+++ b/quad/xsdk_workspace/zybo_fsbl_bsp/.cproject
@@ -3,8 +3,8 @@
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="org.eclipse.cdt.core.default.config.145391090">
- <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.145391090" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+ <cconfiguration id="org.eclipse.cdt.core.default.config.1389527391">
+ <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1389527391" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/.project b/quad/xsdk_workspace/zybo_fsbl_bsp/.project
index db7920e2d..9b0b646a3 100644
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/.project
+++ b/quad/xsdk_workspace/zybo_fsbl_bsp/.project
@@ -3,7 +3,7 @@
<name>zybo_fsbl_bsp</name>
<comment></comment>
<projects>
- <project>system_hw_platform</project>
+ <project>sytem_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options b/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options
index ac5ba3966..c7623d91f 100644
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options
+++ b/quad/xsdk_workspace/zybo_fsbl_bsp/libgen.options
@@ -1,3 +1,3 @@
PROCESSOR=ps7_cortexa9_0
REPOSITORIES=
-HWSPEC=../system_hw_platform/system.xml
+HWSPEC=../sytem_hw_platform/system.xml
diff --git a/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss b/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss
index f6a16bfdc..901e54a47 100644
--- a/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss
+++ b/quad/xsdk_workspace/zybo_fsbl_bsp/system.mss
@@ -120,6 +120,12 @@ BEGIN DRIVER
PARAMETER HW_INSTANCE = ps7_i2c_0
END
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 1.04.a
+ PARAMETER HW_INSTANCE = ps7_i2c_1
+END
+
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
--
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