diff --git a/quad/vivado_workspace/quad_hw.tcl b/quad/vivado_workspace/quad_hw.tcl
index 503789e45ad582ef97c999b1ae76ec4aeaa0d73f..a34e1e0e27eb6d4499ffe03a695560a28cc2c56d 100644
--- a/quad/vivado_workspace/quad_hw.tcl
+++ b/quad/vivado_workspace/quad_hw.tcl
@@ -278,14 +278,16 @@ proc cr_bd_design_1 { parentCell } {
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+ set I2C0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C0 ]
+ set I2C1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C1 ]
+ set UART0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART0 ]
+ set UART1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART1 ]
set btns_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 btns_4bits ]
set leds_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 leds_4bits ]
set rgb_led [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rgb_led ]
set sws_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 sws_4bits ]
# Create ports
- set UART0_RX_0 [ create_bd_port -dir I UART0_RX_0 ]
- set UART0_TX_0 [ create_bd_port -dir O UART0_TX_0 ]
set pwm_in_0 [ create_bd_port -dir I pwm_in_0 ]
set pwm_in_1 [ create_bd_port -dir I pwm_in_1 ]
set pwm_in_2 [ create_bd_port -dir I pwm_in_2 ]
@@ -405,10 +407,11 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
CONFIG.PCW_EN_4K_TIMER {0} \
- CONFIG.PCW_EN_EMIO_I2C0 {0} \
- CONFIG.PCW_EN_EMIO_I2C1 {0} \
+ CONFIG.PCW_EN_EMIO_I2C0 {1} \
+ CONFIG.PCW_EN_EMIO_I2C1 {1} \
CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
CONFIG.PCW_EN_EMIO_UART0 {1} \
+ CONFIG.PCW_EN_EMIO_UART1 {1} \
CONFIG.PCW_EN_ENET0 {1} \
CONFIG.PCW_EN_GPIO {1} \
CONFIG.PCW_EN_I2C0 {1} \
@@ -435,12 +438,14 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
- CONFIG.PCW_I2C0_I2C0_IO {MIO 10 .. 11} \
+ CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \
+ CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \
+ CONFIG.PCW_I2C0_I2C0_IO {EMIO} \
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
- CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
- CONFIG.PCW_I2C1_I2C1_IO {MIO 12 .. 13} \
+ CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
+ CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
+ CONFIG.PCW_I2C1_I2C1_IO {EMIO} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
@@ -534,7 +539,9 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.PCW_MIO_28_PULLUP {enabled} \
CONFIG.PCW_MIO_28_SLEW {fast} \
CONFIG.PCW_MIO_29_DIRECTION {in} \
- CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMO
+ CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_2_PULLUP {disablS 1.8V} \
CONFIG.PCW_MIO_29_PULLUP {enabled} \
CONFIG.PCW_MIO_29_SLEW {fast} \
CONFIG.PCW_MIO_2_DIRECTION {inout} \
@@ -665,8 +672,8 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#I2C 0#I2C 0#I2C 1#I2C 1#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#scl#sda#scl#sda#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
@@ -728,7 +735,7 @@ proc cr_bd_design_1 { parentCell } {
CONFIG.PCW_UART1_BAUD_RATE {115200} \
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+ CONFIG.PCW_UART1_UART1_IO {EMIO} \
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
@@ -866,7 +873,11 @@ proc cr_bd_design_1 { parentCell } {
connect_bd_intf_net -intf_net axi_gpio_3_GPIO [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_3/GPIO]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_IIC_0 [get_bd_intf_ports I2C0] [get_bd_intf_pins processing_system7_0/IIC_0]
+ connect_bd_intf_net -intf_net processing_system7_0_IIC_1 [get_bd_intf_ports I2C1] [get_bd_intf_pins processing_system7_0/IIC_1]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_UART_0 [get_bd_intf_ports UART0] [get_bd_intf_pins processing_system7_0/UART_0]
+ connect_bd_intf_net -intf_net processing_system7_0_UART_1 [get_bd_intf_ports UART1] [get_bd_intf_pins processing_system7_0/UART_1]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_sws/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_leds/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_btns/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
@@ -884,10 +895,8 @@ proc cr_bd_design_1 { parentCell } {
connect_bd_intf_net -intf_net ps7_0_axi_periph_M14_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M14_AXI]
# Create port connections
- connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins processing_system7_0/UART0_RX]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_btns/s_axi_aclk] [get_bd_pins axi_gpio_leds/s_axi_aclk] [get_bd_pins axi_gpio_sws/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/M05_ACLK] [get_bd_pins ps7_0_axi_periph/M06_ACLK] [get_bd_pins ps7_0_axi_periph/M07_ACLK] [get_bd_pins ps7_0_axi_periph/M08_ACLK] [get_bd_pins ps7_0_axi_periph/M09_ACLK] [get_bd_pins ps7_0_axi_periph/M10_ACLK] [get_bd_pins ps7_0_axi_periph/M11_ACLK] [get_bd_pins ps7_0_axi_periph/M12_ACLK] [get_bd_pins ps7_0_axi_periph/M13_ACLK] [get_bd_pins ps7_0_axi_periph/M14_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pwm_recorder_0/s_axi_aclk] [get_bd_pins pwm_recorder_1/s_axi_aclk] [get_bd_pins pwm_recorder_2/s_axi_aclk] [get_bd_pins pwm_recorder_3/s_axi_aclk] [get_bd_pins pwm_recorder_4/s_axi_aclk] [get_bd_pins pwm_recorder_5/s_axi_aclk] [get_bd_pins pwm_signal_out_0/s_axi_aclk] [get_bd_pins pwm_signal_out_1/s_axi_aclk] [get_bd_pins pwm_signal_out_2/s_axi_aclk] [get_bd_pins pwm_signal_out_3/s_axi_aclk] [get_bd_pins rst_ps7_0_50M/slowest_sync_clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_50M/ext_reset_in]
- connect_bd_net -net processing_system7_0_UART0_TX [get_bd_ports UART0_TX_0] [get_bd_pins processing_system7_0/UART0_TX]
connect_bd_net -net pwm_in_master_0_1 [get_bd_ports pwm_in_0] [get_bd_pins pwm_recorder_0/pwm_in_master]
connect_bd_net -net pwm_in_master_1_1 [get_bd_ports pwm_in_1] [get_bd_pins pwm_recorder_1/pwm_in_master]
connect_bd_net -net pwm_in_master_2_1 [get_bd_ports pwm_in_2] [get_bd_pins pwm_recorder_2/pwm_in_master]
diff --git a/quad/vivado_workspace/quad_hw/src/constrs/Zybo-Z7-Master.xdc b/quad/vivado_workspace/quad_hw/src/constrs/Zybo-Z7-Master.xdc
index 07a207269b59319a4e3001dbb8e8cf9c1e1b064a..19608447aa45600a8cc1a2b4e5a0c09a2880ca70 100644
--- a/quad/vivado_workspace/quad_hw/src/constrs/Zybo-Z7-Master.xdc
+++ b/quad/vivado_workspace/quad_hw/src/constrs/Zybo-Z7-Master.xdc
@@ -124,35 +124,35 @@
##Pmod Header JC
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
-set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { UART0_TX_0 }]; #IO_L10N_T1_34 Sch=jc_n[1]
-set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { UART0_RX_0 }]; #IO_L1P_T0_34 Sch=jc_p[2]
+set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { UART0_txd }]; #IO_L10N_T1_34 Sch=jc_n[1]
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { UART0_rxd }]; #IO_L1P_T0_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
-#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
-#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
+set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { UART1_txd }]; #IO_L8N_T1_34 Sch=jc_n[3]
+set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { UART1_rxd }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
##Pmod Header JD
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
-#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
-#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
-set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_4 }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
-set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_5 }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
-#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
-#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { I2C0_sda_io }]; #IO_L6P_T0_34 Sch=jd_p[2]
+set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { I2C0_scl_io }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
+set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_1 }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
+set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_0 }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
+set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { I2C1_sda_io }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
+set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { I2C1_scl_io }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
##Pmod Header JE
-set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_0 }]; #IO_L4P_T0_34 Sch=je[1]
-set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_1 }]; #IO_L18N_T2_34 Sch=je[2]
-set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_2 }]; #IO_25_35 Sch=je[3]
-set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_3 }]; #IO_L19P_T3_35 Sch=je[4]
-set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_0 }]; #IO_L3N_T0_DQS_34 Sch=je[7]
-set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_1 }]; #IO_L9N_T1_DQS_34 Sch=je[8]
-set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_2 }]; #IO_L20P_T3_34 Sch=je[9]
-set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_3 }]; #IO_L7N_T1_34 Sch=je[10]
+set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_5 }]; #IO_L4P_T0_34 Sch=je[1]
+set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_4 }]; #IO_L18N_T2_34 Sch=je[2]
+set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_3 }]; #IO_25_35 Sch=je[3]
+set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { pwm_in_2 }]; #IO_L19P_T3_35 Sch=je[4]
+set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_2 }]; #IO_L3N_T0_DQS_34 Sch=je[7]
+set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_3 }]; #IO_L9N_T1_DQS_34 Sch=je[8]
+set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_1 }]; #IO_L20P_T3_34 Sch=je[9]
+set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { pwm_out_0 }]; #IO_L7N_T1_34 Sch=je[10]
##Pcam MIPI CSI-2 Connector
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
index ab414f5c9380a6f503f9bd620b141da729e5c190..1f9b0fb651be858b26250012f5396fe6abe3558a 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
@@ -68,9 +68,9 @@
#define MOTOR_BACKLEFT_BASEADDR XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR
#define MOTOR_BACKRIGHT_BASEADDR XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR
-#define ACCEL_X_BIAS -0.028f
-#define ACCEL_Y_BIAS 0.109f
-#define ACCEL_Z_BIAS 0.0686f
+#define ACCEL_X_BIAS -0.005f
+#define ACCEL_Y_BIAS 0.03f
+#define ACCEL_Z_BIAS 0.0f
#define GYRO_X_BIAS -0.001f
#define GYRO_Y_BIAS -0.0135f
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
index 287e6fe876aa72b8576edd87b8d4104c1b46369f..bf8bfeb2abce0485da4f03723be6a10b9e3a6a0b 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_imu.c
@@ -98,8 +98,8 @@ int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
u8 buf[3];
u8 ASAX, ASAY, ASAZ;
- // Quickly read from the factory ROM to get correction coefficents
- int status = mpu9150_write(self->i2c, 0x0A, 0x0F);
+ // Quickly read from the factory ROM to get correction coefficients
+ int status = mpu9150_write(self->i2c, 0x0A, 0x1F);
if(status != 0) {
return status;
}
@@ -126,7 +126,9 @@ int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
struct I2CDriver *i2c = self->i2c;
i16 raw_accel_x, raw_accel_y, raw_accel_z;
+ i16 sensor_raw_accel_x, sensor_raw_accel_y, sensor_raw_accel_z;
i16 gyro_x, gyro_y, gyro_z;
+ i16 sensor_gyro_x, sensor_gyro_y, sensor_gyro_z;
u8 sensor_data[ACCEL_GYRO_READ_SIZE] = {};
@@ -134,9 +136,14 @@ int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
if (error) return error;
//Calculate accelerometer data
- raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
- raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
- raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
+ sensor_raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
+ sensor_raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
+ sensor_raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
+
+ // TODO: Update Matlab model with correct directions.
+ raw_accel_x = sensor_raw_accel_y;
+ raw_accel_y = -sensor_raw_accel_x;
+ raw_accel_z = sensor_raw_accel_z;
// put in G's
gam->accel_x = IMU_ACCX_SIGN * (raw_accel_x / 4096.0) + ACCEL_X_BIAS; // 4,096 is the gain per LSB of the measurement reading based on a configuration range of +-8g
@@ -144,9 +151,14 @@ int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
gam->accel_z = IMU_ACCZ_SIGN * (raw_accel_z / 4096.0) + ACCEL_Z_BIAS;
//Convert gyro data to rate (we're only using the most 12 significant bits)
- gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
- gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
- gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
+ sensor_gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
+ sensor_gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
+ sensor_gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
+
+ //remap
+ gyro_x = sensor_gyro_y;
+ gyro_y = -sensor_gyro_x;
+ gyro_z = sensor_gyro_z;
//Get the number of degrees
//javey: converted to radians to following SI units
@@ -206,6 +218,7 @@ int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
u8 mag_data[6];
u8 mag_status;
i16 raw_magX, raw_magY, raw_magZ;
+ i16 sensor_raw_magX, sensor_raw_magY, sensor_raw_magZ;
int trigger = 0;
@@ -226,9 +239,14 @@ int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
return status;
}
- raw_magX = (mag_data[1] << 8) | mag_data[0];
- raw_magY = (mag_data[3] << 8) | mag_data[2];
- raw_magZ = (mag_data[5] << 8) | mag_data[4];
+ sensor_raw_magX = (mag_data[1] << 8) | mag_data[0];
+ sensor_raw_magY = (mag_data[3] << 8) | mag_data[2];
+ sensor_raw_magZ = (mag_data[5] << 8) | mag_data[4];
+
+ //remap
+ raw_magX = -sensor_raw_magY;
+ raw_magY = sensor_raw_magX;
+ raw_magZ = sensor_raw_magZ;
// Set magnetometer data to output
gam->mag_x = raw_magX * gam->magX_correction;
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c
index 32d0fad0cd243c3e871c58eaaa10ead16c3d246b..8b4fe996034d0ce2a66fcd1f69530e2298fb510f 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_lidar.c
@@ -16,6 +16,8 @@ int zybo_lidar_reset(struct LidarDriver *self, lidar_t *lidar) {
struct I2CDriver *i2c = self->i2c;
int error = 0;
+ //Device wakeup if asleep.
+ lidarlite_write(i2c, 0x00, 0x00);
// Device Reset & Wake up with default settings
error = lidarlite_write(i2c, 0x00, 0x00);
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
index a38e87306620ba54d308d61cd450cf7e817614cc..ddc7971a52b063309245f92af66665241a228953 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
@@ -50,7 +50,7 @@ int test_zybo_mio7_led_and_system() {
* distance of the LIDAR sensor.
*/
int test_zybo_i2c() {
- struct I2CDriver i2c = create_zybo_i2c(0);
+ struct I2CDriver i2c = create_zybo_i2c(1);
struct LidarDriver ld = create_zybo_lidar(&i2c);
i2c.reset(&i2c);
@@ -65,7 +65,7 @@ int test_zybo_i2c() {
int test_zybo_i2c_imu() {
struct I2CDriver i2c = create_zybo_i2c(0);
struct IMUDriver imu = create_zybo_imu(&i2c);
-
+ char buf[100];
gam_t gam;
if (i2c.reset(&i2c)) return 0;
if (imu.reset(&imu, &gam)) return 0;
@@ -73,6 +73,7 @@ int test_zybo_i2c_imu() {
int status = 0;
while (!status) {
status = imu.read(&imu, &gam);
+ usleep(5000);
}
return 0;
}
@@ -306,6 +307,7 @@ int test_zybo_uart_comm() {
unsigned char c;
while (1) {
if (comm.uart->read(comm.uart, &c)) {
+ uart.write(&uart, 0x55);
// read failed
led.turn_off(&led);
} else {
@@ -319,3 +321,48 @@ int test_zybo_uart_comm() {
}
+int test_zybo_pcb() {
+ struct UARTDriver uart = create_zybo_uart(0);
+ struct LEDDriver led = create_zybo_mio7_led();
+ struct RCReceiverDriver rc = create_zybo_rc_receiver();
+ struct MotorDriver motors = create_zybo_motors();
+ uart.reset(&uart);
+ led.reset(&led);
+ rc.reset(&rc);
+ motors.reset(&motors);
+
+ char stateMsg[100];
+ unsigned char c;
+ unsigned char led_state = 0;
+ float channels[6];
+ float pwm[4];
+ int i;
+ while (1) {
+ if(uart.read(&uart, &c) >= 0) {
+ if(led_state) {
+ led.turn_off(&led);
+ led_state = 0;
+ } else {
+ led.turn_on(&led);
+ led_state = 1;
+ }
+ }
+ for (i = 0; i < 6; i++) {
+ rc.read(&rc, i, &channels[i]);
+ }
+ pwm[0] = channels[0]+channels[1]+channels[3];
+ pwm[1] = channels[0]+channels[1]-channels[3];
+ pwm[2] = channels[0]-channels[1]+channels[3];
+ pwm[3] = channels[0]-channels[1]-channels[3];
+ sprintf(stateMsg, "%5.2f %5.2f %5.2f %5.2f %5.2f %5.2f -> %5.2f %5.2f %5.2f %5.2f\r\n", channels[0], channels[1], channels[2], channels[3], channels[4], channels[5], pwm[0], pwm[1], pwm[2], pwm[2]);
+ char* it;
+ for (it = stateMsg; *it; it++) {
+ uart.write(&uart, *it);
+ }
+ for (i = 0; i < 4; i++) {
+ motors.write(&motors, i, pwm[i]);
+ }
+ }
+
+ return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/main.c b/quad/xsdk_workspace_vivado/real_quad/src/main.c
index f6991aca7623d2a99bdba5eb5a048e424874b5ff..ab116d90b27b5011b605f68e6f9cf322bdfda03d 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/main.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/main.c
@@ -47,19 +47,19 @@ int main()
#ifdef RUN_TESTS
//test_zybo_mio7_led_and_system();
- //test_zybo_i2c();
- //test_zybo_i2c_imu();
- test_zybo_i2c_px4flow();
- //test_zybo_i2c_lidar();
- //test_zybo_i2c_all();
- //test_zybo_rc_receiver();
- //test_zybo_motors();
- //test_zybo_uart();
+ //!test_zybo_i2c();
+ //!test_zybo_i2c_imu();
+ //!test_zybo_i2c_px4flow();
+ //!test_zybo_i2c_lidar();
+ //!test_zybo_i2c_all();
+ //!test_zybo_rc_receiver();
+ //!test_zybo_motors();
//test_zybo_axi_timer();
- //test_zybo_uart_comm();
+ //!test_zybo_uart_comm();
return 0;
#endif
+ usleep(2*1000000);
// Run the main quad application
quad_main(setup_hardware);
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.cproject b/quad/xsdk_workspace_vivado/system_bsp/.cproject
index 6bfbc95beafba37a0f6c75224604a1429f5c2eac..8ca4d5f8b1a9d9c24f915b38f1444fd532781eb0 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/.cproject
+++ b/quad/xsdk_workspace_vivado/system_bsp/.cproject
@@ -10,4 +10,10 @@
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+ <storageModule moduleId="scannerConfiguration"/>
+ <storageModule moduleId="org.eclipse.cdt.core.pathentry">
+ <pathentry kind="src" path=""/>
+ <pathentry kind="out" path=""/>
+ </storageModule>
</cproject>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.project b/quad/xsdk_workspace_vivado/system_bsp/.project
index 1773c9f5fef32c05d645b542adf3376c708cb66a..55ab2caf3f47d646d65b0f04a248954f54fb928b 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/.project
+++ b/quad/xsdk_workspace_vivado/system_bsp/.project
@@ -24,6 +24,10 @@
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.location</key>
+ <value></value>
+ </dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
index dd82e57dd062516fb69638e72b1609d20aa13292..ddc03c1e87e6437c14b4ebc865dc30f39d77fc7c 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
+++ b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
@@ -1,4 +1,4 @@
THIRPARTY=false
-HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_0
PROCESSOR=ps7_cortexa9_0
+HW_PROJECT_REFERENCE=design_1_wrapper_hw_platform_1
MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
index b977241ce0281c8722d789ce6adf66e27d21a8ae..7859b0eef626654613361272366cfb818a2a0bab 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/include/bspconfig.h
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
index dc4228399c213e5b3364379b241583b64a634a2a..320af47d83bff268576adca625235c1f4101fe63 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
index 03b400a0b64f9c2729ef4eeaa30c3ce3bf558dbf..3bfe837e0ef1e40efbd23b458e8bcfd229590ca2 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
index 095bfd7a903232d96cfa338140039cb74b34ce71..0987122615b0139e167a23f1d96571e95806e7ca 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
index 0afd3205d9bb30da9d6ce39a7e5142d65f56c7f3..d6e9244b00b0bebe61df367d3dbcdb5934d318f1 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
index 1a24fb0d07749ee5ab3e55babf641b6573ab30b0..25b9b1fafe923ad99066d2fc97f5bcea5e50ac49 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
index f98336c627bb7de57cc461facd8b4c0fa253068b..e821c1a134918abe540d6f36caaf92d94ce299fb 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
index 34f07519d9db0aa60e5872868572a391927ff755..a7ced170816f9b4b020a55a46c0375c9ecbf2623 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
index 528e09902e89e1a04ce628dbac7ca2f7fa980113..faad4ae4dd6879daf15ea7c3c90bc797e9812434 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
index 1634bb77ceb74c5c5325768877cfea3a8c12e2b7..34b06867d26ef87262eebaa7981cbf6c18c32546 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
index 14fbf75dbd471e0271aded1f82d08651cc8bfa03..ae52c194c68ab316223c512f8384f34b33f6a2b7 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
index 4fcd04067d51f298a543e99e2ea8aea6f59693c6..e4456f8b19ccf0cbc73e2b5bb4d6044aa310906e 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c
index 73390f7b69902bb427ec56baece04db277b1d508..1857fbc41aceb851b414d9ab56f861a8c419f0ff 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v4_4/src/xtmrctr_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
index ed841e0babce39b3ba339abc827c2e843d3ede70..6ea3eb7688466ccec2d0c67260a53ec5ea942f8d 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
index 947f86f29c23a5dadeb630f87713f96b27d0ab60..bb6cff341a3a4491eb488591c2d18011b3eb79a4 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
diff --git a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
index 157bd00bdeea9470223f5d8bb56dc0b1358244d1..ab17ec3f0758694622d106b1c03879dd6717feb3 100644
--- a/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
+++ b/quad/xsdk_workspace_vivado/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
@@ -5,7 +5,7 @@
* Version:
* DO NOT EDIT.
*
-* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2019 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights