diff --git a/groundStation/.gitignore b/groundStation/.gitignore
index 508a8f243429591a76f612c87353c847358052e0..3c404365ac685a5329202185291efb21aefa35b1 100644
--- a/groundStation/.gitignore
+++ b/groundStation/.gitignore
@@ -42,3 +42,10 @@ logs
BackEnd
obj
Cli
+
+#symlinks
+getpid
+monitor
+setpid
+setsetpoint
+getsetpoint
diff --git a/groundStation/Makefile b/groundStation/Makefile
index 32c9062ef683a66deef45a0cf04334bf016d9e17..052f6bf8af89e079a93dd4c77711609316aead99 100644
--- a/groundStation/Makefile
+++ b/groundStation/Makefile
@@ -23,7 +23,7 @@ CLIBINARY=Cli
CLISRCDIR=src/cli
CLISOURCES := $(wildcard $(CLISRCDIR)/*.c)
CLIOBJECTS = $(CLISOURCES:$(CLISRCDIR)/%.c=$(OBJDIR)/%.o)
-SYMLINKS=monitor setpid getpid setsetpoint
+SYMLINKS=monitor setpid getpid setsetpoint getsetpoint
# Frontend-common stuff
FESRCDIR=src/frontend
diff --git a/groundStation/src/backend/backend.c b/groundStation/src/backend/backend.c
index f521cf732807359df10b4e607111c360d9f26a0d..7efcbc855495ddda5661de6627d3b005372cfd79 100644
--- a/groundStation/src/backend/backend.c
+++ b/groundStation/src/backend/backend.c
@@ -195,7 +195,6 @@ int main(int argc, char **argv)
perror("Error creating log file...");
exit(1);
}
- // writeStringToLog(logHeader);
// watch for input from stdin (fd 0) to see when it has input
safe_fd_set(fileno(stdin), &rfds_master, &max_fd);
@@ -328,8 +327,8 @@ void sendVrpnPacket(struct ucart_vrpn_TrackerData *info) {
memcpy(&packet[11], &(info->y), 4);
memcpy(&packet[15], &(info->x), 4);
memcpy(&packet[19], &(info->z), 4);
- memcpy(&packet[23], &(info->pitch), 4);
- memcpy(&packet[27], &(info->roll), 4);
+ memcpy(&packet[23], &(info->roll), 4);
+ memcpy(&packet[27], &(info->pitch), 4);
memcpy(&packet[31], &(info->yaw), 4);
char checksum = 0;
@@ -482,6 +481,9 @@ static ssize_t writeQuad(const char * buf, size_t count) {
static ssize_t readQuad(char * buf, size_t count) {
ssize_t retval;
+ if (getenv(NOQUAD_ENV)) {
+ return count;
+ }
if (pthread_mutex_lock(&quadSocketMutex)) {
err(-2, "pthrtead_mutex_lock (%s:%d):", __FILE__, __LINE__);
}
@@ -626,7 +628,7 @@ static void client_recv(int fd) {
if (tracker == NULL) {
char * dummy = TD_MAGIC " 1.0 2.0 3.0 4.0 5.0 6.0\n";
write(fd, dummy, strlen(dummy));
- }else if (ucart_vrpn_tracker_getData(tracker, &td)) {
+ } else if (ucart_vrpn_tracker_getData(tracker, &td)) {
write(fd, TD_MAGIC " ERROR\n", strlen(TD_MAGIC " ERROR\n"));
} else {
/* more than sufficient buffer */
@@ -651,17 +653,19 @@ static void client_recv(int fd) {
}
}
} else {
- if(clientAddPendResponses(fd, packet) == -1) {
- warnx("Ran out of room! Consider increasing CLIENT_MAX_PENDING_RESPONSES!\n");
- } else {
- int datalen = (packet[6] << 8) | (packet[5]);
- printf("sending %lf '", getFloat(packet, 7));
- for(int i = 0; i < datalen + 8; ++i) {
- printf(" 0x%x", (signed) packet[i]);
+ if (packet[1] == 0x02) {
+ if (clientAddPendResponses(fd, packet) == -1) {
+ warnx("Ran out of room! Consider increasing CLIENT_MAX_PENDING_RESPONSES!\n");
}
- printf("'\n");
- writeQuad((char *) packet, datalen +8);
}
+
+ int datalen = (packet[6] << 8) | (packet[5]);
+ printf("sending %lf '", getFloat(packet, 7));
+ for(int i = 0; i < datalen + 8; ++i) {
+ printf(" 0x%.2x", (signed) packet[i]);
+ }
+ printf("'\n");
+ writeQuad((char *) packet, datalen +8);
}
char * rest = &buffer[newline] + 1;
@@ -707,17 +711,23 @@ static void quad_recv() {
respBufLen = 0;
return;
}
-
+
/* Get datalen */
size_t datalen = metadata.data_len;
+ if (respBufLen < datalen + 8) {
+ /* Packet not yet fully read */
+ return;
+ }
+
if (datalen > CMD_MAX_LENGTH - 8) {
/* Very invalid packet. Nuke that shit */
+ warnx("data len is over the maximum packet length. Try reducing the data in the packet sent to the groundstation.\n");
respBufLen = 0;
return;
}
-
- if (respBufLen < datalen + 8) {
- /* Packet not yet fully read */
+
+ if(validPacket == -2) {
+ fprintf(stderr, "Checksums did not match (Parse Packet)\n");
return;
}
@@ -726,10 +736,18 @@ static void quad_recv() {
char * cmdText = MessageTypes[(int)metadata.msg_type].subtypes[(int)metadata.msg_subtype].cmdText;
float value = getFloat((unsigned char *)respBuf, 7);
//printf("Quad : %s, %lf\n", cmdText, value);
+
/*
Assuming the quad sends the correct info.. This hasn't been tested yet due to a lack of
quad software. We can check how to format by the cmdText and pass to every client.
*/
+ if(strncmp(cmdText, "log", strlen(cmdText)) == 0) {
+ char log_text[datalen+1];
+ strncpy(log_text, (char *) data, datalen);
+ log_text[datalen] = '\0';
+ printf("log='%s'\n", log_text);
+ }
+
char buffer[1048];
sprintf(buffer, "%s %lf\n", cmdText, value);
@@ -738,8 +756,6 @@ static void quad_recv() {
write(fd, buffer, datalen + 8);
}
}
- } else {
- warnx("Checksum mismatch!");
}
memmove(respBuf, respBuf + datalen + 8, respBufLen - (datalen + 8));
respBufLen -= datalen + 8;
diff --git a/groundStation/src/backend/callbacks.h b/groundStation/src/backend/callbacks.h
index 57d6fbbbbab784744714340ddc943ee3a91dccf2..d04d4fda5dd8c23a2df61cc00594755652a14f89 100644
--- a/groundStation/src/backend/callbacks.h
+++ b/groundStation/src/backend/callbacks.h
@@ -1,5 +1,5 @@
-#ifndef __callbacks_h
-#define __callbacks_h
+#ifndef __CALLBACKS_H
+#define __CALLBACKS_H
/* Grab some stupid stuff from legacy code */
#include "type_def.h"
@@ -8,4 +8,4 @@
typedef void (command_cb)(unsigned char *command,
int dataLen, modular_structs_t *structs);
-#endif
+#endif /* __CALLBACKS_H */
diff --git a/groundStation/src/backend/cb_default.h b/groundStation/src/backend/cb_default.h
index 2deeb4756b3d708ed617209330fab36f5d1c208b..45485767cc34d1619090014bc2f1428f146b1c71 100644
--- a/groundStation/src/backend/cb_default.h
+++ b/groundStation/src/backend/cb_default.h
@@ -1,3 +1,6 @@
+#ifndef __CB_DEFAULT_H
+#define __CB_DEFAULT_H
+
#include "commands.h"
/* The cb_default used on the groundStation. This file MUST NOT BE INCLUDED
@@ -8,3 +11,5 @@ int cb_default(unsigned char * command, int dataLen, modular_structs_t *structs)
{
return 0;
}
+
+#endif /* __CB_DEFAULT_H */
\ No newline at end of file
diff --git a/groundStation/src/backend/commands.h b/groundStation/src/backend/commands.h
index aeb11ad20e57b50f6c8757009766a3e4d022abe2..a3ef5d75297dce9ea2526289617b6b5ad7d10b69 100644
--- a/groundStation/src/backend/commands.h
+++ b/groundStation/src/backend/commands.h
@@ -1,5 +1,5 @@
-#ifndef _COMMANDS_H
-#define _COMMANDS_H
+#ifndef __COMMANDS_H
+#define __COMMANDS_H
#include <stdio.h>
#include <stdlib.h>
@@ -75,4 +75,4 @@ float getFloat(unsigned char* str, int pos);
int getInt(unsigned char* str, int pos);
/* end legacy crap */
-#endif
+#endif /* __COMMANDS_H */
diff --git a/groundStation/src/backend/communication.c b/groundStation/src/backend/communication.c
index 19ea73ae4cf7c8f7f8a35bf8b316bf28e19e7903..ca4e82632ce36c0b381eb3dd49c42777cdd84942 100644
--- a/groundStation/src/backend/communication.c
+++ b/groundStation/src/backend/communication.c
@@ -177,7 +177,7 @@ int formatPacket(metadata_t *metadata, void *data, unsigned char **formattedComm
// Checksum
// receive data and calculate checksum
int i;
- char data_checksum;
+ char data_checksum = 0;
for(i = 0; i < 7 + metadata->data_len; i++)
{
data_checksum ^= (*formattedCommand)[i];
@@ -230,14 +230,13 @@ int parse_packet(unsigned char * packet, unsigned char ** data, metadata_t * met
// calculate checksum
unsigned char calculated_checksum = 0;
- for(i = 0; i < meta_data->data_len + 7; i++)
+ for(i = 0; i < meta_data->data_len + 7 - 1; i++)
{
calculated_checksum ^= packet[i];
}
// compare checksum
if(packet_checksum != calculated_checksum) {
- fprintf(stderr, "Checksums did not match (Parse Packet): 0x%02x\t0x%02x\n", packet_checksum, calculated_checksum);
return -2;
}
diff --git a/groundStation/src/backend/communication.h b/groundStation/src/backend/communication.h
index 746b9f5d45ce9199588ff45b58f5bdaa5d669ad3..364814e3674b25a868e5e516e0bc626dd976b295 100644
--- a/groundStation/src/backend/communication.h
+++ b/groundStation/src/backend/communication.h
@@ -1,5 +1,5 @@
-#ifndef _COMMUNICATION_H
-#define _COMMUNICATION_H
+#ifndef __COMMUNICATION_H
+#define __COMMUNICATION_H
#include <stdio.h>
#include <string.h>
@@ -16,4 +16,4 @@ int parse_packet(unsigned char * packet, unsigned char ** data, metadata_t * met
int processCommand(unsigned char *command, modular_structs_t *structs);
int logData(unsigned char *log_msg, unsigned char *formattedCommand);
-#endif
\ No newline at end of file
+#endif /* __COMMUNICATION_H */
\ No newline at end of file
diff --git a/groundStation/src/backend/config.h b/groundStation/src/backend/config.h
index bf88e6e2b7cf09db273dba3ecc5bcf3cee7d2211..64691610dbfd8282fec14d3706db4219e06dfbc1 100644
--- a/groundStation/src/backend/config.h
+++ b/groundStation/src/backend/config.h
@@ -17,4 +17,4 @@
#define QUAD_PORT_ENV "UCART_QUAD_PORT"
#define QUAD_PORT_DEFAULT 8080
-#endif
+#endif /* __CONFIG_H */
\ No newline at end of file
diff --git a/groundStation/src/backend/logger.h b/groundStation/src/backend/logger.h
index edfb365ffce6606e7b5bd8d1f4305c5f697180a9..9bbd068116482e4d693fdb519f27dffd7bc2fff7 100644
--- a/groundStation/src/backend/logger.h
+++ b/groundStation/src/backend/logger.h
@@ -2,8 +2,8 @@
*
* Logger header file for holding info pertaining to loging to a file.
*/
-#ifndef _LOGGER_H
-#define _LOGGER_H
+#ifndef __LOGGER_H
+#define __LOGGER_H
#include <fcntl.h>
#include <time.h>
@@ -18,4 +18,4 @@ int updateLogFile(const struct ucart_vrpn_TrackerData* );
void closeLogFile();
-#endif
+#endif /* __LOGGER_H */
\ No newline at end of file
diff --git a/groundStation/src/backend/type_def.h b/groundStation/src/backend/type_def.h
index 55dca9e8fb27c26397b00961b7dbec8bbe0d4136..2a2b8249a4c62cb035a38a6c4b6f3abfe96edd89 100644
--- a/groundStation/src/backend/type_def.h
+++ b/groundStation/src/backend/type_def.h
@@ -5,8 +5,8 @@
* Author: ucart
*/
-#ifndef TYPE_DEF_H_
-#define TYPE_DEF_H_
+#ifndef __TYPE_DEF_H
+#define __TYPE_DEF_H
/**
* @brief
@@ -358,4 +358,4 @@ typedef struct {
//////// END MAIN MODULAR STRUCTS
-#endif /* TYPE_DEF_H_ */
+#endif /* __TYPE_DEF_H */
diff --git a/groundStation/src/cli/cli.c b/groundStation/src/cli/cli.c
index acec4dbc6352ca971b84289eb24cfc918da98bbd..8eed2381b6a8440635adbce3a5dcf78460f05cde 100644
--- a/groundStation/src/cli/cli.c
+++ b/groundStation/src/cli/cli.c
@@ -76,6 +76,8 @@ int main(int argc, char **argv)
needCommandHelp = 1;
}
}
+
+ printf("made it\n");
/**
* I the user has asked for help, and we have already found
diff --git a/groundStation/src/cli/cli.h b/groundStation/src/cli/cli.h
index 1d0cf6951488872906ac99447fda3b7b5e9e5b7c..e82bd5cda7e1d31d2aa31dffee2ac30a2fa372f1 100644
--- a/groundStation/src/cli/cli.h
+++ b/groundStation/src/cli/cli.h
@@ -2,6 +2,7 @@
#define __CLI_H
#include "cli_setsetpoint.h"
+#include "cli_getsetpoint.h"
#include "cli_monitor.h"
#include "cli_setpid.h"
#include "cli_getpid.h"
@@ -13,6 +14,7 @@ enum CommandNameIds{
CMD_SETPID,
CMD_GETIMU,
CMD_SETSETPOINT,
+ CMD_GETSETPOINT,
MAX_COMMANDS
};
@@ -22,7 +24,8 @@ static cli_function_ptr cli_functions[] = {
&cli_getpid,
&cli_setpid,
&cli_getimu,
- &cli_setsetpoint
+ &cli_setsetpoint,
+ &cli_getsetpoint
};
static char* commandNames[MAX_COMMANDS] = {
@@ -30,7 +33,8 @@ static char* commandNames[MAX_COMMANDS] = {
"getpid",
"setpid",
"getimu",
- "setsetpoint"
+ "setsetpoint",
+ "getsetpoint"
};
-#endif
+#endif /* __CLI_H */
\ No newline at end of file
diff --git a/groundStation/src/cli/cli_getimu.h b/groundStation/src/cli/cli_getimu.h
index 59089a01722683324edd00e8811d4ac9876143e8..2535f1ae87dfba4cb616adb0aa72e686c2cd4fe7 100644
--- a/groundStation/src/cli/cli_getimu.h
+++ b/groundStation/src/cli/cli_getimu.h
@@ -1,8 +1,8 @@
-#ifndef CLI_GETIMU_H
-#define CLI_GETIMU_H
+#ifndef __CLI_GETIMU_H
+#define __CLI_GETIMU_H
#include "frontend_getimu.h"
int cli_getimu(struct backend_conn * conn, int argc, char ** argv);
-#endif
\ No newline at end of file
+#endif /* __CLI_GETIMU_H */
\ No newline at end of file
diff --git a/groundStation/src/cli/cli_getpid.c b/groundStation/src/cli/cli_getpid.c
index 48c1e72055601df9b66e96ec1c2a3917c1f0fc15..4bf634e3e2e966ea59ac54d8510c3607815f462d 100644
--- a/groundStation/src/cli/cli_getpid.c
+++ b/groundStation/src/cli/cli_getpid.c
@@ -62,62 +62,62 @@ int cli_getpid(struct backend_conn * conn, int argc, char **argv) {
if(getAll) {
for(int i = 0; i < PID_NUM_PIDS; ++i) {
pid_data.controller = i;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
} else {
if(getPitch) {
pid_data.controller = PID_PITCH;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getRoll) {
pid_data.controller = PID_ROLL;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getYaw) {
pid_data.controller = PID_YAW;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getPitchV) {
pid_data.controller = PID_PITCH_RATE;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getRollV) {
pid_data.controller = PID_ROLL_RATE;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getYawV) {
pid_data.controller = PID_YAW_RATE;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getHeight) {
pid_data.controller = PID_HEIGHT;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getLat) {
pid_data.controller = PID_LAT;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
if(getLong) {
pid_data.controller = PID_LONG;
- if ((result = getValues(conn, &pid_data))) {
+ if ((result = getPidValues(conn, &pid_data))) {
return result;
}
}
@@ -127,7 +127,7 @@ int cli_getpid(struct backend_conn * conn, int argc, char **argv) {
return 0;
}
-int getValues(struct backend_conn * conn, struct frontend_pid_data * pid_data) {
+int getPidValues(struct backend_conn * conn, struct frontend_pid_data * pid_data) {
if(frontend_getpid(conn, pid_data)) {
return 1;
}
diff --git a/groundStation/src/cli/cli_getpid.h b/groundStation/src/cli/cli_getpid.h
index f5c0b15e4a2f2c7c5ad605a389b0c1b52a1344a6..799681f06d114602083e304f2cba321891155fbc 100644
--- a/groundStation/src/cli/cli_getpid.h
+++ b/groundStation/src/cli/cli_getpid.h
@@ -1,9 +1,9 @@
-#ifndef CLI_GETPID_H
-#define CLI_GETPID_H
+#ifndef __CLI_GETPID_H
+#define __CLI_GETPID_H
#include "frontend_getpid.h"
-int getValues(struct backend_conn *, struct frontend_pid_data *);
+int getPidValues(struct backend_conn *, struct frontend_pid_data *);
int cli_getpid(struct backend_conn * conn, int argc, char ** argv);
-#endif
\ No newline at end of file
+#endif /* __CLI_GETPID_H */
\ No newline at end of file
diff --git a/groundStation/src/cli/cli_getsetpoint.c b/groundStation/src/cli/cli_getsetpoint.c
new file mode 100644
index 0000000000000000000000000000000000000000..be9766139e002fb2687bab6fc76a54bb8d96b29b
--- /dev/null
+++ b/groundStation/src/cli/cli_getsetpoint.c
@@ -0,0 +1,131 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <getopt.h>
+
+#include "cli_getsetpoint.h"
+
+int cli_getsetpoint(struct backend_conn * conn, int argc, char **argv) {
+ int c;
+ static int getheight = 0, getlat = 0, getlong = 0;
+ static int getpitch = 0, getroll = 0, getyaw = 0;
+ struct frontend_setpoint_data setpoint_data;
+ static int needHelp = 0;
+ static int mask;
+ static struct option long_options[] = {
+ /* These options don’t set a flag. We distinguish them by their indices. */
+ {"help", no_argument, &needHelp, 1},
+ {"height", no_argument, &getheight, 1},
+ {"long", no_argument, &getlong, 1},
+ {"lat", no_argument, &getlat, 1},
+ {"pitch", no_argument, &getpitch, 1},
+ {"roll", no_argument, &getroll, 1},
+ {"yaw", no_argument, &getyaw, 1},
+ {0, 0, 0, 0}
+ };
+
+ while (1)
+ {
+ /* getopt_long stores the option index here. */
+ int option_index = 0;
+
+ c = getopt_long(argc, argv, "a", long_options, &option_index);
+
+ /* Detect the end of the options. */
+ if (c == -1)
+ break;
+
+ if (c == 'a') {
+ getheight = 1;
+ getlat = 1;
+ getlong = 1;
+ getpitch = 1;
+ getroll = 1;
+ getyaw = 1;
+ }
+ }
+
+ if (needHelp) {
+ printf("Getsetpoint gets the height, lat, long, pitch, roll and yaw set point values for the quad.\n");
+ printf("Usage Syntax : \n\t./Cli getsetpoint [options...]\n");
+ printf("Symlink Usage Syntax : \n\t./getsetpoint [options...]\n\n");
+ printf("Available options include the following\n");
+ printf("\t[-a] : Gets all of the following setpoints\n");
+ printf("\t[--height] : Gets the height setpoint\n");
+ printf("\t[--lat] : Gets the latitude setpoint\n");
+ printf("\t[--long] : Gets the longitude setpoint\n");
+ printf("\t[--pitch] : Gets the pitch setpoint\n");
+ printf("\t[--roll] : Gets the roll setpoint\n");
+ printf("\t[--yaw] : Gets the yaw setpoint\n");
+ return 0;
+ }
+
+ if (argc < 2) {
+ printf("Incorrect Usage, run './cli getsetpoint --help' for correct usage.\n");
+ return 1;
+ }
+ int result;
+ if(getheight) {
+ if ((result = getSetPointValues(conn, &setpoint_data, HEIGHT))) {
+ return result;
+ }
+ }
+ if(getlat) {
+ if ((result = getSetPointValues(conn, &setpoint_data, LAT))) {
+ return result;
+ }
+ }
+ if(getlong) {
+ if ((result = getSetPointValues(conn, &setpoint_data, LONGG))) {
+ return result;
+ }
+ }
+ if(getpitch) {
+ if ((result = getSetPointValues(conn, &setpoint_data, PITCH))) {
+ return result;
+ }
+ }
+ if(getroll) {
+ if ((result = getSetPointValues(conn, &setpoint_data, ROLL))) {
+ return result;
+ }
+ }
+ if(getyaw) {
+ if ((result = getSetPointValues(conn, &setpoint_data, YAW))) {
+ return result;
+ }
+ }
+
+ return 0;
+}
+
+int getSetPointValues(struct backend_conn * conn, struct frontend_setpoint_data * setpoint_data, int type) {
+ if(frontend_getsetpoint(conn, setpoint_data, type)) {
+ return 1;
+ }
+
+ switch(type) {
+ case HEIGHT :
+ printf("Height: %f\n",
+ setpoint_data->height);
+ break;
+ case LAT :
+ printf("Latitude: %f\n",
+ setpoint_data->lat);
+ case LONGG :
+ printf("Longitude: %f\n",
+ setpoint_data->longg);
+ case PITCH :
+ printf("Pitch: %f\n",
+ setpoint_data->pitch);
+ break;
+ case ROLL :
+ printf("Roll: %f\n",
+ setpoint_data->roll);
+ case YAW :
+ printf("Yaw: %f\n",
+ setpoint_data->yaw);
+ default :
+ break;
+ }
+ return 0;
+}
diff --git a/groundStation/src/cli/cli_getsetpoint.h b/groundStation/src/cli/cli_getsetpoint.h
new file mode 100644
index 0000000000000000000000000000000000000000..a852b37973c84b21ca985e89dbb90180f35907ba
--- /dev/null
+++ b/groundStation/src/cli/cli_getsetpoint.h
@@ -0,0 +1,18 @@
+#ifndef __CLI_GETSETPOINT_H
+#define __CLI_GETSETPOINT_H
+
+#include "frontend_getsetpoint.h"
+
+enum {
+ HEIGHT,
+ LAT,
+ LONGG,
+ PITCH,
+ ROLL,
+ YAW
+};
+
+int getSetPointValues(struct backend_conn *, struct frontend_setpoint_data *, int type);
+int cli_getsetpoint(struct backend_conn * conn, int argc, char ** argv);
+
+#endif /* __CLI_GETSETPOINT_H */
\ No newline at end of file
diff --git a/groundStation/src/cli/cli_monitor.h b/groundStation/src/cli/cli_monitor.h
index 308721bb89f177da345269971a8d63b32d9dc39c..694323739001d0b0e1b820c37b87ff95362f27e5 100644
--- a/groundStation/src/cli/cli_monitor.h
+++ b/groundStation/src/cli/cli_monitor.h
@@ -1,5 +1,5 @@
-#ifndef CLI_MONITOR_H
-#define CLI_MONITOR_H
+#ifndef __CLI_MONITOR_H
+#define __CLI_MONITOR_H
#include <time.h>
@@ -11,4 +11,4 @@ int cli_monitor(struct backend_conn * conn, int argc, char **argv);
// Return 0 on success and 1 otherwise
int monitor(struct backend_conn * conn);
-#endif
\ No newline at end of file
+#endif /* __CLI_MONITOR_H */
\ No newline at end of file
diff --git a/groundStation/src/cli/cli_setpid.h b/groundStation/src/cli/cli_setpid.h
index 2ebdc9545e38f9f3d3697b02b22b8b1be2ef324e..d78fcc07042d7d571f35940f798493a5c8cb1c88 100644
--- a/groundStation/src/cli/cli_setpid.h
+++ b/groundStation/src/cli/cli_setpid.h
@@ -1,8 +1,8 @@
-#ifndef CLI_SETPID_H
-#define CLI_SETPID_H
+#ifndef __CLI_SETPID_H
+#define __CLI_SETPID_H
#include "frontend_setpid.h"
int cli_setpid(struct backend_conn * conn, int argc, char ** argv);
-#endif
+#endif /* __CLI_SETPID_H */
\ No newline at end of file
diff --git a/groundStation/src/cli/cli_setsetpoint.c b/groundStation/src/cli/cli_setsetpoint.c
index 85cd86d164712e0a83ef7bdc64bd1b50a0ffeee3..e0c43814ff98b2e5326b2d6feb0e14fa468d9032 100644
--- a/groundStation/src/cli/cli_setsetpoint.c
+++ b/groundStation/src/cli/cli_setsetpoint.c
@@ -4,15 +4,22 @@
#include "cli_setsetpoint.h"
-int cli_set(struct backend_conn * conn, int argc, char **argv) {
+int cli_setsetpoint(struct backend_conn * conn, int argc, char **argv) {
int c;
- static int setX = 0, setY = 0, setZ = 0;
+ static int setheight = 0, setlat = 0, setlong = 0;
+ static int setpitch = 0, setroll = 0, setyaw = 0;
struct frontend_setpoint_data setpoint_data;
static int needHelp = 0;
static int mask;
static struct option long_options[] = {
/* These options don’t set a flag. We distinguish them by their indices. */
- {"help", no_argument, &needHelp, 1},
+ {"help", no_argument, &needHelp, 1},
+ {"height", required_argument, 0, 'h'},
+ {"long", required_argument, 0, 'l'},
+ {"lat", required_argument, 0, 't'},
+ {"pitch", required_argument, 0, 'p'},
+ {"roll", required_argument, 0, 'r'},
+ {"yaw", required_argument, 0, 'y'},
{0, 0, 0, 0}
};
@@ -21,38 +28,54 @@ int cli_set(struct backend_conn * conn, int argc, char **argv) {
/* getopt_long stores the option index here. */
int option_index = 0;
- c = getopt_long(argc, argv, "x:y:z:", long_options, &option_index);
+ c = getopt_long(argc, argv, "", long_options, &option_index);
/* Detect the end of the options. */
if (c == -1)
break;
switch(c) {
- case 'x' :
- setpoint_data.x = atof(optarg);
- mask |= SET_X;
+ case 'h' :
+ setpoint_data.height = atof(optarg);
+ mask |= SET_HEIGHT;
break;
- case 'y' :
- setpoint_data.y = atof(optarg);
- mask |= SET_Y;
+ case 't' :
+ setpoint_data.lat = atof(optarg);
+ mask |= SET_LAT;
+ break;
+ case 'l' :
+ setpoint_data.longg = atof(optarg);
+ mask |= SET_LONG;
+ break;
+ case 'p' :
+ setpoint_data.pitch = atof(optarg);
+ mask |= SET_PITCH;
break;
- case 'z' :
- setpoint_data.z = atof(optarg);
- mask |= SET_Z;
+ case 'r' :
+ setpoint_data.roll = atof(optarg);
+ mask |= SET_ROLL;
+ break;
+ case 'y' :
+ setpoint_data.yaw = atof(optarg);
+ mask |= SET_YAW;
break;
default :
break;
}
+
}
if (needHelp) {
- printf("Setsetpoint sets the x, y , or z set point values for the quad.\n");
+ printf("Setsetpoint sets the height, lat, long, pitch, roll, or yaw set point values for the quad.\n");
printf("Usage Syntax : \n\t./Cli setsetpoint [options...]\n");
printf("Symlink Usage Syntax : \n\t./setsetpoint [options...]\n\n");
printf("Available options include the following\n");
- printf("\t[-x] 'val' : Sets the x setpoint value to 'val'\n");
- printf("\t[-z] 'val' : Sets the y setpoint value to 'val'\n");
- printf("\t[-z] 'val' : Sets the z setpoint value to 'val'\n");
+ printf("\t[--height] 'val' : Sets the height setpoint value to 'val'\n");
+ printf("\t[--lat] 'val' : Sets the latitude setpoint value to 'val'\n");
+ printf("\t[--long] 'val' : Sets the longitude setpoint value to 'val'\n");
+ printf("\t[--pitch] 'val' : Sets the pitch setpoint value to 'val'\n");
+ printf("\t[--roll] 'val' : Sets the roll setpoint value to 'val'\n");
+ printf("\t[--yaw] 'val' : Sets the yaw setpoint value to 'val'\n");
return 0;
}
diff --git a/groundStation/src/cli/cli_setsetpoint.h b/groundStation/src/cli/cli_setsetpoint.h
index 8f2657963222181f4fcf7e20fae9242d84b37b95..514145a9485733276fb1982418f5a44747103e74 100644
--- a/groundStation/src/cli/cli_setsetpoint.h
+++ b/groundStation/src/cli/cli_setsetpoint.h
@@ -1,8 +1,8 @@
-#ifndef CLI_SETSETPOINT_H
-#define CLI_SETSETPOINT_H
+#ifndef __CLI_SETSETPOINT_H
+#define __CLI_SETSETPOINT_H
#include "frontend_setsetpoint.h"
int cli_setsetpoint(struct backend_conn * conn, int argc, char ** argv);
-#endif /* CLI_SETSETPOINT_H */
+#endif /* __CLI_SETSETPOINT_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_common.c b/groundStation/src/frontend/frontend_common.c
index cbedbe42a6dcbed1622f2109d833a75a1ce6d7ba..e71bc425e28aaa8514474e6df7cc078b46261e24 100644
--- a/groundStation/src/frontend/frontend_common.c
+++ b/groundStation/src/frontend/frontend_common.c
@@ -33,7 +33,7 @@ struct backend_conn * ucart_backendConnect()
struct backend_conn * conn = NULL;
- printf("Trying to connect...\n");
+ printf("Trying to connect...");
remote.sun_family = AF_UNIX;
char * sock_env = getenv(SOCKET_ENV);
@@ -60,6 +60,7 @@ struct backend_conn * ucart_backendConnect()
warn("setvbuf");
}
+ printf("Success\n");
/* success */
goto fail_final;
@@ -68,6 +69,7 @@ fail_malloc_conn:
conn = NULL;
fail_sock:
close(s);
+ printf("Failure\n");
fail_final:
return conn;
}
diff --git a/groundStation/src/frontend/frontend_common.h b/groundStation/src/frontend/frontend_common.h
index c8ea7877190c29ff41f02f9aa92a3987c80e2de6..60ee336269ee95388ed4f334ac1e3dfbe6e143bb 100644
--- a/groundStation/src/frontend/frontend_common.h
+++ b/groundStation/src/frontend/frontend_common.h
@@ -1,5 +1,5 @@
-#ifndef FRONTEND_COMMON_H
-#define FRONTEND_COMMON_H
+#ifndef __FRONTEND_COMMON_H
+#define __FRONTEND_COMMON_H
#include <stdlib.h>
struct backend_conn;
@@ -19,4 +19,4 @@ char * ucart_backendGetline(struct backend_conn * conn);
/* Write a line to the backend */
int ucart_backendWrite(struct backend_conn * backend, const char * line);
-#endif
+#endif /* __FRONTEND_COMMON_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_getimu.h b/groundStation/src/frontend/frontend_getimu.h
index c95784a1d4aada157283aa40ca74cd0fb211d505..1747252bbc78a403799fb0744c91e2b04883c0cb 100644
--- a/groundStation/src/frontend/frontend_getimu.h
+++ b/groundStation/src/frontend/frontend_getimu.h
@@ -1,6 +1,6 @@
-#ifndef FRONTEND_GETIMU_H
-#define FRONTEND_GETIMU_H
+#ifndef __FRONTEND_GETIMU_H
+#define __FRONTEND_GETIMU_H
#include "frontend_common.h"
-#endif
\ No newline at end of file
+#endif /* __FRONTEND_GETIMU_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_getpid.c b/groundStation/src/frontend/frontend_getpid.c
index e7e21cfebbcaaae0e276e515f837716cd3d694c6..08827a528fdaec30b36910e5d91438100c12e4de 100644
--- a/groundStation/src/frontend/frontend_getpid.c
+++ b/groundStation/src/frontend/frontend_getpid.c
@@ -1,6 +1,7 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
+#include <err.h>
#include "frontend_getpid.h"
#include "pid_common.h"
@@ -60,5 +61,23 @@ int frontend_getpid(
return 1;
}
+ char * response;
+ for (;;) {
+ response = ucart_backendGetline(conn);
+ if (response == NULL) {
+ warnx("Line not returned from backend");
+ return 1;
+ }
+ printf("received : %s\n", response);
+ // if (strncmp(response, MAGIC, strlen(MAGIC)) == 0) {
+ // break;
+ // }
+ }
+
+ // if (strncmp(response, MAGIC " ERROR", strlen(MAGIC " ERROR")) == 0) {
+ // warnx("Backend returned an error: %s", strstr(response, "ERROR"));
+ // return 1;
+ // }
+
return 0;
}
diff --git a/groundStation/src/frontend/frontend_getpid.h b/groundStation/src/frontend/frontend_getpid.h
index 977ae97f314a3c5b3891f5d60e56929aa03d6db9..e7933f1abf1869ac7f3074d472c8a8a36106507c 100644
--- a/groundStation/src/frontend/frontend_getpid.h
+++ b/groundStation/src/frontend/frontend_getpid.h
@@ -1,5 +1,5 @@
-#ifndef FRONTEND_GETPID_H
-#define FRONTEND_GETPID_H
+#ifndef __FRONTEND_GETPID_H
+#define __FRONTEND_GETPID_H
#include "frontend_common.h"
#include "pid_common.h"
@@ -23,4 +23,4 @@ int frontend_getpid(
struct frontend_pid_data * pid_data);
-#endif
+#endif /* __FRONTEND_GETPID_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_getsetpoint.c b/groundStation/src/frontend/frontend_getsetpoint.c
new file mode 100644
index 0000000000000000000000000000000000000000..1268416f5a9e0a0a32d4735935691cba6be516ae
--- /dev/null
+++ b/groundStation/src/frontend/frontend_getsetpoint.c
@@ -0,0 +1,52 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "frontend_getsetpoint.h"
+#include "setpoint_common.h"
+#include "cli_getsetpoint.h"
+
+/* Get a specified setpoint.
+ *
+ * Example:
+ *
+ * struct frontend_setpoint_data setpoint_data;
+ * if (frontend_getpid(conn, &pid_data)) {
+ * error
+ * } else {
+ * setpoint_data.height, setpoint_data.lat, and setpoint.long are filled
+ * }
+ *
+ * Returns 0 on success, 1 on error
+ */
+int frontend_getsetpoint(
+ struct backend_conn * conn, struct frontend_setpoint_data * setpoint_data, int type) {
+
+ char line[25] = "";
+ switch (type) {
+ case HEIGHT :
+ strncpy(line, "getheight\n", 10);
+ break;
+ case LAT :
+ strncpy(line, "getlat\n", 7);
+ break;
+ case LONGG :
+ strncpy(line, "getlong\n", 8);
+ break;
+ case PITCH :
+ strncpy(line, "getpitch\n", 9);
+ break;
+ case ROLL :
+ strncpy(line, "getroll\n", 8);
+ break;
+ case YAW :
+ strncpy(line, "getyaw\n", 7);
+ break;
+ }
+ int size;
+ if((size = ucart_backendWrite(conn, line)) < 0 ) {
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/groundStation/src/frontend/frontend_getsetpoint.h b/groundStation/src/frontend/frontend_getsetpoint.h
new file mode 100644
index 0000000000000000000000000000000000000000..f8dfdc87b3df057d5fd43714c5b81a52831ce763
--- /dev/null
+++ b/groundStation/src/frontend/frontend_getsetpoint.h
@@ -0,0 +1,25 @@
+#ifndef __FRONTEND_GETSETPOINT_H
+#define __FRONTEND_GETSETPOINT_H
+
+#include "frontend_common.h"
+#include "setpoint_common.h"
+
+/* Get a specified setpoint.
+ *
+ * Example:
+ *
+ * struct frontend_setpoint_data setpoint_data;
+ * if (frontend_getpid(conn, &pid_data)) {
+ * error
+ * } else {
+ * setpoint_data.height, setpoint_data.lat, and setpoint.long are filled
+ * }
+ *
+ * Returns 0 on success, 1 on error
+ */
+int frontend_getsetpoint(
+ struct backend_conn * conn,
+ struct frontend_setpoint_data * setpoint_data,
+ int type);
+
+#endif /* __FRONTEND_GETPID_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_setpid.h b/groundStation/src/frontend/frontend_setpid.h
index bd53cd4535e4aa5834e2841879fdf4dd6bdb014c..b9c6e073d3433a0350ebd9b2d9de8ee55a12f18e 100644
--- a/groundStation/src/frontend/frontend_setpid.h
+++ b/groundStation/src/frontend/frontend_setpid.h
@@ -1,5 +1,5 @@
-#ifndef FRONTEND_SETPID_H
-#define FRONTEND_SETPID_H
+#ifndef __FRONTEND_SETPID_H
+#define __FRONTEND_SETPID_H
#include "pid_common.h"
#include "frontend_common.h"
@@ -17,4 +17,4 @@ int frontend_setpid(
#define SET_ALL (SET_P | SET_I | SET_D)
#endif /* SET_ALL */
-#endif /* FRONTEND_SETPID_H */
\ No newline at end of file
+#endif /* __FRONTEND_SETPID_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_setsetpoint.c b/groundStation/src/frontend/frontend_setsetpoint.c
index f264479210dc801629bd27f14200a11709a38e1b..b9f43caed0ded4d80964dddcc39a12e165f5c54a 100644
--- a/groundStation/src/frontend/frontend_setsetpoint.c
+++ b/groundStation/src/frontend/frontend_setsetpoint.c
@@ -16,26 +16,50 @@ int frontend_setsetpoint(
char buffer[2048];
/* Set the P, I, and D */
- if (mask & SET_X) {
+ if (mask & SET_HEIGHT) {
if (snprintf(buffer, 2048,
- "setsetpointx %f\n",
- setpoint_data->x) >= 2048) {
+ "setheight %f\n",
+ setpoint_data->height) >= 2048) {
errx(0, "Buffer to small to format!");
}
ucart_backendWrite(conn, buffer);
}
- if (mask & SET_Y) {
+ if (mask & SET_LAT) {
if (snprintf(buffer, 2048,
- "setsetpointy %f\n",
- setpoint_data->y) >= 2048) {
+ "setlat %f\n",
+ setpoint_data->lat) >= 2048) {
errx(0, "Buffer to small to format!");
}
ucart_backendWrite(conn, buffer);
}
- if (mask & SET_Z) {
+ if (mask & SET_LONG) {
if (snprintf(buffer, 2048,
- "setsetpointz %f\n",
- setpoint_data->z) >= 2048) {
+ "setlong %f\n",
+ setpoint_data->longg) >= 2048) {
+ errx(0, "Buffer to small to format!");
+ }
+ ucart_backendWrite(conn, buffer);
+ }
+ if (mask & SET_PITCH) {
+ if (snprintf(buffer, 2048,
+ "setpitch %f\n",
+ setpoint_data->pitch) >= 2048) {
+ errx(0, "Buffer to small to format!");
+ }
+ ucart_backendWrite(conn, buffer);
+ }
+ if (mask & SET_ROLL) {
+ if (snprintf(buffer, 2048,
+ "setroll %f\n",
+ setpoint_data->roll) >= 2048) {
+ errx(0, "Buffer to small to format!");
+ }
+ ucart_backendWrite(conn, buffer);
+ }
+ if (mask & SET_YAW) {
+ if (snprintf(buffer, 2048,
+ "setyaw %f\n",
+ setpoint_data->yaw) >= 2048) {
errx(0, "Buffer to small to format!");
}
ucart_backendWrite(conn, buffer);
diff --git a/groundStation/src/frontend/frontend_setsetpoint.h b/groundStation/src/frontend/frontend_setsetpoint.h
index 03806fdfe2bfb492a458475c36ffbb012586ebcd..2607c4d564e14b5c4baae8b9500a74d6b878b922 100644
--- a/groundStation/src/frontend/frontend_setsetpoint.h
+++ b/groundStation/src/frontend/frontend_setsetpoint.h
@@ -1,5 +1,5 @@
-#ifndef FRONTEND_SETSETPOINT_H
-#define FRONTEND_SETSETPOINT_H
+#ifndef __FRONTEND_SETSETPOINT_H
+#define __FRONTEND_SETSETPOINT_H
#include "setpoint_common.h"
#include "frontend_common.h"
@@ -9,12 +9,15 @@ int frontend_setsetpoint(
struct frontend_setpoint_data * setpoint_data,
int mask);
-#define SET_X 0x01
-#define SET_Y 0x02
-#define SET_Z 0x04
+#define SET_LAT 0x01
+#define SET_LONG 0x02
+#define SET_HEIGHT 0x04
+#define SET_PITCH 0x08
+#define SET_ROLL 0x10
+#define SET_YAW 0x20
#ifndef SET_ALL
-#define SET_ALL (SET_X | SET_Y | SET_Z)
+#define SET_ALL (SET_LAT | SET_LONG | SET_HEIGHT | SET_PITCH | SET_ROLL | SET_YAW)
#endif /* SET_ALL */
-#endif /* FRONTEND_SETSETPOINT_H */
\ No newline at end of file
+#endif /* __FRONTEND_SETSETPOINT_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/frontend_tracker.h b/groundStation/src/frontend/frontend_tracker.h
index 5fa82487cafb8650a4f990ef9fed0c4ea4154405..58284ca01dc1b4987b523fc125b60010209af930 100644
--- a/groundStation/src/frontend/frontend_tracker.h
+++ b/groundStation/src/frontend/frontend_tracker.h
@@ -1,5 +1,5 @@
-#ifndef _FRONTEND_TRACKER_H
-#define _FRONTEND_TRACKER_H
+#ifndef __FRONTEND_TRACKER_H
+#define __FRONTEND_TRACKER_H
#include "frontend_common.h"
@@ -24,4 +24,4 @@ struct frontend_tracker_data {
int frontend_track(struct backend_conn * conn,
struct frontend_tracker_data *data);
-#endif
+#endif /* __FRONTEND_TRACKER_H */
\ No newline at end of file
diff --git a/groundStation/src/frontend/pid_common.h b/groundStation/src/frontend/pid_common.h
index c40c4fb42fb19bf7caf22a03effe091fb7621ece..b89e3b1cddc85bb8820520e91ea4fa1858becd3a 100644
--- a/groundStation/src/frontend/pid_common.h
+++ b/groundStation/src/frontend/pid_common.h
@@ -1,5 +1,5 @@
-#ifndef PID_COMMON_H
-#define PID_COMMON_H
+#ifndef __PID_COMMON_H
+#define __PID_COMMON_H
enum pid_controller {
PID_PITCH,
@@ -23,4 +23,4 @@ struct frontend_pid_data {
};
-#endif
+#endif /* __PID_COMMON_H */
diff --git a/groundStation/src/frontend/setpoint_common.h b/groundStation/src/frontend/setpoint_common.h
index 25dc8c1ce8ee6ae76805ba10595c0e0139ea8a00..a661cb1cd6b2a3fe84edbba7fdf2ffac85e9c074 100644
--- a/groundStation/src/frontend/setpoint_common.h
+++ b/groundStation/src/frontend/setpoint_common.h
@@ -1,11 +1,15 @@
-#ifndef SETPOINT_COMMON_H
-#define SETPOINT_COMMON_H
+#ifndef __SETPOINT_COMMON_H
+#define __SETPOINT_COMMON_H
struct frontend_setpoint_data {
- float x;
- float y;
- float z;
+ float height;
+ float lat;
+ /* named with two g's due to long type name */
+ float longg;
+ float pitch;
+ float roll;
+ float yaw;
};
-#endif /* SETPOINT_COMMON_H */
\ No newline at end of file
+#endif /* __SETPOINT_COMMON_H */
\ No newline at end of file
diff --git a/quad/.gitignore b/quad/.gitignore
index b127a1194dfeac45d72904d1b869279d06f9231b..53a35d022ad1dea8f70ea943700a97f57e643399 100644
--- a/quad/.gitignore
+++ b/quad/.gitignore
@@ -1,2 +1,3 @@
zybo_fsbl_bsp/
+zybo_fsbl/
test.log
diff --git a/quad/sw/modular_quad_pid/src/initialize_components.c b/quad/sw/modular_quad_pid/src/initialize_components.c
index b56ac63236006f1c05ec4cf53c2685aeda984caf..c548d26d2151f6923fc91421211a2f938f3e9a4b 100644
--- a/quad/sw/modular_quad_pid/src/initialize_components.c
+++ b/quad/sw/modular_quad_pid/src/initialize_components.c
@@ -28,12 +28,7 @@ int protection_loops(modular_structs_t *structs)
read_rec_all(rc_commands);
// wait until the ground station has connected to the quad and acknowledged that its ready to start
- char buf[255] = {};
- int length = snprintf(buf, sizeof(buf), "The quad is ready to receive VRPN data.\r\n");
- length = length >= sizeof(buf) ? 255 : length;
-
while (!structs->user_input_struct.receivedBeginUpdate) {
- //send_data(BEGINUPDATE_TYPE_ID, 0, buf, length);
process_received(structs);
usleep(10000);
}
diff --git a/quad/zybo_fsbl/.cproject b/quad/zybo_fsbl/.cproject
deleted file mode 100644
index 96b7f268fe3d3f92430281623eebae70a7bd7e0f..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/.cproject
+++ /dev/null
@@ -1,172 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="xilinx.gnu.arm.exe.debug.1095913674">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.1095913674" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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diff --git a/quad/zybo_fsbl/.gitignore b/quad/zybo_fsbl/.gitignore
deleted file mode 100644
index cd9403fc0253d13fe387ddbc73f2e92adf8bd073..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-bootimage/
-Debug/
diff --git a/quad/zybo_fsbl/.project b/quad/zybo_fsbl/.project
deleted file mode 100644
index bc2d382197a84b9721fcff26d44f304f29f1d097..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/.project
+++ /dev/null
@@ -1,26 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>zybo_fsbl</name>
- <comment>zybo_fsbl_bsp - ps7_cortexa9_0</comment>
- <projects>
- <project>zybo_fsbl_bsp</project>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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- <natures>
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- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
-</projectDescription>
diff --git a/quad/zybo_fsbl/src/ddr_init.c b/quad/zybo_fsbl/src/ddr_init.c
deleted file mode 100644
index bf9a059a68a3d536e76e5c8f98e7e6c2219b7a0b..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/ddr_init.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file ddr_init.c
-*
-* Initialize the DDR controller. When PCW is functioning, this would be gone.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 06/19/09 First release
-* 2.00a jz 05/11/11 Changed register to #defines, updated to peep11
-* 3.00a mb 30/05/12 included fsbl.h
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_io.h"
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define DDR_CONFIG_BASE (XPS_DDR_CTRL_BASEADDR + 0x000)
-
-#define DDR_MSTR_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x000)
-
-#define DDR_TWORANKPHY_REG (XPS_DDR_CTRL_BASEADDR + 0x004)
-
-#define DDR_HPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x008)
-#define DDR_LPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x00C)
-#define DDR_W_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x010)
-#define DDR_DRAM_PARAMS_1_REG (XPS_DDR_CTRL_BASEADDR + 0x014)
-#define DDR_DRAM_PARAMS_2_REG (XPS_DDR_CTRL_BASEADDR + 0x018)
-#define DDR_DRAM_PARAMS_3_REG (XPS_DDR_CTRL_BASEADDR + 0x01C)
-#define DDR_DRAM_PARAMS_4_REG (XPS_DDR_CTRL_BASEADDR + 0x020)
-#define DDR_DRAM_PARAMS_5_REG (XPS_DDR_CTRL_BASEADDR + 0x024)
-#define DDR_DRAM_INIT_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x028)
-
-#define DDR_DRAM_MODE_1_REG (XPS_DDR_CTRL_BASEADDR + 0x02C)
-#define DDR_DRAM_MODE_2_REG (XPS_DDR_CTRL_BASEADDR + 0x030)
-#define DDR_DRAM_BURST8_REG (XPS_DDR_CTRL_BASEADDR + 0x034)
-
-#define DDR_DEBUG_REG (XPS_DDR_CTRL_BASEADDR + 0x038)
-
-#define DDR_ADDR_MAP_1_REG (XPS_DDR_CTRL_BASEADDR + 0x03C)
-#define DDR_ADDR_MAP_2_REG (XPS_DDR_CTRL_BASEADDR + 0x040)
-#define DDR_ADDR_MAP_3_REG (XPS_DDR_CTRL_BASEADDR + 0x044)
-
-#define DDR_ODT_RD_WR_REG (XPS_DDR_CTRL_BASEADDR + 0x048)
-#define DDR_PHY_RDC_FIFO_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x04C)
-#define DDR_REG_PHY_RDC_FIFO_CTRL (XPS_DDR_CTRL_BASEADDR + 0x050)
-#define DDR_STATUS_REG (XPS_DDR_CTRL_BASEADDR + 0x054)
-
-#define DDR_DLL_CALIB_REG (XPS_DDR_CTRL_BASEADDR + 0x058)
-#define DDR_ODT_REG (XPS_DDR_CTRL_BASEADDR + 0x05C)
-#define DDR_MISC_1_REG (XPS_DDR_CTRL_BASEADDR + 0x060)
-#define DDR_MISC_2_REG (XPS_DDR_CTRL_BASEADDR + 0x064)
-
-#define DDR_WR_DLL_FORCE (XPS_DDR_CTRL_BASEADDR + 0x068)
-#define DDR_RD_DLL_FORCE0_REG (XPS_DDR_CTRL_BASEADDR + 0x06C)
-#define DDR_RD_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x070)
-
-#define DDR_WR_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x074)
-#define DDR_RD_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x078)
-
-#define DDR_MSTR_DLL_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x07C)
-#define DDR_RD_SLAVE_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x080)
-#define DDR_RD_SLAVE_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x084)
-
-#define DDR_OF_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x088)
-#define DDR_OF_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x08C)
-#define DDR_OF_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x090)
-#define DDR_OF_STATUS3_REG (XPS_DDR_CTRL_BASEADDR + 0x094)
-
-#define DDR_MSTR_DLL_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x098)
-
-#define DDR_Wr_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x09C)
-#define DDR_REFRESH_TIMER01_REG (XPS_DDR_CTRL_BASEADDR + 0x0A0)
-#define DDR_T_ZQ_REG (XPS_DDR_CTRL_BASEADDR + 0x0A4)
-#define DDR_T_ZQ_SHORT_INTERVAL_REG (XPS_DDR_CTRL_BASEADDR + 0x0A8)
-
-#define DDR_STATUS_DATA_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0AC)
-#define DDR_STATUS_DATA_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B0)
-#define DDR_STATUS_DQS_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0B4)
-#define DDR_STATUS_DQS_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B8)
-
-#define DDR_WR_DATA_SLV0_REG (XPS_DDR_CTRL_BASEADDR + 0x17c)
-#define DDR_WR_DATA_SLV1_REG (XPS_DDR_CTRL_BASEADDR + 0x180)
-#define DDR_WR_DATA_SLV2_REG (XPS_DDR_CTRL_BASEADDR + 0x184)
-#define DDR_WR_DATA_SLV3_REG (XPS_DDR_CTRL_BASEADDR + 0x188)
-
-#define DDR_ID_REG (XPS_DDR_CTRL_BASEADDR + 0x200)
-#define DDR_DDR_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x204)
-
-#define DDR_PRIO_WR_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x208)
-#define DDR_PRIO_WR_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x20C)
-#define DDR_PRIO_WR_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x210)
-#define DDR_PRIO_WR_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x214)
-#define DDR_PRIO_RD_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x218)
-#define DDR_PRIO_RD_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x21C)
-#define DDR_PRIO_RD_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x220)
-#define DDR_PRIO_RD_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x224)
-
-#define DDR_PERF_MON_1_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x228)
-#define DDR_PERF_MON_1_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x22C)
-#define DDR_PERF_MON_1_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x230)
-#define DDR_PERF_MON_1_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x234)
-#define DDR_PERF_MON_2_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x238)
-#define DDR_PERF_MON_2_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x23C)
-#define DDR_PERF_MON_2_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x240)
-#define DDR_PERF_MON_2_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x244)
-#define DDR_PERF_MON_3_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x248)
-#define DDR_PERF_MON_3_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x24C)
-#define DDR_PERF_MON_3_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x250)
-#define DDR_PERF_MON_3_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x254)
-#define DDR_TRUSTED_MEM_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x258)
-
-#define DDR_EXCLACC_CFG_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x25C)
-#define DDR_EXCLACC_CFG_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x260)
-#define DDR_EXCLACC_CFG_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x264)
-#define DDR_EXCLACC_CFG_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x268)
-
-/* Trust zone configuration register */
-#define SLCR_LOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x4)
-#define SLCR_UNLOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x8)
-#define TZ_DDR_RAM_REG (XPS_SYS_CTRL_BASEADDR + 0x430)
-
-
-/* Mask defines */
-#define DDR_OUT_RESET_MASK 0x1
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define DDRIn32 Xil_In32
-#define DDROut32 Xil_Out32
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void init_ddr(void);
-
-#define DDRIn32 Xil_In32
-#define DDROut32 Xil_Out32
-
-static int verify = 0;
-
-static void NewDDROut32(u32 Address, u32 Value)
-{
- u32 Data;
-
- if (verify) {
- Data = DDRIn32(Address);
- if (Data != Value) fsbl_printf(DEBUG_INFO,"Verify failed, Address = %08X, \
- Data = %08X, Expected = %08X\n\r", Address, Data, Value);
- } else
- DDROut32(Address, Value);
-}
-
-#undef DDROut32
-#define DDROut32 NewDDROut32
-
-void init_ddr(void)
-{
- u32 RegValue;
-
- RegValue = DDRIn32(DDR_MSTR_CTRL_REG);
-
- /* If DDR is being taking out of reset, then it has been configured
- */
- if (RegValue & DDR_OUT_RESET_MASK)
- verify = 1;
-
- /* Configure DDR */
- DDROut32(DDR_MSTR_CTRL_REG, 0x00000200);
-
- /* direct rip of the DDR init tcl for the PEEP startup */
- DDROut32(DDR_TWORANKPHY_REG, 0x000C1061); /* # 0 */
-
- DDROut32(DDR_LPR_PARAMS_REG, 0x03001001); //;#3
- DDROut32(DDR_W_PARAMS_REG, 0x00014001); //;#4
-
- DDROut32(DDR_DRAM_PARAMS_1_REG, 0x0004e020); //; #5
-
-#ifdef PEEP_CODE
- DDROut32(DDR_DRAM_PARAMS_2_REG, 0x36264ccf); //; #6
-#else
- DDROut32(DDR_DRAM_PARAMS_2_REG, 0x349B48CD); //; #6
-#endif
- DDROut32(DDR_DRAM_PARAMS_3_REG, 0x820158a4); //; #7
-
- DDROut32(DDR_DRAM_PARAMS_4_REG, 0x250882c4); //; #8
-
- DDROut32(DDR_DRAM_INIT_PARAMS_REG, 0x00809004); //; #10
-
- DDROut32(DDR_DRAM_MODE_1_REG, 0x0); //; #11
-
- DDROut32(DDR_DRAM_MODE_2_REG, 0x00040952); //; #12
-
- DDROut32(DDR_DRAM_BURST8_REG, 0x00020022); //; #13
-
-#ifdef PEEP_CODE
- DDROut32(DDR_ADDR_MAP_1_REG, 0xF88); //; #15
-#endif
-
-#ifdef PALLADIUM
- DDROut32(DDR_ADDR_MAP_1_REG, 0x777); //; #15
-#endif
-
- DDROut32(DDR_ADDR_MAP_2_REG, 0xFF000000); //; #16
-
- DDROut32(DDR_ADDR_MAP_3_REG, 0x0FF66666); //; #17
-
- DDROut32(DDR_REG_PHY_RDC_FIFO_CTRL, 0x256); //; #20
-
- DDROut32(DDR_ODT_REG, 0x2223); //; #23
-
- DDROut32(DDR_MISC_2_REG, 0x00020FE0); //; #25
-
- DDROut32(DDR_T_ZQ_REG, 0x10200800); //; #41
-
- DDROut32(DDR_STATUS_DQS_SL_DLL_23_REG, 0x200065); //; #46
-
- DDROut32(DDR_WR_DATA_SLV0_REG, 0x50); //; #95
-
- DDROut32(DDR_WR_DATA_SLV1_REG, 0x50); //; #96
-
- DDROut32(DDR_WR_DATA_SLV2_REG, 0x50); //; #97
-
- DDROut32(DDR_WR_DATA_SLV3_REG, 0x50); //; #98
-
- DDROut32(DDR_ID_REG, 0x0); //; #128
-
- /* Enable ddr controller by taking the controller out of reset */
- DDROut32(DDR_MSTR_CTRL_REG,
- DDRIn32(DDR_MSTR_CTRL_REG) | DDR_OUT_RESET_MASK);
-
-#ifdef PALLADIUM
-
- /* Workaround for early palladium, to be removed for 4.61 */
- DDROut32(SLCR_UNLOCK_REG, 0xDF0D);
-
- DDROut32(TZ_DDR_RAM_REG, 0xffffffff);
-
- DDROut32(SLCR_LOCK_REG, 0x767B);
-
-#endif /* PALLADIUM*/
-}
diff --git a/quad/zybo_fsbl/src/diskio.h b/quad/zybo_fsbl/src/diskio.h
deleted file mode 100644
index 5244efd77904e1023716a9990361208340a461e2..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/diskio.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*-----------------------------------------------------------------------
-/ Low level disk interface modlue include file (C)ChaN, 2009
-/-----------------------------------------------------------------------*/
-
-#ifndef _DISKIO
-#define _DISKIO
-
-#include "integer.h"
-
-
-/* Status of Disk Functions */
-typedef BYTE DSTATUS;
-
-/* Results of Disk Functions */
-typedef enum {
- RES_OK = 0, /* 0: Successful */
- RES_ERROR, /* 1: R/W Error */
- RES_WRPRT, /* 2: Write Protected */
- RES_NOTRDY, /* 3: Not Ready */
- RES_PARERR /* 4: Invalid Parameter */
-} DRESULT;
-
-
-/*---------------------------------------*/
-/* Prototypes for disk control functions */
-
-int assign_drives (int, int);
-DSTATUS disk_initialize (BYTE);
-DSTATUS disk_status (BYTE);
-DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
-DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
-DRESULT disk_ioctl (BYTE, BYTE, void*);
-
-
-
-/* Disk Status Bits (DSTATUS) */
-
-#define STA_NOINIT 0x01 /* Drive not initialized */
-#define STA_NODISK 0x02 /* No medium in the drive */
-#define STA_PROTECT 0x04 /* Write protected */
-
-
-/* Command code for disk_ioctrl fucntion */
-
-/* Generic command (mandatory for FatFs) */
-#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
-#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
-#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
-#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
-
-#endif
diff --git a/quad/zybo_fsbl/src/ff.c b/quad/zybo_fsbl/src/ff.c
deleted file mode 100644
index 35bfa7e50afb44e44833ae218af15355a7210ea7..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/ff.c
+++ /dev/null
@@ -1,3756 +0,0 @@
-/*----------------------------------------------------------------------------/
-/ FatFs - FAT file system module R0.08a (C)ChaN, 2010
-/-----------------------------------------------------------------------------/
-/ FatFs module is a generic FAT file system module for small embedded systems.
-/ This is a free software that opened for education, research and commercial
-/ developments under license policy of following terms.
-/
-/ Copyright (C) 2010, ChaN, all right reserved.
-/
-/ * The FatFs module is a free software and there is NO WARRANTY.
-/ * No restriction on use. You can use, modify and redistribute it for
-/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
-/ * Redistributions of source code must retain the above copyright notice.
-/
-/-----------------------------------------------------------------------------/
-/ Feb 26,'06 R0.00 Prototype.
-/
-/ Apr 29,'06 R0.01 First stable version.
-/
-/ Jun 01,'06 R0.02 Added FAT12 support.
-/ Removed unbuffered mode.
-/ Fixed a problem on small (<32M) partition.
-/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
-/
-/ Sep 22,'06 R0.03 Added f_rename().
-/ Changed option _FS_MINIMUM to _FS_MINIMIZE.
-/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
-/ Fixed f_mkdir() creates incorrect directory on FAT32.
-/
-/ Feb 04,'07 R0.04 Supported multiple drive system.
-/ Changed some interfaces for multiple drive system.
-/ Changed f_mountdrv() to f_mount().
-/ Added f_mkfs().
-/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
-/ Added a capability of extending file size to f_lseek().
-/ Added minimization level 3.
-/ Fixed an endian sensitive code in f_mkfs().
-/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
-/ Added FSInfo support.
-/ Fixed DBCS name can result FR_INVALID_NAME.
-/ Fixed short seek (<= csize) collapses the file object.
-/
-/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs().
-/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
-/ Fixed f_mkdir() on FAT32 creates incorrect directory.
-/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
-/ Fixed off by one error at FAT sub-type determination.
-/ Fixed btr in f_read() can be mistruncated.
-/ Fixed cached sector is not flushed when create and close without write.
-/
-/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets().
-/ Improved performance of f_lseek() on moving to the same or following cluster.
-/
-/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. (_FS_TINY)
-/ Added long file name support.
-/ Added multiple code page support.
-/ Added re-entrancy for multitask operation.
-/ Added auto cluster size selection to f_mkfs().
-/ Added rewind option to f_readdir().
-/ Changed result code of critical errors.
-/ Renamed string functions to avoid name collision.
-/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
-/ Added multiple sector size support.
-/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
-/ Fixed wrong cache control in f_lseek().
-/ Added relative path feature.
-/ Added f_chdir() and f_chdrive().
-/ Added proper case conversion to extended char.
-/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
-/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
-/ Fixed name matching error on the 13 char boundary.
-/ Added a configuration option, _LFN_UNICODE.
-/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
-/
-/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3)
-/ Added file lock feature. (_FS_SHARE)
-/ Added fast seek feature. (_USE_FASTSEEK)
-/ Changed some types on the API, XCHAR->TCHAR.
-/ Changed fname member in the FILINFO structure on Unicode cfg.
-/ String functions support UTF-8 encoding files on Unicode cfg.
-/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
-/ Added sector erase feature. (_USE_ERASE)
-/ Moved file lock semaphore table from fs object to the bss.
-/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
-/ Fixed f_mkfs() creates wrong FAT32 volume.
-/---------------------------------------------------------------------------*/
-#include "xparameters.h"
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-#include "ff.h" /* FatFs configurations and declarations */
-#include "diskio.h" /* Declarations of low level disk I/O functions */
-
-/*--------------------------------------------------------------------------
-
- Module Private Definitions
-
----------------------------------------------------------------------------*/
-
-#if _FATFS != 8255
-#error Wrong include file (ff.h).
-#endif
-
-
-/* Definitions on sector size */
-#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
-#error Wrong sector size.
-#endif
-#if _MAX_SS != 512
-#define SS(fs) ((fs)->ssize) /* Multiple sector size */
-#else
-#define SS(fs) 512U /* Fixed sector size */
-#endif
-
-
-/* Reentrancy related */
-#if _FS_REENTRANT
-#if _USE_LFN == 1
-#error Static LFN work area must not be used in re-entrant configuration.
-#endif
-#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; }
-#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
-#else
-#define ENTER_FF(fs)
-#define LEAVE_FF(fs, res) return res
-#endif
-
-#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
-
-
-/* File shareing feature */
-#if _FS_SHARE
-#if _FS_READONLY
-#error _FS_SHARE must be 0 on read-only cfg.
-#endif
-typedef struct {
- FATFS *fs; /* File ID 1, volume (NULL:blank entry) */
- DWORD clu; /* File ID 2, directory */
- WORD idx; /* File ID 3, directory index */
- WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
-} FILESEM;
-#endif
-
-
-/* Misc definitions */
-#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
-#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);}
-
-
-/* Character code support macros */
-#define IsUpper(c) (((c)>='A')&&((c)<='Z'))
-#define IsLower(c) (((c)>='a')&&((c)<='z'))
-#define IsDigit(c) (((c)>='0')&&((c)<='9'))
-
-#if _DF1S /* Code page is DBCS */
-
-#ifdef _DF2S /* Two 1st byte areas */
-#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
-#else /* One 1st byte area */
-#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
-#endif
-
-#ifdef _DS3S /* Three 2nd byte areas */
-#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
-#else /* Two 2nd byte areas */
-#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
-#endif
-
-#else /* Code page is SBCS */
-
-#define IsDBCS1(c) 0
-#define IsDBCS2(c) 0
-
-#endif /* _DF1S */
-
-
-/* Name status flags */
-#define NS 11 /* Offset of name status byte */
-#define NS_LOSS 0x01 /* Out of 8.3 format */
-#define NS_LFN 0x02 /* Force to create LFN entry */
-#define NS_LAST 0x04 /* Last segment */
-#define NS_BODY 0x08 /* Lower case flag (body) */
-#define NS_EXT 0x10 /* Lower case flag (ext) */
-#define NS_DOT 0x20 /* Dot entry */
-
-
-/* FAT sub-type boundaries */
-/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
-#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */
-#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */
-
-
-/* FatFs refers the members in the FAT structures as byte array instead of
-/ structure member because there are incompatibility of the packing option
-/ between compilers. */
-
-#define BS_jmpBoot 0
-#define BS_OEMName 3
-#define BPB_BytsPerSec 11
-#define BPB_SecPerClus 13
-#define BPB_RsvdSecCnt 14
-#define BPB_NumFATs 16
-#define BPB_RootEntCnt 17
-#define BPB_TotSec16 19
-#define BPB_Media 21
-#define BPB_FATSz16 22
-#define BPB_SecPerTrk 24
-#define BPB_NumHeads 26
-#define BPB_HiddSec 28
-#define BPB_TotSec32 32
-#define BS_DrvNum 36
-#define BS_BootSig 38
-#define BS_VolID 39
-#define BS_VolLab 43
-#define BS_FilSysType 54
-#define BPB_FATSz32 36
-#define BPB_ExtFlags 40
-#define BPB_FSVer 42
-#define BPB_RootClus 44
-#define BPB_FSInfo 48
-#define BPB_BkBootSec 50
-#define BS_DrvNum32 64
-#define BS_BootSig32 66
-#define BS_VolID32 67
-#define BS_VolLab32 71
-#define BS_FilSysType32 82
-#define FSI_LeadSig 0
-#define FSI_StrucSig 484
-#define FSI_Free_Count 488
-#define FSI_Nxt_Free 492
-#define MBR_Table 446
-#define BS_55AA 510
-
-#define DIR_Name 0
-#define DIR_Attr 11
-#define DIR_NTres 12
-#define DIR_CrtTime 14
-#define DIR_CrtDate 16
-#define DIR_FstClusHI 20
-#define DIR_WrtTime 22
-#define DIR_WrtDate 24
-#define DIR_FstClusLO 26
-#define DIR_FileSize 28
-#define LDIR_Ord 0
-#define LDIR_Attr 11
-#define LDIR_Type 12
-#define LDIR_Chksum 13
-#define LDIR_FstClusLO 26
-
-
-
-/*------------------------------------------------------------*/
-/* Work area */
-
-#if _VOLUMES
-static
-FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
-#else
-#error Number of drives must not be 0.
-#endif
-
-static
-WORD Fsid; /* File system mount ID */
-
-#if _FS_RPATH
-static
-BYTE CurrVol; /* Current drive */
-#endif
-
-#if _FS_SHARE
-static
-FILESEM Files[_FS_SHARE]; /* File lock semaphores */
-#endif
-
-#if _USE_LFN == 0 /* No LFN */
-#define DEF_NAMEBUF BYTE sfn[12]
-#define INIT_BUF(dobj) (dobj).fn = sfn
-#define FREE_BUF()
-
-#elif _USE_LFN == 1 /* LFN with static LFN working buffer */
-static WCHAR LfnBuf[_MAX_LFN+1];
-#define DEF_NAMEBUF BYTE sfn[12]
-#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
-#define FREE_BUF()
-
-#elif _USE_LFN == 2 /* LFN with dynamic LFN working buffer on the stack */
-#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
-#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; }
-#define FREE_BUF()
-
-#elif _USE_LFN == 3 /* LFN with dynamic LFN working buffer on the heap */
-#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn
-#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
- if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
- (dobj).lfn = lfn; (dobj).fn = sfn; }
-#define FREE_BUF() ff_memfree(lfn)
-
-#else
-#error Wrong LFN configuration.
-#endif
-
-
-
-
-/*--------------------------------------------------------------------------
-
- Module Private Functions
-
----------------------------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------------------*/
-/* String functions */
-/*-----------------------------------------------------------------------*/
-
-/* Copy memory to memory */
-static
-void mem_cpy (void* dst, const void* src, UINT cnt) {
- BYTE *d = (BYTE*)dst;
- const BYTE *s = (const BYTE*)src;
-
-#if _WORD_ACCESS == 1
- while (cnt >= sizeof(int)) {
- *(int*)d = *(int*)s;
- d += sizeof(int); s += sizeof(int);
- cnt -= sizeof(int);
- }
-#endif
- while (cnt--)
- *d++ = *s++;
-}
-
-/* Fill memory */
-static
-void mem_set (void* dst, int val, UINT cnt) {
- BYTE *d = (BYTE*)dst;
-
- while (cnt--)
- *d++ = (BYTE)val;
-}
-
-/* Compare memory to memory */
-static
-int mem_cmp (const void* dst, const void* src, UINT cnt) {
- const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
- int r = 0;
-
- while (cnt-- && (r = *d++ - *s++) == 0) ;
- return r;
-}
-
-/* Check if chr is contained in the string */
-static
-int chk_chr (const char* str, int chr) {
- while (*str && *str != chr) str++;
- return *str;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Request/Release grant to access the volume */
-/*-----------------------------------------------------------------------*/
-#if _FS_REENTRANT
-
-static
-int lock_fs (
- FATFS *fs /* File system object */
-)
-{
- return ff_req_grant(fs->sobj);
-}
-
-
-static
-void unlock_fs (
- FATFS *fs, /* File system object */
- FRESULT res /* Result code to be returned */
-)
-{
- if (res != FR_NOT_ENABLED &&
- res != FR_INVALID_DRIVE &&
- res != FR_INVALID_OBJECT &&
- res != FR_TIMEOUT) {
- ff_rel_grant(fs->sobj);
- }
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* File shareing control functions */
-/*-----------------------------------------------------------------------*/
-#if _FS_SHARE
-
-static
-FRESULT chk_lock ( /* Check if the file can be accessed */
- DIR* dj, /* Directory object pointing the file to be checked */
- int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
-)
-{
- UINT i, be;
-
- /* Search file semaphore table */
- for (i = be = 0; i < _FS_SHARE; i++) {
- if (Files[i].fs) { /* Existing entry */
- if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */
- Files[i].clu == dj->sclust &&
- Files[i].idx == dj->index) break;
- } else { /* Blank entry */
- be++;
- }
- }
- if (i == _FS_SHARE) /* The file is not opened */
- return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */
-
- /* The file has been opened. Reject any open against writing file and all write mode open */
- return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
-}
-
-
-static
-int enq_lock ( /* Check if an entry is available for a new file */
- FATFS* fs /* File system object */
-)
-{
- UINT i;
-
- for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ;
- return (i == _FS_SHARE) ? 0 : 1;
-}
-
-
-static
-UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */
- DIR* dj, /* Directory object pointing the file to register or increment */
- int acc /* Desired access mode (0:Read, !0:Write) */
-)
-{
- UINT i;
-
-
- for (i = 0; i < _FS_SHARE; i++) { /* Find the file */
- if (Files[i].fs == dj->fs &&
- Files[i].clu == dj->sclust &&
- Files[i].idx == dj->index) break;
- }
-
- if (i == _FS_SHARE) { /* Not opened. Register it as new. */
- for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ;
- if (i == _FS_SHARE) return 0; /* No space to register (int err) */
- Files[i].fs = dj->fs;
- Files[i].clu = dj->sclust;
- Files[i].idx = dj->index;
- Files[i].ctr = 0;
- }
-
- if (acc && Files[i].ctr) return 0; /* Access violation (int err) */
-
- Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
-
- return i + 1;
-}
-
-
-static
-FRESULT dec_lock ( /* Decrement file open counter */
- UINT i /* Semaphore index */
-)
-{
- WORD n;
- FRESULT res;
-
-
- if (--i < _FS_SHARE) {
- n = Files[i].ctr;
- if (n == 0x100) n = 0;
- if (n) n--;
- Files[i].ctr = n;
- if (!n) Files[i].fs = 0;
- res = FR_OK;
- } else {
- res = FR_INT_ERR;
- }
- return res;
-}
-
-
-static
-void clear_lock ( /* Clear lock entries of the volume */
- FATFS *fs
-)
-{
- UINT i;
-
- for (i = 0; i < _FS_SHARE; i++) {
- if (Files[i].fs == fs) Files[i].fs = 0;
- }
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change window offset */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT move_window (
- FATFS *fs, /* File system object */
- DWORD sector /* Sector number to make appearance in the fs->win[] */
-) /* Move to zero only writes back dirty window */
-{
- DWORD wsect;
-
- wsect = fs->winsect;
- if (wsect != sector) { /* Changed current window */
-#if !_FS_READONLY
- if (fs->wflag) { /* Write back dirty window if needed */
- if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
- return FR_DISK_ERR;
- fs->wflag = 0;
- if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */
- BYTE nf;
- for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */
- wsect += fs->fsize;
- disk_write(fs->drv, fs->win, wsect, 1);
- }
- }
- }
-#endif
- if (sector) {
- if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
- return FR_DISK_ERR;
- fs->winsect = sector;
- }
- }
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Clean-up cached data */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */
- FATFS *fs /* File system object */
-)
-{
- FRESULT res;
-
-
- res = move_window(fs, 0);
- if (res == FR_OK) {
- /* Update FSInfo sector if needed */
- if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
- fs->winsect = 0;
- mem_set(fs->win, 0, 512);
- ST_WORD(fs->win+BS_55AA, 0xAA55);
- ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
- ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
- ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
- ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
- disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
- fs->fsi_flag = 0;
- }
- /* Make sure that no pending write process in the physical drive */
- if (disk_ioctl(fs->drv, CTRL_SYNC, (void*)0) != RES_OK)
- res = FR_DISK_ERR;
- }
-
- return res;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get sector# from cluster# */
-/*-----------------------------------------------------------------------*/
-
-
-DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to be converted */
-)
-{
- clst -= 2;
- if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */
- return clst * fs->csize + fs->database;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Read value of a FAT entry */
-/*-----------------------------------------------------------------------*/
-
-
-DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to get the link information */
-)
-{
- UINT wc, bc;
- BYTE *p;
-
-
- if (clst < 2 || clst >= fs->n_fatent) /* Chack range */
- return 1;
-
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = (UINT)clst; bc += bc / 2;
- if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
- wc = fs->win[bc % SS(fs)]; bc++;
- if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
- wc |= fs->win[bc % SS(fs)] << 8;
- return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
-
- case FS_FAT16 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
- p = &fs->win[clst * 2 % SS(fs)];
- return LD_WORD(p);
-
- case FS_FAT32 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
- p = &fs->win[clst * 4 % SS(fs)];
- return LD_DWORD(p) & 0x0FFFFFFF;
- }
-
- return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Change value of a FAT entry */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-
-FRESULT put_fat (
- FATFS *fs, /* File system object */
- DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
- DWORD val /* New value to mark the cluster */
-)
-{
- UINT bc;
- BYTE *p;
- FRESULT res;
-
-
- if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
- res = FR_INT_ERR;
-
- } else {
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = clst; bc += bc / 2;
- res = move_window(fs, fs->fatbase + (bc / SS(fs)));
- if (res != FR_OK) break;
- p = &fs->win[bc % SS(fs)];
- *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
- bc++;
- fs->wflag = 1;
- res = move_window(fs, fs->fatbase + (bc / SS(fs)));
- if (res != FR_OK) break;
- p = &fs->win[bc % SS(fs)];
- *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
- break;
-
- case FS_FAT16 :
- res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
- if (res != FR_OK) break;
- p = &fs->win[clst * 2 % SS(fs)];
- ST_WORD(p, (WORD)val);
- break;
-
- case FS_FAT32 :
- res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
- if (res != FR_OK) break;
- p = &fs->win[clst * 4 % SS(fs)];
- val |= LD_DWORD(p) & 0xF0000000;
- ST_DWORD(p, val);
- break;
-
- default :
- res = FR_INT_ERR;
- }
- fs->wflag = 1;
- }
-
- return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Remove a cluster chain */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT remove_chain (
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to remove a chain from */
-)
-{
- FRESULT res;
- DWORD nxt;
-#if _USE_ERASE
- DWORD scl = clst, ecl = clst, resion[2];
-#endif
-
- if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
- res = FR_INT_ERR;
-
- } else {
- res = FR_OK;
- while (clst < fs->n_fatent) { /* Not a last link? */
- nxt = get_fat(fs, clst); /* Get cluster status */
- if (nxt == 0) break; /* Empty cluster? */
- if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */
- if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */
- res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */
- if (res != FR_OK) break;
- if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */
- fs->free_clust++;
- fs->fsi_flag = 1;
- }
-#if _USE_ERASE
- if (ecl + 1 == nxt) { /* Next cluster is contiguous */
- ecl = nxt;
- } else { /* End of contiguous clusters */
- resion[0] = clust2sect(fs, scl); /* Start sector */
- resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
- disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */
- scl = ecl = nxt;
- }
-#endif
- clst = nxt; /* Next cluster */
- }
- }
-
- return res;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Stretch or Create a cluster chain */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
- FATFS *fs, /* File system object */
- DWORD clst /* Cluster# to stretch. 0 means create a new chain. */
-)
-{
- DWORD cs, ncl, scl;
- FRESULT res;
-
-
- if (clst == 0) { /* Create a new chain */
- scl = fs->last_clust; /* Get suggested start point */
- if (!scl || scl >= fs->n_fatent) scl = 1;
- }
- else { /* Stretch the current chain */
- cs = get_fat(fs, clst); /* Check the cluster status */
- if (cs < 2) return 1; /* It is an invalid cluster */
- if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
- scl = clst;
- }
-
- ncl = scl; /* Start cluster */
- for (;;) {
- ncl++; /* Next cluster */
- if (ncl >= fs->n_fatent) { /* Wrap around */
- ncl = 2;
- if (ncl > scl) return 0; /* No free cluster */
- }
- cs = get_fat(fs, ncl); /* Get the cluster status */
- if (cs == 0) break; /* Found a free cluster */
- if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
- return cs;
- if (ncl == scl) return 0; /* No free cluster */
- }
-
- res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */
- if (res == FR_OK && clst != 0) {
- res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */
- }
- if (res == FR_OK) {
- fs->last_clust = ncl; /* Update FSINFO */
- if (fs->free_clust != 0xFFFFFFFF) {
- fs->free_clust--;
- fs->fsi_flag = 1;
- }
- } else {
- ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
- }
-
- return ncl; /* Return new cluster number or error code */
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Set directory index */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_sdi (
- DIR *dj, /* Pointer to directory object */
- WORD idx /* Directory index number */
-)
-{
- DWORD clst;
- WORD ic;
-
-
- dj->index = idx;
- clst = dj->sclust;
- if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */
- return FR_INT_ERR;
- if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */
- clst = dj->fs->dirbase;
-
- if (clst == 0) { /* Static table (root-dir in FAT12/16) */
- dj->clust = clst;
- if (idx >= dj->fs->n_rootdir) /* Index is out of range */
- return FR_INT_ERR;
- dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */
- }
- else { /* Dynamic table (sub-dirs or root-dir in FAT32) */
- ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */
- while (idx >= ic) { /* Follow cluster chain */
- clst = get_fat(dj->fs, clst); /* Get next cluster */
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
- if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */
- return FR_INT_ERR;
- idx -= ic;
- }
- dj->clust = clst;
- dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */
- }
-
- dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */
-
- return FR_OK; /* Seek succeeded */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Move directory index next */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */
- DIR *dj, /* Pointer to directory object */
- int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
-)
-{
- DWORD clst;
- WORD i;
-
-
- i = dj->index + 1;
- if (!i || !dj->sect) /* Report EOT when index has reached 65535 */
- return FR_NO_FILE;
-
- if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */
- dj->sect++; /* Next sector */
-
- if (dj->clust == 0) { /* Static table */
- if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */
- return FR_NO_FILE;
- }
- else { /* Dynamic table */
- if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */
- clst = get_fat(dj->fs, dj->clust); /* Get next cluster */
- if (clst <= 1) return FR_INT_ERR;
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
- if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */
-#if !_FS_READONLY
- BYTE c;
- if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */
- clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */
- if (clst == 0) return FR_DENIED; /* No free cluster */
- if (clst == 1) return FR_INT_ERR;
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
- /* Clean-up stretched table */
- if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */
- mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */
- dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */
- for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */
- dj->fs->wflag = 1;
- if (move_window(dj->fs, 0)) return FR_DISK_ERR;
- dj->fs->winsect++;
- }
- dj->fs->winsect -= c; /* Rewind window address */
-#else
- return FR_NO_FILE; /* Report EOT */
-#endif
- }
- dj->clust = clst; /* Initialize data for new cluster */
- dj->sect = clust2sect(dj->fs, clst);
- }
- }
- }
-
- dj->index = i;
- dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32;
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-static
-const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */
-
-
-static
-int cmp_lfn ( /* 1:Matched, 0:Not matched */
- WCHAR *lfnbuf, /* Pointer to the LFN to be compared */
- BYTE *dir /* Pointer to the directory entry containing a part of LFN */
-)
-{
- UINT i, s;
- WCHAR wc, uc;
-
-
- i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */
- s = 0; wc = 1;
- do {
- uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
- if (wc) { /* Last char has not been processed */
- wc = ff_wtoupper(uc); /* Convert it to upper case */
- if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */
- return 0; /* Not matched */
- } else {
- if (uc != 0xFFFF) return 0; /* Check filler */
- }
- } while (++s < 13); /* Repeat until all chars in the entry are checked */
-
- if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */
- return 0;
-
- return 1; /* The part of LFN matched */
-}
-
-
-
-static
-int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */
- WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */
- BYTE *dir /* Pointer to the directory entry */
-)
-{
- UINT i, s;
- WCHAR wc, uc;
-
-
- i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
-
- s = 0; wc = 1;
- do {
- uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
- if (wc) { /* Last char has not been processed */
- if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
- lfnbuf[i++] = wc = uc; /* Store it */
- } else {
- if (uc != 0xFFFF) return 0; /* Check filler */
- }
- } while (++s < 13); /* Read all character in the entry */
-
- if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */
- if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
- lfnbuf[i] = 0;
- }
-
- return 1;
-}
-
-
-#if !_FS_READONLY
-static
-void fit_lfn (
- const WCHAR *lfnbuf, /* Pointer to the LFN buffer */
- BYTE *dir, /* Pointer to the directory entry */
- BYTE ord, /* LFN order (1-20) */
- BYTE sum /* SFN sum */
-)
-{
- UINT i, s;
- WCHAR wc;
-
-
- dir[LDIR_Chksum] = sum; /* Set check sum */
- dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
- dir[LDIR_Type] = 0;
- ST_WORD(dir+LDIR_FstClusLO, 0);
-
- i = (ord - 1) * 13; /* Get offset in the LFN buffer */
- s = wc = 0;
- do {
- if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */
- ST_WORD(dir+LfnOfs[s], wc); /* Put it */
- if (!wc) wc = 0xFFFF; /* Padding chars following last char */
- } while (++s < 13);
- if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */
- dir[LDIR_Ord] = ord; /* Set the LFN order */
-}
-
-#endif
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create numbered name */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-void gen_numname (
- BYTE *dst, /* Pointer to generated SFN */
- const BYTE *src, /* Pointer to source SFN to be modified */
- const WCHAR *lfn, /* Pointer to LFN */
- WORD seq /* Sequence number */
-)
-{
- BYTE ns[8], c;
- UINT i, j;
-
-
- mem_cpy(dst, src, 11);
-
- if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */
- do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn);
- }
-
- /* itoa */
- i = 7;
- do {
- c = (seq % 16) + '0';
- if (c > '9') c += 7;
- ns[i--] = c;
- seq /= 16;
- } while (seq);
- ns[i] = '~';
-
- /* Append the number */
- for (j = 0; j < i && dst[j] != ' '; j++) {
- if (IsDBCS1(dst[j])) {
- if (j == i - 1) break;
- j++;
- }
- }
- do {
- dst[j++] = (i < 8) ? ns[i++] : ' ';
- } while (j < 8);
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Calculate sum of an SFN */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-static
-BYTE sum_sfn (
- const BYTE *dir /* Ptr to directory entry */
-)
-{
- BYTE sum = 0;
- UINT n = 11;
-
- do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
- return sum;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Find an object in the directory */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_find (
- DIR *dj /* Pointer to the directory object linked to the file name */
-)
-{
- FRESULT res;
- BYTE c, *dir;
-#if _USE_LFN
- BYTE a, ord, sum;
-#endif
-
- res = dir_sdi(dj, 0); /* Rewind directory object */
- if (res != FR_OK) return res;
-
-#if _USE_LFN
- ord = sum = 0xFF;
-#endif
- do {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- dir = dj->dir; /* Ptr to the directory entry of current index */
- c = dir[DIR_Name];
- if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
-#if _USE_LFN /* LFN configuration */
- a = dir[DIR_Attr] & AM_MASK;
- if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
- ord = 0xFF;
- } else {
- if (a == AM_LFN) { /* An LFN entry is found */
- if (dj->lfn) {
- if (c & 0x40) { /* Is it start of LFN sequence? */
- sum = dir[LDIR_Chksum];
- c &= 0xBF; ord = c; /* LFN start order */
- dj->lfn_idx = dj->index;
- }
- /* Check validity of the LFN entry and compare it with given name */
- ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
- }
- } else { /* An SFN entry is found */
- if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
- ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */
- if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */
- }
- }
-#else /* Non LFN configuration */
- if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
- break;
-#endif
- res = dir_next(dj, 0); /* Next entry */
- } while (res == FR_OK);
-
- return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read an object from the directory */
-/*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1
-static
-FRESULT dir_read (
- DIR *dj /* Pointer to the directory object that pointing the entry to be read */
-)
-{
- FRESULT res;
- BYTE c, *dir;
-#if _USE_LFN
- BYTE a, ord = 0xFF, sum = 0xFF;
-#endif
-
- res = FR_NO_FILE;
- while (dj->sect) {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- dir = dj->dir; /* Ptr to the directory entry of current index */
- c = dir[DIR_Name];
- if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
-#if _USE_LFN /* LFN configuration */
- a = dir[DIR_Attr] & AM_MASK;
- if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
- ord = 0xFF;
- } else {
- if (a == AM_LFN) { /* An LFN entry is found */
- if (c & 0x40) { /* Is it start of LFN sequence? */
- sum = dir[LDIR_Chksum];
- c &= 0xBF; ord = c;
- dj->lfn_idx = dj->index;
- }
- /* Check LFN validity and capture it */
- ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
- } else { /* An SFN entry is found */
- if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */
- dj->lfn_idx = 0xFFFF; /* It has no LFN. */
- break;
- }
- }
-#else /* Non LFN configuration */
- if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */
- break;
-#endif
- res = dir_next(dj, 0); /* Next entry */
- if (res != FR_OK) break;
- }
-
- if (res != FR_OK) dj->sect = 0;
-
- return res;
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Register an object to the directory */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
- DIR *dj /* Target directory with object name to be created */
-)
-{
- FRESULT res;
- BYTE c, *dir;
-#if _USE_LFN /* LFN configuration */
- WORD n, ne, is;
- BYTE sn[12], *fn, sum;
- WCHAR *lfn;
-
-
- fn = dj->fn; lfn = dj->lfn;
- mem_cpy(sn, fn, 12);
-
- if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */
- return FR_INVALID_NAME;
-
- if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
- fn[NS] = 0; dj->lfn = 0; /* Find only SFN */
- for (n = 1; n < 100; n++) {
- gen_numname(fn, sn, lfn, n); /* Generate a numbered name */
- res = dir_find(dj); /* Check if the name collides with existing SFN */
- if (res != FR_OK) break;
- }
- if (n == 100) return FR_DENIED; /* Abort if too many collisions */
- if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
- fn[NS] = sn[NS]; dj->lfn = lfn;
- }
-
- if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */
- for (ne = 0; lfn[ne]; ne++) ;
- ne = (ne + 25) / 13;
- } else { /* Otherwise reserve only an SFN entry. */
- ne = 1;
- }
-
- /* Reserve contiguous entries */
- res = dir_sdi(dj, 0);
- if (res != FR_OK) return res;
- n = is = 0;
- do {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- c = *dj->dir; /* Check the entry status */
- if (c == 0xE5 || c == 0) { /* Is it a blank entry? */
- if (n == 0) is = dj->index; /* First index of the contiguous entry */
- if (++n == ne) break; /* A contiguous entry that required count is found */
- } else {
- n = 0; /* Not a blank entry. Restart to search */
- }
- res = dir_next(dj, 1); /* Next entry with table stretch */
- } while (res == FR_OK);
-
- if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */
- res = dir_sdi(dj, is);
- if (res == FR_OK) {
- sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */
- ne--;
- do { /* Store LFN entries in bottom first */
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
- dj->fs->wflag = 1;
- res = dir_next(dj, 0); /* Next entry */
- } while (res == FR_OK && --ne);
- }
- }
-
-#else /* Non LFN configuration */
- res = dir_sdi(dj, 0);
- if (res == FR_OK) {
- do { /* Find a blank entry for the SFN */
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- c = *dj->dir;
- if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */
- res = dir_next(dj, 1); /* Next entry with table stretch */
- } while (res == FR_OK);
- }
-#endif
-
- if (res == FR_OK) { /* Initialize the SFN entry */
- res = move_window(dj->fs, dj->sect);
- if (res == FR_OK) {
- dir = dj->dir;
- mem_set(dir, 0, 32); /* Clean the entry */
- mem_cpy(dir, dj->fn, 11); /* Put SFN */
-#if _USE_LFN
- dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */
-#endif
- dj->fs->wflag = 1;
- }
- }
-
- return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Remove an object from the directory */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY && !_FS_MINIMIZE
-static
-FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */
- DIR *dj /* Directory object pointing the entry to be removed */
-)
-{
- FRESULT res;
-#if _USE_LFN /* LFN configuration */
- WORD i;
-
- i = dj->index; /* SFN index */
- res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */
- if (res == FR_OK) {
- do {
- res = move_window(dj->fs, dj->sect);
- if (res != FR_OK) break;
- *dj->dir = 0xE5; /* Mark the entry "deleted" */
- dj->fs->wflag = 1;
- if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */
- res = dir_next(dj, 0); /* Next entry */
- } while (res == FR_OK);
- if (res == FR_NO_FILE) res = FR_INT_ERR;
- }
-
-#else /* Non LFN configuration */
- res = dir_sdi(dj, dj->index);
- if (res == FR_OK) {
- res = move_window(dj->fs, dj->sect);
- if (res == FR_OK) {
- *dj->dir = 0xE5; /* Mark the entry "deleted" */
- dj->fs->wflag = 1;
- }
- }
-#endif
-
- return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Pick a segment and create the object name in directory form */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT create_name (
- DIR *dj, /* Pointer to the directory object */
- const TCHAR **path /* Pointer to pointer to the segment in the path string */
-)
-{
-#ifdef _EXCVT
- static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */
-#endif
-
-#if _USE_LFN /* LFN configuration */
- BYTE b, cf;
- WCHAR w, *lfn;
- UINT i, ni, si, di;
- const TCHAR *p;
-
- /* Create LFN in Unicode */
- si = di = 0;
- p = *path;
- lfn = dj->lfn;
- for (;;) {
- w = p[si++]; /* Get a character */
- if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */
- if (di >= _MAX_LFN) /* Reject too long name */
- return FR_INVALID_NAME;
-#if !_LFN_UNICODE
- w &= 0xFF;
- if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
- b = (BYTE)p[si++]; /* Get 2nd byte */
- if (!IsDBCS2(b))
- return FR_INVALID_NAME; /* Reject invalid sequence */
- w = (w << 8) + b; /* Create a DBC */
- }
- w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */
- if (!w) return FR_INVALID_NAME; /* Reject invalid code */
-#endif
- if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
- return FR_INVALID_NAME;
- lfn[di++] = w; /* Store the Unicode char */
- }
- *path = &p[si]; /* Return pointer to the next segment */
- cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
-#if _FS_RPATH
- if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
- (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
- lfn[di] = 0;
- for (i = 0; i < 11; i++)
- dj->fn[i] = (i < di) ? '.' : ' ';
- dj->fn[i] = cf | NS_DOT; /* This is a dot entry */
- return FR_OK;
- }
-#endif
- while (di) { /* Strip trailing spaces and dots */
- w = lfn[di-1];
- if (w != ' ' && w != '.') break;
- di--;
- }
- if (!di) return FR_INVALID_NAME; /* Reject nul string */
-
- lfn[di] = 0; /* LFN is created */
-
- /* Create SFN in directory form */
- mem_set(dj->fn, ' ', 11);
- for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */
- if (si) cf |= NS_LOSS | NS_LFN;
- while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */
-
- b = i = 0; ni = 8;
- for (;;) {
- w = lfn[si++]; /* Get an LFN char */
- if (!w) break; /* Break on end of the LFN */
- if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */
- cf |= NS_LOSS | NS_LFN; continue;
- }
-
- if (i >= ni || si == di) { /* Extension or end of SFN */
- if (ni == 11) { /* Long extension */
- cf |= NS_LOSS | NS_LFN; break;
- }
- if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */
- if (si > di) break; /* No extension */
- si = di; i = 8; ni = 11; /* Enter extension section */
- b <<= 2; continue;
- }
-
- if (w >= 0x80) { /* Non ASCII char */
-#ifdef _EXCVT
- w = ff_convert(w, 0); /* Unicode -> OEM code */
- if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */
-#else
- w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */
-#endif
- cf |= NS_LFN; /* Force create LFN entry */
- }
-
- if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */
- if (i >= ni - 1) {
- cf |= NS_LOSS | NS_LFN; i = ni; continue;
- }
- dj->fn[i++] = (BYTE)(w >> 8);
- } else { /* Single byte char */
- if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */
- w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
- } else {
- if (IsUpper(w)) { /* ASCII large capital */
- b |= 2;
- } else {
- if (IsLower(w)) { /* ASCII small capital */
- b |= 1; w -= 0x20;
- }
- }
- }
- }
- dj->fn[i++] = (BYTE)w;
- }
-
- if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */
-
- if (ni == 8) b <<= 2;
- if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */
- cf |= NS_LFN;
- if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */
- if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */
- if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
- }
-
- dj->fn[NS] = cf; /* SFN is created */
-
- return FR_OK;
-
-
-#else /* Non-LFN configuration */
- BYTE b, c, d, *sfn;
- UINT ni, si, i;
- const char *p;
-
- /* Create file name in directory form */
- sfn = dj->fn;
- mem_set(sfn, ' ', 11);
- si = i = b = 0; ni = 8;
- p = *path;
-#if _FS_RPATH
- if (p[si] == '.') { /* Is this a dot entry? */
- for (;;) {
- c = (BYTE)p[si++];
- if (c != '.' || si >= 3) break;
- sfn[i++] = c;
- }
- if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
- *path = &p[si]; /* Return pointer to the next segment */
- sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
- return FR_OK;
- }
-#endif
- for (;;) {
- c = (BYTE)p[si++];
- if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */
- if (c == '.' || i >= ni) {
- if (ni != 8 || c != '.') return FR_INVALID_NAME;
- i = 8; ni = 11;
- b <<= 2; continue;
- }
- if (c >= 0x80) { /* Extended char? */
- b |= 3; /* Eliminate NT flag */
-#ifdef _EXCVT
- c = excvt[c-0x80]; /* Upper conversion (SBCS) */
-#else
-#if !_DF1S /* ASCII only cfg */
- return FR_INVALID_NAME;
-#endif
-#endif
- }
- if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
- d = (BYTE)p[si++]; /* Get 2nd byte */
- if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */
- return FR_INVALID_NAME;
- sfn[i++] = c;
- sfn[i++] = d;
- } else { /* Single byte code */
- if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */
- return FR_INVALID_NAME;
- if (IsUpper(c)) { /* ASCII large capital? */
- b |= 2;
- } else {
- if (IsLower(c)) { /* ASCII small capital? */
- b |= 1; c -= 0x20;
- }
- }
- sfn[i++] = c;
- }
- }
- *path = &p[si]; /* Return pointer to the next segment */
- c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
-
- if (!i) return FR_INVALID_NAME; /* Reject nul string */
- if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */
-
- if (ni == 8) b <<= 2;
- if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */
- if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */
-
- sfn[NS] = c; /* Store NT flag, File name is created */
-
- return FR_OK;
-#endif
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get file information from directory entry */
-/*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1
-static
-void get_fileinfo ( /* No return code */
- DIR *dj, /* Pointer to the directory object */
- FILINFO *fno /* Pointer to the file information to be filled */
-)
-{
- UINT i;
- BYTE nt, *dir;
- TCHAR *p, c;
-
-
- p = fno->fname;
- if (dj->sect) {
- dir = dj->dir;
- nt = dir[DIR_NTres]; /* NT flag */
- for (i = 0; i < 8; i++) { /* Copy name body */
- c = dir[i];
- if (c == ' ') break;
- if (c == 0x05) c = (TCHAR)0xE5;
- if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
-#if _LFN_UNICODE
- if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
- c = (c << 8) | dir[++i];
- c = ff_convert(c, 1);
- if (!c) c = '?';
-#endif
- *p++ = c;
- }
- if (dir[8] != ' ') { /* Copy name extension */
- *p++ = '.';
- for (i = 8; i < 11; i++) {
- c = dir[i];
- if (c == ' ') break;
- if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
-#if _LFN_UNICODE
- if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
- c = (c << 8) | dir[++i];
- c = ff_convert(c, 1);
- if (!c) c = '?';
-#endif
- *p++ = c;
- }
- }
- fno->fattrib = dir[DIR_Attr]; /* Attribute */
- fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */
- fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */
- fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */
- }
- *p = 0; /* Terminate SFN str by a \0 */
-
-#if _USE_LFN
- if (fno->lfname && fno->lfsize) {
- TCHAR *tp = fno->lfname;
- WCHAR w, *lfn;
-
- i = 0;
- if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
- lfn = dj->lfn;
- while ((w = *lfn++) != 0) { /* Get an LFN char */
-#if !_LFN_UNICODE
- w = ff_convert(w, 0); /* Unicode -> OEM conversion */
- if (!w) { i = 0; break; } /* Could not convert, no LFN */
- if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */
- tp[i++] = (TCHAR)(w >> 8);
-#endif
- if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */
- tp[i++] = (TCHAR)w;
- }
- }
- tp[i] = 0; /* Terminate the LFN str by a \0 */
- }
-#endif
-}
-#endif /* _FS_MINIMIZE <= 1 */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Follow a file path */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
- DIR *dj, /* Directory object to return last directory and found object */
- const TCHAR *path /* Full-path string to find a file or directory */
-)
-{
- FRESULT res;
- BYTE *dir, ns;
-
-
-#if _FS_RPATH
- if (*path == '/' || *path == '\\') { /* There is a heading separator */
- path++; dj->sclust = 0; /* Strip it and start from the root dir */
- } else { /* No heading separator */
- dj->sclust = dj->fs->cdir; /* Start from the current dir */
- }
-#else
- if (*path == '/' || *path == '\\') /* Strip heading separator if exist */
- path++;
- dj->sclust = 0; /* Start from the root dir */
-#endif
-
- if ((UINT)*path < ' ') { /* Nul path means the start directory itself */
- res = dir_sdi(dj, 0);
- dj->dir = 0;
-
- } else { /* Follow path */
- for (;;) {
- res = create_name(dj, &path); /* Get a segment */
- if (res != FR_OK) break;
- res = dir_find(dj); /* Find it */
- ns = *(dj->fn+NS);
- if (res != FR_OK) { /* Failed to find the object */
- if (res != FR_NO_FILE) break; /* Abort if any hard error occured */
- /* Object not found */
- if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */
- dj->sclust = 0; dj->dir = 0; /* It is the root dir */
- res = FR_OK;
- if (!(ns & NS_LAST)) continue;
- } else { /* Could not find the object */
- if (!(ns & NS_LAST)) res = FR_NO_PATH;
- }
- break;
- }
- if (ns & NS_LAST) break; /* Last segment match. Function completed. */
- dir = dj->dir; /* There is next segment. Follow the sub directory */
- if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
- res = FR_NO_PATH; break;
- }
- dj->sclust = LD_CLUST(dir);
- }
- }
-
- return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Load boot record and check if it is an FAT boot record */
-/*-----------------------------------------------------------------------*/
-
-static
-BYTE check_fs ( /* 0:The FAT BR, 1:Valid BR but not an FAT, 2:Not a BR, 3:Disk error */
- FATFS *fs, /* File system object */
- DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */
-)
-{
- if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) { /* Load boot record */
- return 3;
- }
-
- if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) { /* Check record signature (always placed at offset 510 even if the sector size is >512) */
- return 2;
- }
-
- if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */
- return 0;
- if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
- return 0;
-
- return 1;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file system object is valid or not */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */
- const TCHAR **path, /* Pointer to pointer to the path name (drive number) */
- FATFS **rfs, /* Pointer to pointer to the found file system object */
- BYTE chk_wp /* !=0: Check media write protection for write access */
-)
-{
- BYTE fmt, b, *tbl;
- UINT vol;
- DSTATUS stat;
- DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
- WORD nrsv;
- const TCHAR *p = *path;
- FATFS *fs;
-
- /* Get logical drive number from the path name */
- vol = p[0] - '0'; /* Is there a drive number? */
- if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */
- p += 2; *path = p; /* Return pointer to the path name */
- } else { /* No drive number is given */
-#if _FS_RPATH
- vol = CurrVol; /* Use current drive */
-#else
- vol = 0; /* Use drive 0 */
-#endif
- }
-
- /* Check if the logical drive is valid or not */
- if (vol >= _VOLUMES) /* Is the drive number valid? */
- return FR_INVALID_DRIVE;
- *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */
- if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */
-
- ENTER_FF(fs); /* Lock file system */
-
- if (fs->fs_type) { /* If the logical drive has been mounted */
- stat = disk_status(fs->drv);
- if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */
-#if !_FS_READONLY
- if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */
- return FR_WRITE_PROTECTED;
-#endif
- return FR_OK; /* The file system object is valid */
- }
- }
-
- /* The logical drive must be mounted. */
- /* Following code attempts to mount a volume. (analyze BPB and initialize the fs object) */
-
- fs->fs_type = 0; /* Clear the file system object */
- fs->drv = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */
- stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */
- if (stat & STA_NOINIT) /* Check if the initialization succeeded */
- return FR_NOT_READY; /* Failed to initialize due to no media or hard error */
-#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */
- if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
- return FR_DISK_ERR;
-#endif
-#if !_FS_READONLY
- if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */
- return FR_WRITE_PROTECTED;
-#endif
- /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */
- fmt = check_fs(fs, bsect = 0); /* Check sector 0 if it is a VBR */
- if (fmt == 1) { /* Not an FAT-VBR, the disk may be partitioned */
- /* Check the partition listed in top of the partition table */
- tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */
- if (tbl[4]) { /* Is the partition existing? */
- bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */
- fmt = check_fs(fs, bsect); /* Check the partition */
- }
- }
- if (fmt == 3) return FR_DISK_ERR;
- if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */
-
- /* Following code initializes the file system object */
-
- if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) { /* (BPB_BytsPerSec must be equal to the physical sector size) */
-
- return FR_NO_FILESYSTEM;
- }
-
- fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */
- if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
- fs->fsize = fasize;
-
- fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */
- if (b != 1 && b != 2) {
- return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
- }
- fasize *= b; /* Number of sectors for FAT area */
-
- fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */
- if (!b || (b & (b - 1))) {
- return FR_NO_FILESYSTEM; /* (Must be power of 2) */
- }
-
- fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */
- if (fs->n_rootdir % (SS(fs) / 32)) {
- return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */
- }
-
- tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */
- if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
-
- nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */
- if (!nrsv) {
- return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */
- }
-
- /* Determine the FAT sub type */
- sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / 32); /* RSV+FAT+DIR */
- if (tsect < sysect) {
- return FR_NO_FILESYSTEM; /* (Invalid volume size) */
- }
- nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
- if (!nclst) {
- return FR_NO_FILESYSTEM; /* (Invalid volume size) */
- }
- fmt = FS_FAT12;
- if (nclst >= MIN_FAT16) fmt = FS_FAT16;
- if (nclst >= MIN_FAT32) fmt = FS_FAT32;
-
- /* Boundaries and Limits */
- fs->n_fatent = nclst + 2; /* Number of FAT entries */
- fs->database = bsect + sysect; /* Data start sector */
- fs->fatbase = bsect + nrsv; /* FAT start sector */
- if (fmt == FS_FAT32) {
- if (fs->n_rootdir) {
- return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
- }
- fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */
- szbfat = fs->n_fatent * 4; /* (Required FAT size) */
- } else {
- if (!fs->n_rootdir) {
- return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
- }
- fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
- szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */
- fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
- }
- if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) { /* (FAT size must not be less than FAT sectors */
- return FR_NO_FILESYSTEM;
- }
-
-#if !_FS_READONLY
- /* Initialize cluster allocation information */
- fs->free_clust = 0xFFFFFFFF;
- fs->last_clust = 0;
-
- /* Get fsinfo if available */
- if (fmt == FS_FAT32) {
- fs->fsi_flag = 0;
- fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
- if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
- LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
- LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
- LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
- fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
- fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
- }
- }
-#endif
- fs->fs_type = fmt; /* FAT sub-type */
- fs->id = ++Fsid; /* File system mount ID */
- fs->winsect = 0; /* Invalidate sector cache */
- fs->wflag = 0;
-#if _FS_RPATH
- fs->cdir = 0; /* Current directory (root dir) */
-#endif
-#if _FS_SHARE /* Clear file lock semaphores */
- clear_lock(fs);
-#endif
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file/dir object is valid or not */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */
- FATFS *fs, /* Pointer to the file system object */
- WORD id /* Member id of the target object to be checked */
-)
-{
- if (!fs || !fs->fs_type || fs->id != id)
- return FR_INVALID_OBJECT;
-
- ENTER_FF(fs); /* Lock file system */
-
- if (disk_status(fs->drv) & STA_NOINIT)
- return FR_NOT_READY;
-
- return FR_OK;
-}
-
-
-
-
-/*--------------------------------------------------------------------------
-
- Public Functions
-
---------------------------------------------------------------------------*/
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Mount/Unmount a Logical Drive */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mount (
- BYTE vol, /* Logical drive number to be mounted/unmounted */
- FATFS *fs /* Pointer to new file system object (NULL for unmount)*/
-)
-{
- FATFS *rfs;
-
-
- if (vol >= _VOLUMES) /* Check if the drive number is valid */
- return FR_INVALID_DRIVE;
- rfs = FatFs[vol]; /* Get current fs object */
-
- if (rfs) {
-#if _FS_SHARE
- clear_lock(rfs);
-#endif
-#if _FS_REENTRANT /* Discard sync object of the current volume */
- if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
-#endif
- rfs->fs_type = 0; /* Clear old fs object */
- }
-
- if (fs) {
- fs->fs_type = 0; /* Clear new fs object */
-#if _FS_REENTRANT /* Create sync object for the new volume */
- if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
-#endif
- }
- FatFs[vol] = fs; /* Register new fs object */
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Open or Create a File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_open (
- FIL *fp, /* Pointer to the blank file object */
- const TCHAR *path, /* Pointer to the file name */
- BYTE mode /* Access mode and file open mode flags */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- fp->fs = 0; /* Clear file object */
-
-#if !_FS_READONLY
- mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
- res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
-#else
- mode &= FA_READ;
- res = chk_mounted(&path, &dj.fs, 0);
-#endif
- INIT_BUF(dj);
- if (res == FR_OK)
- res = follow_path(&dj, path); /* Follow the file path */
- dir = dj.dir;
-
-#if !_FS_READONLY /* R/W configuration */
- if (res == FR_OK) {
- if (!dir) /* Current dir itself */
- res = FR_INVALID_NAME;
-#if _FS_SHARE
- else
- res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
-#endif
- }
- /* Create or Open a file */
- if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
- DWORD dw, cl;
-
- if (res != FR_OK) { /* No file, create new */
- if (res == FR_NO_FILE) /* There is no file to open, create a new entry */
-#if _FS_SHARE
- res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
-#else
- res = dir_register(&dj);
-#endif
- mode |= FA_CREATE_ALWAYS; /* File is created */
- dir = dj.dir; /* New entry */
- }
- else { /* Any object is already existing */
- if (mode & FA_CREATE_NEW) { /* Cannot create new */
- res = FR_EXIST;
- } else {
- if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) /* Cannot overwrite it (R/O or DIR) */
- res = FR_DENIED;
- }
- }
- if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
- dw = get_fattime(); /* Created time */
- ST_DWORD(dir+DIR_CrtTime, dw);
- dir[DIR_Attr] = 0; /* Reset attribute */
- ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */
- cl = LD_CLUST(dir); /* Get start cluster */
- ST_CLUST(dir, 0); /* cluster = 0 */
- dj.fs->wflag = 1;
- if (cl) { /* Remove the cluster chain if exist */
- dw = dj.fs->winsect;
- res = remove_chain(dj.fs, cl);
- if (res == FR_OK) {
- dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */
- res = move_window(dj.fs, dw);
- }
- }
- }
- }
- else { /* Open an existing file */
- if (res == FR_OK) { /* Follow succeeded */
- if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */
- res = FR_NO_FILE;
- } else {
- if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
- res = FR_DENIED;
- }
- }
- }
- if (res == FR_OK) {
- if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */
- mode |= FA__WRITTEN;
- fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */
- fp->dir_ptr = dir;
-#if _FS_SHARE
- fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
- if (!fp->lockid) res = FR_INT_ERR;
-#endif
- }
-
-#else /* R/O configuration */
- if (res == FR_OK) { /* Follow succeeded */
- if (!dir) { /* Current dir itself */
- res = FR_INVALID_NAME;
- } else {
- if (dir[DIR_Attr] & AM_DIR) /* It is a directory */
- res = FR_NO_FILE;
- }
- }
-#endif
- FREE_BUF();
-
- if (res == FR_OK) {
- fp->flag = mode; /* File access mode */
- fp->org_clust = LD_CLUST(dir); /* File start cluster */
- fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */
- fp->fptr = 0; /* File pointer */
- fp->dsect = 0;
-#if _USE_FASTSEEK
- fp->cltbl = 0; /* No cluster link map table */
-#endif
- fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_read (
- FIL *fp, /* Pointer to the file object */
- void *buff, /* Pointer to data buffer */
- UINT btr, /* Number of bytes to read */
- UINT *br /* Pointer to number of bytes read */
-)
-{
- FRESULT res;
- DWORD clst, sect, remain;
- UINT rcnt, cc;
- BYTE csect, *rbuff = (BYTE *)buff;
-
- *br = 0; /* Initialize byte counter */
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check abort flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
- if (!(fp->flag & FA_READ)) /* Check access mode */
- LEAVE_FF(fp->fs, FR_DENIED);
- remain = fp->fsize - fp->fptr;
- if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
-
- for ( ; btr; /* Repeat until all data transferred */
- rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
- if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
- csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
- if (!csect) { /* On the cluster boundary? */
- clst = (fp->fptr == 0) ? /* On the top of the file? */
- fp->org_clust : get_fat(fp->fs, fp->curr_clust);
- if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->curr_clust = clst; /* Update current cluster */
- }
- sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */
- if (!sect) ABORT(fp->fs, FR_INT_ERR);
- sect += csect;
- cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */
- if (cc) { /* Read maximum contiguous sectors directly */
- if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
- cc = fp->fs->csize - csect;
- if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
-#if _FS_TINY
- if (fp->fs->wflag && fp->fs->winsect - sect < cc)
- mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
-#else
- if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
- mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
-#endif
-#endif
- rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
- continue;
- }
-#if !_FS_TINY
-#if !_FS_READONLY
- if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- if (fp->dsect != sect) { /* Fill sector buffer with file data */
- if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- }
-#endif
- fp->dsect = sect;
- }
- rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */
- if (rcnt > btr) rcnt = btr;
-#if _FS_TINY
- if (move_window(fp->fs, fp->dsect)) /* Move sector window */
- ABORT(fp->fs, FR_DISK_ERR);
- mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
-#else
- mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
-#endif
- }
-
- LEAVE_FF(fp->fs, FR_OK);
-}
-
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Write File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_write (
- FIL *fp, /* Pointer to the file object */
- const void *buff, /* Pointer to the data to be written */
- UINT btw, /* Number of bytes to write */
- UINT *bw /* Pointer to number of bytes written */
-)
-{
- FRESULT res;
- DWORD clst, sect;
- UINT wcnt, cc;
- const BYTE *wbuff = buff;
- BYTE csect;
-
-
- *bw = 0; /* Initialize byte counter */
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check abort flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
- if (!(fp->flag & FA_WRITE)) /* Check access mode */
- LEAVE_FF(fp->fs, FR_DENIED);
- if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */
-
- for ( ; btw; /* Repeat until all data transferred */
- wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
- if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
- csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
- if (!csect) { /* On the cluster boundary? */
- if (fp->fptr == 0) { /* On the top of the file? */
- clst = fp->org_clust; /* Follow from the origin */
- if (clst == 0) /* When there is no cluster chain, */
- fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */
- } else { /* Middle or end of the file */
- clst = create_chain(fp->fs, fp->curr_clust); /* Follow or stretch cluster chain */
- }
- if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
- if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->curr_clust = clst; /* Update current cluster */
- }
-#if _FS_TINY
- if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */
- ABORT(fp->fs, FR_DISK_ERR);
-#else
- if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */
- if (!sect) ABORT(fp->fs, FR_INT_ERR);
- sect += csect;
- cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */
- if (cc) { /* Write maximum contiguous sectors directly */
- if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
- cc = fp->fs->csize - csect;
- if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#if _FS_TINY
- if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */
- mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
- fp->fs->wflag = 0;
- }
-#else
- if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */
- mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
- continue;
- }
-#if _FS_TINY
- if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */
- if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR);
- fp->fs->winsect = sect;
- }
-#else
- if (fp->dsect != sect) { /* Fill sector buffer with file data */
- if (fp->fptr < fp->fsize &&
- disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- }
-#endif
- fp->dsect = sect;
- }
- wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
- if (wcnt > btw) wcnt = btw;
-#if _FS_TINY
- if (move_window(fp->fs, fp->dsect)) /* Move sector window */
- ABORT(fp->fs, FR_DISK_ERR);
- mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
- fp->fs->wflag = 1;
-#else
- mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
- fp->flag |= FA__DIRTY;
-#endif
- }
-
- if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */
- fp->flag |= FA__WRITTEN; /* Set file change flag */
-
- LEAVE_FF(fp->fs, FR_OK);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Synchronize the File Object */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_sync (
- FIL *fp /* Pointer to the file object */
-)
-{
- FRESULT res;
- DWORD tim;
- BYTE *dir;
-
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res == FR_OK) {
- if (fp->flag & FA__WRITTEN) { /* Has the file been written? */
-#if !_FS_TINY /* Write-back dirty buffer */
- if (fp->flag & FA__DIRTY) {
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- LEAVE_FF(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- /* Update the directory entry */
- res = move_window(fp->fs, fp->dir_sect);
- if (res == FR_OK) {
- dir = fp->dir_ptr;
- dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
- ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */
- ST_CLUST(dir, fp->org_clust); /* Update start cluster */
- tim = get_fattime(); /* Update updated time */
- ST_DWORD(dir+DIR_WrtTime, tim);
- fp->flag &= ~FA__WRITTEN;
- fp->fs->wflag = 1;
- res = sync(fp->fs);
- }
- }
- }
-
- LEAVE_FF(fp->fs, res);
-}
-
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Close File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_close (
- FIL *fp /* Pointer to the file object to be closed */
-)
-{
- FRESULT res;
-
-#if _FS_READONLY
- FATFS *fs = fp->fs;
- res = validate(fs, fp->id);
- if (res == FR_OK) fp->fs = 0; /* Discard file object */
- LEAVE_FF(fs, res);
-
-#else
- res = f_sync(fp); /* Flush cached data */
-#if _FS_SHARE
- if (res == FR_OK) { /* Decrement open counter */
-#if _FS_REENTRANT
- res = validate(fp->fs, fp->id);
- if (res == FR_OK) {
- res = dec_lock(fp->lockid);
- unlock_fs(fp->fs, FR_OK);
- }
-#else
- res = dec_lock(fp->lockid);
-#endif
- }
-#endif
- if (res == FR_OK) fp->fs = 0; /* Discard file object */
- return res;
-#endif
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Current Drive/Directory Handlings */
-/*-----------------------------------------------------------------------*/
-
-#if _FS_RPATH >= 1
-
-FRESULT f_chdrive (
- BYTE drv /* Drive number */
-)
-{
- if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
-
- CurrVol = drv;
-
- return FR_OK;
-}
-
-
-
-FRESULT f_chdir (
- const TCHAR *path /* Pointer to the directory path */
-)
-{
- FRESULT res;
- DIR dj;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 0);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the path */
- FREE_BUF();
- if (res == FR_OK) { /* Follow completed */
- if (!dj.dir) {
- dj.fs->cdir = dj.sclust; /* Start directory itself */
- } else {
- if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */
- dj.fs->cdir = LD_CLUST(dj.dir);
- else
- res = FR_NO_PATH; /* Reached but a file */
- }
- }
- if (res == FR_NO_FILE) res = FR_NO_PATH;
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-#if _FS_RPATH >= 2
-FRESULT f_getcwd (
- TCHAR *path, /* Pointer to the directory path */
- UINT sz_path /* Size of path */
-)
-{
- FRESULT res;
- DIR dj;
- UINT i, n;
- DWORD ccl;
- TCHAR *tp;
- FILINFO fno;
- DEF_NAMEBUF;
-
-
- *path = 0;
- res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */
- if (res == FR_OK) {
- INIT_BUF(dj);
- i = sz_path; /* Bottom of buffer (dir stack base) */
- dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */
- while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */
- res = dir_sdi(&dj, 1); /* Get parent dir */
- if (res != FR_OK) break;
- res = dir_read(&dj);
- if (res != FR_OK) break;
- dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */
- res = dir_sdi(&dj, 0);
- if (res != FR_OK) break;
- do { /* Find the entry links to the child dir */
- res = dir_read(&dj);
- if (res != FR_OK) break;
- if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */
- res = dir_next(&dj, 0);
- } while (res == FR_OK);
- if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
- if (res != FR_OK) break;
-#if _USE_LFN
- fno.lfname = path;
- fno.lfsize = i;
-#endif
- get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */
- tp = fno.fname;
- if (_USE_LFN && *path) tp = path;
- for (n = 0; tp[n]; n++) ;
- if (i < n + 3) {
- res = FR_NOT_ENOUGH_CORE; break;
- }
- while (n) path[--i] = tp[--n];
- path[--i] = '/';
- }
- tp = path;
- if (res == FR_OK) {
- *tp++ = '0' + CurrVol; /* Put drive number */
- *tp++ = ':';
- if (i == sz_path) { /* Root-dir */
- *tp++ = '/';
- } else { /* Sub-dir */
- do /* Add stacked path str */
- *tp++ = path[i++];
- while (i < sz_path);
- }
- }
- *tp = 0;
- FREE_BUF();
- }
-
- LEAVE_FF(dj.fs, res);
-}
-#endif /* _FS_RPATH >= 2 */
-#endif /* _FS_RPATH >= 1 */
-
-
-
-#if _FS_MINIMIZE <= 2
-/*-----------------------------------------------------------------------*/
-/* Seek File R/W Pointer */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_lseek (
- FIL *fp, /* Pointer to the file object */
- DWORD ofs /* File pointer from top of file */
-)
-{
- FRESULT res;
-
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check abort flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
-
-#if _USE_FASTSEEK
- if (fp->cltbl) { /* Fast seek */
- DWORD cl, pcl, ncl, tcl, dsc, tlen, *tbl = fp->cltbl;
- BYTE csc;
-
- tlen = *tbl++;
- if (ofs == CREATE_LINKMAP) { /* Create link map table */
- cl = fp->org_clust;
- if (cl) {
- do {
- if (tlen < 4) { /* Not enough table items */
- res = FR_NOT_ENOUGH_CORE; break;
- }
- tcl = cl; ncl = 0;
- do { /* Get a fragment and store the top and length */
- pcl = cl; ncl++;
- cl = get_fat(fp->fs, cl);
- if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
- if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- } while (cl == pcl + 1);
- *tbl++ = ncl; *tbl++ = tcl;
- tlen -= 2;
- } while (cl < fp->fs->n_fatent);
- }
- *tbl = 0; /* Terminate table */
-
- } else { /* Fast seek */
- if (ofs > fp->fsize) /* Clip offset at the file size */
- ofs = fp->fsize;
- fp->fptr = ofs; /* Set file pointer */
- if (ofs) {
- dsc = (ofs - 1) / SS(fp->fs);
- cl = dsc / fp->fs->csize;
- for (;;) {
- ncl = *tbl++;
- if (!ncl) ABORT(fp->fs, FR_INT_ERR);
- if (cl < ncl) break;
- cl -= ncl; tbl++;
- }
- fp->curr_clust = cl + *tbl;
- csc = (BYTE)(dsc & (fp->fs->csize - 1));
- dsc = clust2sect(fp->fs, fp->curr_clust);
- if (!dsc) ABORT(fp->fs, FR_INT_ERR);
- dsc += csc;
- if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {
-#if !_FS_TINY
-#if !_FS_READONLY
- if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#endif
- fp->dsect = dsc;
- }
- }
- }
- } else
-#endif
-
- /* Normal Seek */
- {
- DWORD clst, bcs, nsect, ifptr;
-
- if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */
-#if !_FS_READONLY
- && !(fp->flag & FA_WRITE)
-#endif
- ) ofs = fp->fsize;
-
- ifptr = fp->fptr;
- fp->fptr = nsect = 0;
- if (ofs) {
- bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */
- if (ifptr > 0 &&
- (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
- fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */
- ofs -= fp->fptr;
- clst = fp->curr_clust;
- } else { /* When seek to back cluster, */
- clst = fp->org_clust; /* start from the first cluster */
-#if !_FS_READONLY
- if (clst == 0) { /* If no cluster chain, create a new chain */
- clst = create_chain(fp->fs, 0);
- if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->org_clust = clst;
- }
-#endif
- fp->curr_clust = clst;
- }
- if (clst != 0) {
- while (ofs > bcs) { /* Cluster following loop */
-#if !_FS_READONLY
- if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
- clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */
- if (clst == 0) { /* When disk gets full, clip file size */
- ofs = bcs; break;
- }
- } else
-#endif
- clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
- fp->curr_clust = clst;
- fp->fptr += bcs;
- ofs -= bcs;
- }
- fp->fptr += ofs;
- if (ofs % SS(fp->fs)) {
- nsect = clust2sect(fp->fs, clst); /* Current sector */
- if (!nsect) ABORT(fp->fs, FR_INT_ERR);
- nsect += ofs / SS(fp->fs);
- }
- }
- }
- if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {
-#if !_FS_TINY
-#if !_FS_READONLY
- if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
- fp->flag &= ~FA__DIRTY;
- }
-#endif
- if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK)
- ABORT(fp->fs, FR_DISK_ERR);
-#endif
- fp->dsect = nsect;
- }
-#if !_FS_READONLY
- if (fp->fptr > fp->fsize) { /* Set change flag if the file size is extended */
- fp->fsize = fp->fptr;
- fp->flag |= FA__WRITTEN;
- }
-#endif
- }
-
- LEAVE_FF(fp->fs, res);
-}
-
-
-
-#if _FS_MINIMIZE <= 1
-/*-----------------------------------------------------------------------*/
-/* Create a Directroy Object */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_opendir (
- DIR *dj, /* Pointer to directory object to create */
- const TCHAR *path /* Pointer to the directory path */
-)
-{
- FRESULT res;
- DEF_NAMEBUF;
-
- res = chk_mounted(&path, &dj->fs, 0);
- if (res == FR_OK) {
- INIT_BUF(*dj);
- res = follow_path(dj, path); /* Follow the path to the directory */
- FREE_BUF();
- if (res == FR_OK) { /* Follow completed */
- if (dj->dir) { /* It is not the root dir */
- if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */
- dj->sclust = LD_CLUST(dj->dir);
- } else { /* The object is not a directory */
- res = FR_NO_PATH;
- }
- }
- if (res == FR_OK) {
- dj->id = dj->fs->id;
- res = dir_sdi(dj, 0); /* Rewind dir */
- }
- }
- if (res == FR_NO_FILE) res = FR_NO_PATH;
- }
-
- LEAVE_FF(dj->fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Directory Entry in Sequense */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_readdir (
- DIR *dj, /* Pointer to the open directory object */
- FILINFO *fno /* Pointer to file information to return */
-)
-{
- FRESULT res;
- DEF_NAMEBUF;
-
-
- res = validate(dj->fs, dj->id); /* Check validity of the object */
- if (res == FR_OK) {
- if (!fno) {
- res = dir_sdi(dj, 0); /* Rewind the directory object */
- } else {
- INIT_BUF(*dj);
- res = dir_read(dj); /* Read an directory item */
- if (res == FR_NO_FILE) { /* Reached end of dir */
- dj->sect = 0;
- res = FR_OK;
- }
- if (res == FR_OK) { /* A valid entry is found */
- get_fileinfo(dj, fno); /* Get the object information */
- res = dir_next(dj, 0); /* Increment index for next */
- if (res == FR_NO_FILE) {
- dj->sect = 0;
- res = FR_OK;
- }
- }
- FREE_BUF();
- }
- }
-
- LEAVE_FF(dj->fs, res);
-}
-
-
-
-#if _FS_MINIMIZE == 0
-/*-----------------------------------------------------------------------*/
-/* Get File Status */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_stat (
- const TCHAR *path, /* Pointer to the file path */
- FILINFO *fno /* Pointer to file information to return */
-)
-{
- FRESULT res;
- DIR dj;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 0);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK) { /* Follow completed */
- if (dj.dir) /* Found an object */
- get_fileinfo(&dj, fno);
- else /* It is root dir */
- res = FR_INVALID_NAME;
- }
- FREE_BUF();
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Get Number of Free Clusters */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_getfree (
- const TCHAR *path, /* Pointer to the logical drive number (root dir) */
- DWORD *nclst, /* Pointer to the variable to return number of free clusters */
- FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */
-)
-{
- FRESULT res;
- DWORD n, clst, sect, stat;
- UINT i;
- BYTE fat, *p;
-
-
- /* Get drive number */
- res = chk_mounted(&path, fatfs, 0);
- if (res == FR_OK) {
- /* If free_clust is valid, return it without full cluster scan */
- if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) {
- *nclst = (*fatfs)->free_clust;
- } else {
- /* Get number of free clusters */
- fat = (*fatfs)->fs_type;
- n = 0;
- if (fat == FS_FAT12) {
- clst = 2;
- do {
- stat = get_fat(*fatfs, clst);
- if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
- if (stat == 1) { res = FR_INT_ERR; break; }
- if (stat == 0) n++;
- } while (++clst < (*fatfs)->n_fatent);
- } else {
- clst = (*fatfs)->n_fatent;
- sect = (*fatfs)->fatbase;
- i = 0; p = 0;
- do {
- if (!i) {
- res = move_window(*fatfs, sect++);
- if (res != FR_OK) break;
- p = (*fatfs)->win;
- i = SS(*fatfs);
- }
- if (fat == FS_FAT16) {
- if (LD_WORD(p) == 0) n++;
- p += 2; i -= 2;
- } else {
- if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
- p += 4; i -= 4;
- }
- } while (--clst);
- }
- (*fatfs)->free_clust = n;
- if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1;
- *nclst = n;
- }
- }
- LEAVE_FF(*fatfs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Truncate File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_truncate (
- FIL *fp /* Pointer to the file object */
-)
-{
- FRESULT res;
- DWORD ncl;
-
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res == FR_OK) {
- if (fp->flag & FA__ERROR) { /* Check abort flag */
- res = FR_INT_ERR;
- } else {
- if (!(fp->flag & FA_WRITE)) /* Check access mode */
- res = FR_DENIED;
- }
- }
- if (res == FR_OK) {
- if (fp->fsize > fp->fptr) {
- fp->fsize = fp->fptr; /* Set file size to current R/W point */
- fp->flag |= FA__WRITTEN;
- if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
- res = remove_chain(fp->fs, fp->org_clust);
- fp->org_clust = 0;
- } else { /* When truncate a part of the file, remove remaining clusters */
- ncl = get_fat(fp->fs, fp->curr_clust);
- res = FR_OK;
- if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
- if (ncl == 1) res = FR_INT_ERR;
- if (res == FR_OK && ncl < fp->fs->n_fatent) {
- res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF);
- if (res == FR_OK) res = remove_chain(fp->fs, ncl);
- }
- }
- }
- if (res != FR_OK) fp->flag |= FA__ERROR;
- }
-
- LEAVE_FF(fp->fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Delete a File or Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_unlink (
- const TCHAR *path /* Pointer to the file or directory path */
-)
-{
- FRESULT res;
- DIR dj, sdj;
- BYTE *dir;
- DWORD dclst;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME; /* Cannot remove dot entry */
-#if _FS_SHARE
- if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */
-#endif
- if (res == FR_OK) { /* The object is accessible */
- dir = dj.dir;
- if (!dir) {
- res = FR_INVALID_NAME; /* Cannot remove the start directory */
- } else {
- if (dir[DIR_Attr] & AM_RDO)
- res = FR_DENIED; /* Cannot remove R/O object */
- }
- dclst = LD_CLUST(dir);
- if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
- if (dclst < 2) {
- res = FR_INT_ERR;
- } else {
- mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */
- sdj.sclust = dclst;
- res = dir_sdi(&sdj, 2); /* Exclude dot entries */
- if (res == FR_OK) {
- res = dir_read(&sdj);
- if (res == FR_OK /* Not empty dir */
-#if _FS_RPATH
- || dclst == sdj.fs->cdir /* Current dir */
-#endif
- ) res = FR_DENIED;
- if (res == FR_NO_FILE) res = FR_OK; /* Empty */
- }
- }
- }
- if (res == FR_OK) {
- res = dir_remove(&dj); /* Remove the directory entry */
- if (res == FR_OK) {
- if (dclst) /* Remove the cluster chain if exist */
- res = remove_chain(dj.fs, dclst);
- if (res == FR_OK) res = sync(dj.fs);
- }
- }
- }
- FREE_BUF();
- }
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create a Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mkdir (
- const TCHAR *path /* Pointer to the directory path */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir, n;
- DWORD dsc, dcl, pcl, tim = get_fattime();
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
- if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_NO_FILE) { /* Can create a new directory */
- dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */
- res = FR_OK;
- if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
- if (dcl == 1) res = FR_INT_ERR;
- if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
- if (res == FR_OK) /* Flush FAT */
- res = move_window(dj.fs, 0);
- if (res == FR_OK) { /* Initialize the new directory table */
- dsc = clust2sect(dj.fs, dcl);
- dir = dj.fs->win;
- mem_set(dir, 0, SS(dj.fs));
- mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */
- dir[DIR_Name] = '.';
- dir[DIR_Attr] = AM_DIR;
- ST_DWORD(dir+DIR_WrtTime, tim);
- ST_CLUST(dir, dcl);
- mem_cpy(dir+32, dir, 32); /* Create ".." entry */
- dir[33] = '.'; pcl = dj.sclust;
- if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
- pcl = 0;
- ST_CLUST(dir+32, pcl);
- for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */
- dj.fs->winsect = dsc++;
- dj.fs->wflag = 1;
- res = move_window(dj.fs, 0);
- if (res != FR_OK) break;
- mem_set(dir, 0, SS(dj.fs));
- }
- }
- if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */
- if (res != FR_OK) {
- remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */
- } else {
- dir = dj.dir;
- dir[DIR_Attr] = AM_DIR; /* Attribute */
- ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */
- ST_CLUST(dir, dcl); /* Table start cluster */
- dj.fs->wflag = 1;
- res = sync(dj.fs);
- }
- }
- FREE_BUF();
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Attribute */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_chmod (
- const TCHAR *path, /* Pointer to the file path */
- BYTE value, /* Attribute bits */
- BYTE mask /* Attribute mask to change */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- FREE_BUF();
- if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_OK) {
- dir = dj.dir;
- if (!dir) { /* Is it a root directory? */
- res = FR_INVALID_NAME;
- } else { /* File or sub directory */
- mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
- dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
- dj.fs->wflag = 1;
- res = sync(dj.fs);
- }
- }
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Timestamp */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_utime (
- const TCHAR *path, /* Pointer to the file/directory name */
- const FILINFO *fno /* Pointer to the time stamp to be set */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path, &dj.fs, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- FREE_BUF();
- if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_OK) {
- dir = dj.dir;
- if (!dir) { /* Root directory */
- res = FR_INVALID_NAME;
- } else { /* File or sub-directory */
- ST_WORD(dir+DIR_WrtTime, fno->ftime);
- ST_WORD(dir+DIR_WrtDate, fno->fdate);
- dj.fs->wflag = 1;
- res = sync(dj.fs);
- }
- }
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Rename File/Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_rename (
- const TCHAR *path_old, /* Pointer to the old name */
- const TCHAR *path_new /* Pointer to the new name */
-)
-{
- FRESULT res;
- DIR djo, djn;
- BYTE buf[21], *dir;
- DWORD dw;
- DEF_NAMEBUF;
-
-
- res = chk_mounted(&path_old, &djo.fs, 1);
- if (res == FR_OK) {
- djn.fs = djo.fs;
- INIT_BUF(djo);
- res = follow_path(&djo, path_old); /* Check old object */
- if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
- res = FR_INVALID_NAME;
-#if _FS_SHARE
- if (res == FR_OK) res = chk_lock(&djo, 2);
-#endif
- if (res == FR_OK) { /* Old object is found */
- if (!djo.dir) { /* Is root dir? */
- res = FR_NO_FILE;
- } else {
- mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */
- mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */
- res = follow_path(&djn, path_new);
- if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */
- if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */
-/* Start critical section that any interruption or error can cause cross-link */
- res = dir_register(&djn); /* Register the new entry */
- if (res == FR_OK) {
- dir = djn.dir; /* Copy object information except for name */
- mem_cpy(dir+13, buf+2, 19);
- dir[DIR_Attr] = buf[0] | AM_ARC;
- djo.fs->wflag = 1;
- if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */
- dw = clust2sect(djn.fs, LD_CLUST(dir));
- if (!dw) {
- res = FR_INT_ERR;
- } else {
- res = move_window(djn.fs, dw);
- dir = djn.fs->win+32; /* .. entry */
- if (res == FR_OK && dir[1] == '.') {
- dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust;
- ST_CLUST(dir, dw);
- djn.fs->wflag = 1;
- }
- }
- }
- if (res == FR_OK) {
- res = dir_remove(&djo); /* Remove old entry */
- if (res == FR_OK)
- res = sync(djo.fs);
- }
- }
-/* End critical section */
- }
- }
- }
- FREE_BUF();
- }
- LEAVE_FF(djo.fs, res);
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _FS_MINIMIZE == 0 */
-#endif /* _FS_MINIMIZE <= 1 */
-#endif /* _FS_MINIMIZE <= 2 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Forward data to the stream directly (available on only tiny cfg) */
-/*-----------------------------------------------------------------------*/
-#if _USE_FORWARD && _FS_TINY
-
-FRESULT f_forward (
- FIL *fp, /* Pointer to the file object */
- UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
- UINT btr, /* Number of bytes to forward */
- UINT *bf /* Pointer to number of bytes forwarded */
-)
-{
- FRESULT res;
- DWORD remain, clst, sect;
- UINT rcnt;
- BYTE csect;
-
-
- *bf = 0; /* Initialize byte counter */
-
- res = validate(fp->fs, fp->id); /* Check validity of the object */
- if (res != FR_OK) LEAVE_FF(fp->fs, res);
- if (fp->flag & FA__ERROR) /* Check error flag */
- LEAVE_FF(fp->fs, FR_INT_ERR);
- if (!(fp->flag & FA_READ)) /* Check access mode */
- LEAVE_FF(fp->fs, FR_DENIED);
-
- remain = fp->fsize - fp->fptr;
- if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
-
- for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */
- fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) {
- csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
- if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
- if (!csect) { /* On the cluster boundary? */
- clst = (fp->fptr == 0) ? /* On the top of the file? */
- fp->org_clust : get_fat(fp->fs, fp->curr_clust);
- if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
- fp->curr_clust = clst; /* Update current cluster */
- }
- }
- sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */
- if (!sect) ABORT(fp->fs, FR_INT_ERR);
- sect += csect;
- if (move_window(fp->fs, sect)) /* Move sector window */
- ABORT(fp->fs, FR_DISK_ERR);
- fp->dsect = sect;
- rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */
- if (rcnt > btr) rcnt = btr;
- rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
- if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
- }
-
- LEAVE_FF(fp->fs, FR_OK);
-}
-#endif /* _USE_FORWARD */
-
-
-
-#if _USE_MKFS && !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Create File System on the Drive */
-/*-----------------------------------------------------------------------*/
-#define N_ROOTDIR 512 /* Multiple of 32 */
-#define N_FATS 1 /* 1 or 2 */
-
-
-FRESULT f_mkfs (
- BYTE drv, /* Logical drive number */
- BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */
- UINT au /* Allocation unit size [bytes] */
-)
-{
- static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0};
- static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
- BYTE fmt, md, *tbl;
- DWORD n_clst, vs, n, wsect;
- UINT i;
- DWORD b_vol, b_fat, b_dir, b_data; /* Offset (LBA) */
- DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */
- FATFS *fs;
- DSTATUS stat;
-
- /* Check mounted drive and clear work area */
- if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
- fs = FatFs[drv];
- if (!fs) return FR_NOT_ENABLED;
- fs->fs_type = 0;
- drv = LD2PD(drv);
-
- /* Get disk statics */
- stat = disk_initialize(drv);
- if (stat & STA_NOINIT) return FR_NOT_READY;
- if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
-#if _MAX_SS != 512 /* Get disk sector size */
- if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK)
- return FR_DISK_ERR;
-#endif
- if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
- return FR_DISK_ERR;
- b_vol = (sfd) ? 0 : 63; /* Volume start sector */
- n_vol -= b_vol;
- if (au & (au - 1)) au = 0; /* Check validity of the allocation unit size */
- if (!au) { /* AU auto selection */
- vs = n_vol / (2000 / (SS(fs) / 512));
- for (i = 0; vs < vst[i]; i++) ;
- au = cst[i];
- }
- au /= SS(fs); /* Number of sectors per cluster */
- if (au == 0) au = 1;
- if (au > 128) au = 128;
-
- /* Pre-compute number of clusters and FAT syb-type */
- n_clst = n_vol / au;
- fmt = FS_FAT12;
- if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
- if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
-
- /* Determine offset and size of FAT structure */
- if (fmt == FS_FAT32) {
- n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
- n_rsv = 32;
- n_dir = 0;
- } else {
- n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
- n_fat = (n_fat + SS(fs) - 1) / SS(fs);
- n_rsv = 1;
- n_dir = N_ROOTDIR * 32UL / SS(fs);
- }
- b_fat = b_vol + n_rsv; /* FAT area start sector */
- b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */
- b_data = b_dir + n_dir; /* Data area start sector */
- if (n_vol < b_data + au) return FR_MKFS_ABORTED; /* Too small volume */
-
- /* Align data start sector to erase block boundary (for flash memory media) */
- if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
- n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */
- n = (n - b_data) / N_FATS;
- if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */
- n_rsv += n;
- b_fat += n;
- } else { /* FAT12/16: Expand FAT size */
- n_fat += n;
- }
-
- /* Determine number of cluster and final check of validity of the FAT sub-type */
- n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
- if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16)
- || (fmt == FS_FAT32 && n_clst < MIN_FAT32))
- return FR_MKFS_ABORTED;
-
- /* Create partition table if required */
- if (sfd) {
- md = 0xF0;
- } else {
- DWORD n_disk = b_vol + n_vol;
-
- mem_set(fs->win, 0, SS(fs));
- tbl = fs->win+MBR_Table;
- ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */
- if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */
- n_disk = n_disk / 63 / 255;
- tbl[7] = (BYTE)n_disk;
- tbl[6] = (BYTE)((n_disk >> 2) | 63);
- } else {
- ST_WORD(&tbl[6], 0xFFFF);
- }
- tbl[5] = 254;
- if (fmt != FS_FAT32) /* System ID */
- tbl[4] = (n_vol < 0x10000) ? 0x04 : 0x06;
- else
- tbl[4] = 0x0c;
- ST_DWORD(tbl+8, 63); /* Partition start in LBA */
- ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */
- ST_WORD(tbl+64, 0xAA55); /* Signature */
- if (disk_write(drv, fs->win, 0, 1) != RES_OK)
- return FR_DISK_ERR;
- md = 0xF8;
- }
-
- /* Create volume boot record */
- tbl = fs->win; /* Clear sector */
- mem_set(tbl, 0, SS(fs));
- mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot code, OEM name */
- i = SS(fs); /* Sector size */
- ST_WORD(tbl+BPB_BytsPerSec, i);
- tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */
- ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */
- tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */
- i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */
- ST_WORD(tbl+BPB_RootEntCnt, i);
- if (n_vol < 0x10000) { /* Number of total sectors */
- ST_WORD(tbl+BPB_TotSec16, n_vol);
- } else {
- ST_DWORD(tbl+BPB_TotSec32, n_vol);
- }
- tbl[BPB_Media] = md; /* Media descriptor */
- ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */
- ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */
- ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */
- n = get_fattime(); /* Use current time as VSN */
- if (fmt == FS_FAT32) {
- ST_DWORD(tbl+BS_VolID32, n); /* VSN */
- ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */
- ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */
- ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */
- ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */
- tbl[BS_DrvNum32] = 0x80; /* Drive number */
- tbl[BS_BootSig32] = 0x29; /* Extended boot signature */
- mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
- } else {
- ST_DWORD(tbl+BS_VolID, n); /* VSN */
- ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */
- tbl[BS_DrvNum] = 0x80; /* Drive number */
- tbl[BS_BootSig] = 0x29; /* Extended boot signature */
- mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
- }
- ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */
- if (disk_write(drv, tbl, b_vol, 1) != RES_OK)/* Write original (VBR) */
- return FR_DISK_ERR;
- if (fmt == FS_FAT32) /* Write backup (VBR+6) */
- disk_write(drv, tbl, b_vol + 6, 1);
-
- /* Initialize FAT area */
- wsect = b_fat;
- for (i = 0; i < N_FATS; i++) {
- mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */
- n = md; /* Media descriptor byte */
- if (fmt != FS_FAT32) {
- n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
- ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */
- } else {
- n |= 0xFFFFFF00;
- ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */
- ST_DWORD(tbl+4, 0xFFFFFFFF);
- ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */
- }
- if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
- return FR_DISK_ERR;
- mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */
- for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector write */
- if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
- return FR_DISK_ERR;
- }
- }
-
- /* Initialize root directory */
- i = (fmt == FS_FAT32) ? au : n_dir;
- do {
- if (disk_write(drv, tbl, wsect++, 1) != RES_OK)
- return FR_DISK_ERR;
- } while (--i);
-
-#if _USE_ERASE /* Erase data area if needed */
- {
- DWORD eb[2];
-
- eb[0] = wsect; eb[1] = wsect + n_clst * au - 1;
- disk_ioctl(drv, CTRL_ERASE_SECTOR, eb);
- }
-#endif
-
- /* Create FSInfo if needed */
- if (fmt == FS_FAT32) {
- ST_WORD(tbl+BS_55AA, 0xAA55);
- ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
- ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
- ST_DWORD(tbl+FSI_Free_Count, n_clst - 1);
- ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF);
- disk_write(drv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */
- disk_write(drv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */
- }
-
- return (disk_ioctl(drv, CTRL_SYNC, (void*)0) == RES_OK) ? FR_OK : FR_DISK_ERR;
-}
-
-#endif /* _USE_MKFS && !_FS_READONLY */
-
-
-
-
-#if _USE_STRFUNC
-/*-----------------------------------------------------------------------*/
-/* Get a string from the file */
-/*-----------------------------------------------------------------------*/
-TCHAR* f_gets (
- TCHAR* buff, /* Pointer to the string buffer to read */
- int len, /* Size of string buffer (characters) */
- FIL* fil /* Pointer to the file object */
-)
-{
- int n = 0;
- TCHAR c, *p = buff;
- BYTE s[2];
- UINT rc;
-
-
- while (n < len - 1) { /* Read bytes until buffer gets filled */
- f_read(fil, s, 1, &rc);
- if (rc != 1) break; /* Break on EOF or error */
- c = s[0];
-#if _LFN_UNICODE /* Read a character in UTF-8 encoding */
- if (c >= 0x80) {
- if (c < 0xC0) continue; /* Skip stray trailer */
- if (c < 0xE0) { /* Two-byte sequense */
- f_read(fil, s, 1, &rc);
- if (rc != 1) break;
- c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
- if (c < 0x80) c = '?';
- } else {
- if (c < 0xF0) { /* Three-byte sequense */
- f_read(fil, s, 2, &rc);
- if (rc != 2) break;
- c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
- if (c < 0x800) c = '?';
- } else { /* Reject four-byte sequense */
- c = '?';
- }
- }
- }
-#endif
-#if _USE_STRFUNC >= 2
- if (c == '\r') continue; /* Strip '\r' */
-#endif
- *p++ = c;
- n++;
- if (c == '\n') break; /* Break on EOL */
- }
- *p = 0;
- return n ? buff : 0; /* When no data read (eof or error), return with error. */
-}
-
-
-
-#if !_FS_READONLY
-#include <stdarg.h>
-/*-----------------------------------------------------------------------*/
-/* Put a character to the file */
-/*-----------------------------------------------------------------------*/
-int f_putc (
- TCHAR c, /* A character to be output */
- FIL* fil /* Pointer to the file object */
-)
-{
- UINT bw, btw;
- BYTE s[3];
-
-
-#if _USE_STRFUNC >= 2
- if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */
-#endif
-
-#if _LFN_UNICODE /* Write the character in UTF-8 encoding */
- if (c < 0x80) { /* 7-bit */
- s[0] = (BYTE)c;
- btw = 1;
- } else {
- if (c < 0x800) { /* 11-bit */
- s[0] = (BYTE)(0xC0 | (c >> 6));
- s[1] = (BYTE)(0x80 | (c & 0x3F));
- btw = 2;
- } else { /* 16-bit */
- s[0] = (BYTE)(0xE0 | (c >> 12));
- s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
- s[2] = (BYTE)(0x80 | (c & 0x3F));
- btw = 3;
- }
- }
-#else /* Write the character without conversion */
- s[0] = (BYTE)c;
- btw = 1;
-#endif
- f_write(fil, s, btw, &bw); /* Write the char to the file */
- return (bw == btw) ? 1 : EOF; /* Return the result */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a string to the file */
-/*-----------------------------------------------------------------------*/
-int f_puts (
- const TCHAR* str, /* Pointer to the string to be output */
- FIL* fil /* Pointer to the file object */
-)
-{
- int n;
-
-
- for (n = 0; *str; str++, n++) {
- if (f_putc(*str, fil) == EOF) return EOF;
- }
- return n;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a formatted string to the file */
-/*-----------------------------------------------------------------------*/
-int f_printf (
- FIL* fil, /* Pointer to the file object */
- const TCHAR* str, /* Pointer to the format string */
- ... /* Optional arguments... */
-)
-{
- va_list arp;
- BYTE f, r;
- UINT i, w;
- ULONG val;
- TCHAR c, d, s[16];
- int res, cc;
-
-
- va_start(arp, str);
-
- for (cc = res = 0; cc != EOF; res += cc) {
- c = *str++;
- if (c == 0) break; /* End of string */
- if (c != '%') { /* Non escape character */
- cc = f_putc(c, fil);
- if (cc != EOF) cc = 1;
- continue;
- }
- w = f = 0;
- c = *str++;
- if (c == '0') { /* Flag: '0' padding */
- f = 1; c = *str++;
- }
- while (IsDigit(c)) { /* Precision */
- w = w * 10 + c - '0';
- c = *str++;
- }
- if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
- f |= 2; c = *str++;
- }
- if (!c) break;
- d = c;
- if (IsLower(d)) d -= 0x20;
- switch (d) { /* Type is... */
- case 'S' : /* String */
- cc = f_puts(va_arg(arp, TCHAR*), fil); continue;
- case 'C' : /* Character */
- cc = f_putc((TCHAR)va_arg(arp, int), fil); continue;
- case 'B' : /* Binary */
- r = 2; break;
- case 'O' : /* Octal */
- r = 8; break;
- case 'D' : /* Signed decimal */
- case 'U' : /* Unsigned decimal */
- r = 10; break;
- case 'X' : /* Hexdecimal */
- r = 16; break;
- default: /* Unknown */
- cc = f_putc(c, fil); continue;
- }
-
- /* Get an argument */
- val = (f & 2) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : va_arg(arp, unsigned int));
- if (d == 'D' && (val & 0x80000000)) {
- val = 0 - val;
- f |= 4;
- }
- /* Put it in numeral string */
- i = 0;
- do {
- d = (TCHAR)(val % r); val /= r;
- if (d > 9) {
- d += 7;
- if (c == 'x') d += 0x20;
- }
- s[i++] = d + '0';
- } while (val && i < sizeof(s) / sizeof(s[0]));
- if (f & 4) s[i++] = '-';
- cc = 0;
- while (i < w-- && cc != EOF) {
- cc = f_putc((TCHAR)((f & 1) ? '0' : ' '), fil);
- res++;
- }
- do {
- cc = f_putc(s[--i], fil);
- res++;
- } while (i && cc != EOF);
- if (cc != EOF) cc = 0;
- }
-
- va_end(arp);
- return (cc == EOF) ? cc : res;
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _USE_STRFUNC */
-
-#endif /* XPAR_PS7_SD_0_S_AXI_BASEADDR */
diff --git a/quad/zybo_fsbl/src/ff.h b/quad/zybo_fsbl/src/ff.h
deleted file mode 100644
index a2cf4907a0c1fb7e207492ca4c8b68fb14e5b821..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/ff.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/*---------------------------------------------------------------------------/
-/ FatFs - FAT file system module include file R0.08a (C)ChaN, 2010
-/----------------------------------------------------------------------------/
-/ FatFs module is a generic FAT file system module for small embedded systems.
-/ This is a free software that opened for education, research and commercial
-/ developments under license policy of following trems.
-/
-/ Copyright (C) 2010, ChaN, all right reserved.
-/
-/ * The FatFs module is a free software and there is NO WARRANTY.
-/ * No restriction on use. You can use, modify and redistribute it for
-/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
-/ * Redistributions of source code must retain the above copyright notice.
-/
-/----------------------------------------------------------------------------*/
-
-#ifndef _FATFS
-#define _FATFS 8255 /* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h" /* Basic integer types */
-#include "ffconf.h" /* FatFs configuration options */
-
-#if _FATFS != _FFCONF
-#error Wrong configuration file (ffconf.h).
-#endif
-
-
-/* DBCS code ranges and SBCS extend char conversion table */
-
-#if _CODE_PAGE == 932 /* Japanese Shift-JIS */
-#define _DF1S 0x81 /* DBC 1st byte range 1 start */
-#define _DF1E 0x9F /* DBC 1st byte range 1 end */
-#define _DF2S 0xE0 /* DBC 1st byte range 2 start */
-#define _DF2E 0xFC /* DBC 1st byte range 2 end */
-#define _DS1S 0x40 /* DBC 2nd byte range 1 start */
-#define _DS1E 0x7E /* DBC 2nd byte range 1 end */
-#define _DS2S 0x80 /* DBC 2nd byte range 2 start */
-#define _DS2E 0xFC /* DBC 2nd byte range 2 end */
-
-#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
-#define _DF1S 0x81
-#define _DF1E 0xFE
-#define _DS1S 0x40
-#define _DS1E 0x7E
-#define _DS2S 0x80
-#define _DS2E 0xFE
-
-#elif _CODE_PAGE == 949 /* Korean */
-#define _DF1S 0x81
-#define _DF1E 0xFE
-#define _DS1S 0x41
-#define _DS1E 0x5A
-#define _DS2S 0x61
-#define _DS2E 0x7A
-#define _DS3S 0x81
-#define _DS3E 0xFE
-
-#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
-#define _DF1S 0x81
-#define _DF1E 0xFE
-#define _DS1S 0x40
-#define _DS1E 0x7E
-#define _DS2S 0xA1
-#define _DS2E 0xFE
-
-#elif _CODE_PAGE == 437 /* U.S. (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 720 /* Arabic (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 737 /* Greek (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
- 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 775 /* Baltic (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
- 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
-
-#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
- 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
- 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 857 /* Turkish (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 866 /* Russian (OEM) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
-
-#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
- 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
-
-#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
-
-#elif _CODE_PAGE == 1253 /* Greek (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
- 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
-
-#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
-
-#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
-
-#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
-#define _DF1S 0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
- 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
-
-#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */
-#define _DF1S 0
-
-#else
-#error Unknown code page
-
-#endif
-
-
-
-/* Definitions of volume management */
-
-#if _MULTI_PARTITION /* Multiple partition configuration */
-#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive# */
-#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition# */
-typedef struct {
- BYTE pd; /* Physical drive# */
- BYTE pt; /* Partition # (0-3) */
-} PARTITION;
-extern const PARTITION VolToPart[]; /* Volume - Physical location resolution table */
-
-#else /* Single partition configuration */
-#define LD2PD(vol) (vol) /* Logical drive# is bound to the same physical drive# */
-#define LD2PT(vol) 0 /* Always mounts the 1st partition */
-
-#endif
-
-
-
-/* Type of path name strings on FatFs API */
-
-#if _LFN_UNICODE /* Unicode string */
-#if !_USE_LFN
-#error _LFN_UNICODE must be 0 in non-LFN cfg.
-#endif
-#ifndef _INC_TCHAR
-typedef WCHAR TCHAR;
-#define _T(x) L ## x
-#define _TEXT(x) L ## x
-#endif
-
-#else /* ANSI/OEM string */
-#ifndef _INC_TCHAR
-typedef char TCHAR;
-#define _T(x) x
-#define _TEXT(x) x
-#endif
-
-#endif
-
-
-
-/* File system object structure (FATFS) */
-
-typedef struct {
- BYTE fs_type; /* FAT sub-type (0:Not mounted) */
- BYTE drv; /* Physical drive number */
- BYTE csize; /* Sectors per cluster (1,2,4...128) */
- BYTE n_fats; /* Number of FAT copies (1,2) */
- BYTE wflag; /* win[] dirty flag (1:must be written back) */
- BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */
- WORD id; /* File system mount ID */
- WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
-#if _MAX_SS != 512
- WORD ssize; /* Bytes per sector (512,1024,2048,4096) */
-#endif
-#if _FS_REENTRANT
- _SYNC_t sobj; /* Identifier of sync object */
-#endif
-#if !_FS_READONLY
- DWORD last_clust; /* Last allocated cluster */
- DWORD free_clust; /* Number of free clusters */
- DWORD fsi_sector; /* fsinfo sector (FAT32) */
-#endif
-#if _FS_RPATH
- DWORD cdir; /* Current directory start cluster (0:root) */
-#endif
- DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
- DWORD fsize; /* Sectors per FAT */
- DWORD fatbase; /* FAT start sector */
- DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
- DWORD database; /* Data start sector */
- DWORD winsect; /* Current sector appearing in the win[] */
- BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
-} FATFS;
-
-
-
-/* File object structure (FIL) */
-
-typedef struct {
- FATFS* fs; /* Pointer to the owner file system object */
- WORD id; /* Owner file system mount ID */
- BYTE flag; /* File status flags */
- BYTE pad1;
- DWORD fptr; /* File read/write pointer (0 on file open) */
- DWORD fsize; /* File size */
- DWORD org_clust; /* File start cluster (0 when fsize==0) */
- DWORD curr_clust; /* Current cluster */
- DWORD dsect; /* Current data sector */
-#if !_FS_READONLY
- DWORD dir_sect; /* Sector containing the directory entry */
- BYTE* dir_ptr; /* Ponter to the directory entry in the window */
-#endif
-#if _USE_FASTSEEK
- DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */
-#endif
-#if _FS_SHARE
- UINT lockid; /* File lock ID (index of file semaphore table) */
-#endif
-#if !_FS_TINY
- BYTE buf[_MAX_SS]; /* File data read/write buffer */
-#endif
-} FIL;
-
-
-
-/* Directory object structure (DIR) */
-
-typedef struct {
- FATFS* fs; /* Pointer to the owner file system object */
- WORD id; /* Owner file system mount ID */
- WORD index; /* Current read/write index number */
- DWORD sclust; /* Table start cluster (0:Root dir) */
- DWORD clust; /* Current cluster */
- DWORD sect; /* Current sector */
- BYTE* dir; /* Pointer to the current SFN entry in the win[] */
- BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
-#if _USE_LFN
- WCHAR* lfn; /* Pointer to the LFN working buffer */
- WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
-#endif
-} DIR;
-
-
-
-/* File status structure (FILINFO) */
-
-typedef struct {
- DWORD fsize; /* File size */
- WORD fdate; /* Last modified date */
- WORD ftime; /* Last modified time */
- BYTE fattrib; /* Attribute */
- TCHAR fname[13]; /* Short file name (8.3 format) */
-#if _USE_LFN
- TCHAR* lfname; /* Pointer to the LFN buffer */
- UINT lfsize; /* Size of LFN buffer in TCHAR */
-#endif
-} FILINFO;
-
-
-
-/* File function return code (FRESULT) */
-
-typedef enum {
- FR_OK = 0, /* (0) Succeeded */
- FR_DISK_ERR, /* (1) A hard error occured in the low level disk I/O layer */
- FR_INT_ERR, /* (2) Assertion failed */
- FR_NOT_READY, /* (3) The physical drive cannot work */
- FR_NO_FILE, /* (4) Could not find the file */
- FR_NO_PATH, /* (5) Could not find the path */
- FR_INVALID_NAME, /* (6) The path name format is invalid */
- FR_DENIED, /* (7) Acces denied due to prohibited access or directory full */
- FR_EXIST, /* (8) Acces denied due to prohibited access */
- FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
- FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
- FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
- FR_NOT_ENABLED, /* (12) The volume has no work area */
- FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume on the physical drive */
- FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
- FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
- FR_LOCKED, /* (16) The operation is rejected according to the file shareing policy */
- FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
- FR_TOO_MANY_OPEN_FILES /* (18) Number of open files > _FS_SHARE */
-} FRESULT;
-
-
-
-/*--------------------------------------------------------------*/
-/* FatFs module application interface */
-
-FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */
-FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */
-FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */
-FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */
-FRESULT f_close (FIL*); /* Close an open file object */
-FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */
-FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */
-FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
-
-#if !_FS_READONLY
-FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */
-FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */
-FRESULT f_truncate (FIL*); /* Truncate file */
-FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
-FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
-FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
-FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */
-FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */
-FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
-#endif
-
-#if _USE_FORWARD
-FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */
-#endif
-
-#if _USE_MKFS
-FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */
-#endif
-
-#if _FS_RPATH
-FRESULT f_chdrive (BYTE); /* Change current drive */
-FRESULT f_chdir (const TCHAR*); /* Change current directory */
-FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */
-#endif
-
-#if _USE_STRFUNC
-int f_putc (TCHAR, FIL*); /* Put a character to the file */
-int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
-int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
-TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
-#ifndef EOF
-#define EOF (-1)
-#endif
-#endif
-
-#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
-#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
-#define f_tell(fp) ((fp)->fptr)
-#define f_size(fp) ((fp)->fsize)
-
-
-
-/*--------------------------------------------------------------*/
-/* Additional user defined functions */
-
-/* RTC function */
-#if !_FS_READONLY
-DWORD get_fattime (void);
-#endif
-
-/* Unicode support functions */
-#if _USE_LFN /* Unicode - OEM code conversion */
-WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */
-WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */
-#if _USE_LFN == 3 /* Memory functions */
-void* ff_memalloc (UINT); /* Allocate memory block */
-void ff_memfree (void*); /* Free memory block */
-#endif
-#endif
-
-/* Sync functions */
-#if _FS_REENTRANT
-int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
-int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
-int ff_req_grant (_SYNC_t); /* Lock sync object */
-void ff_rel_grant (_SYNC_t); /* Unlock sync object */
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Flags and offset address */
-
-
-/* File access control and file status flags (FIL.flag) */
-
-#define FA_READ 0x01
-#define FA_OPEN_EXISTING 0x00
-#define FA__ERROR 0x80
-
-#if !_FS_READONLY
-#define FA_WRITE 0x02
-#define FA_CREATE_NEW 0x04
-#define FA_CREATE_ALWAYS 0x08
-#define FA_OPEN_ALWAYS 0x10
-#define FA__WRITTEN 0x20
-#define FA__DIRTY 0x40
-#endif
-
-
-/* FAT sub type (FATFS.fs_type) */
-
-#define FS_FAT12 1
-#define FS_FAT16 2
-#define FS_FAT32 3
-
-
-/* File attribute bits for directory entry */
-
-#define AM_RDO 0x01 /* Read only */
-#define AM_HID 0x02 /* Hidden */
-#define AM_SYS 0x04 /* System */
-#define AM_VOL 0x08 /* Volume label */
-#define AM_LFN 0x0F /* LFN entry */
-#define AM_DIR 0x10 /* Directory */
-#define AM_ARC 0x20 /* Archive */
-#define AM_MASK 0x3F /* Mask of defined bits */
-
-
-/* Fast seek function */
-#define CREATE_LINKMAP 0xFFFFFFFF
-
-
-/*--------------------------------*/
-/* Multi-byte word access macros */
-
-#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
- #define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
- #define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
- #define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
- #define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
-#else /* Use byte-by-byte access to the FAT structure */
- #define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
- #define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr))
- #define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8)
- #define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FATFS */
diff --git a/quad/zybo_fsbl/src/ffconf.h b/quad/zybo_fsbl/src/ffconf.h
deleted file mode 100644
index 1b57f9705773169512413e4f60ba658703f12fd9..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/ffconf.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*---------------------------------------------------------------------------/
-/ FatFs - FAT file system module configuration file R0.08a (C)ChaN, 2010
-/----------------------------------------------------------------------------/
-/
-/ CAUTION! Do not forget to make clean the project after any changes to
-/ the configuration options.
-/
-/----------------------------------------------------------------------------*/
-#ifndef _FFCONF
-#define _FFCONF 8255 /* Revision ID */
-
-
-/*---------------------------------------------------------------------------/
-/ Function and Buffer Configurations
-/----------------------------------------------------------------------------*/
-
-#define _FS_TINY 1 /* 0:Normal or 1:Tiny */
-/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
-/ object instead of the sector buffer in the individual file object for file
-/ data transfer. This reduces memory consumption 512 bytes each file object. */
-
-
-#define _FS_READONLY 1 /* 0:Read/Write or 1:Read only */
-/* Setting _FS_READONLY to 1 defines read only configuration. This removes
-/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
-/ f_truncate and useless f_getfree. */
-
-
-#define _FS_MINIMIZE 1 /* 0 to 3 */
-/* The _FS_MINIMIZE option defines minimization level to remove some functions.
-/
-/ 0: Full function.
-/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
-/ are removed.
-/ 2: f_opendir and f_readdir are removed in addition to 1.
-/ 3: f_lseek is removed in addition to 2. */
-
-
-#define _USE_STRFUNC 0 /* 0:Disable or 1/2:Enable */
-/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
-
-
-#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
-/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
-
-
-#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
-/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
-
-
-#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
-/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ Locale and Namespace Configurations
-/----------------------------------------------------------------------------*/
-
-#define _CODE_PAGE 437
-/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
-/ Incorrect setting of the code page can cause a file open failure.
-/
-/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
-/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
-/ 949 - Korean (DBCS, OEM, Windows)
-/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
-/ 1250 - Central Europe (Windows)
-/ 1251 - Cyrillic (Windows)
-/ 1252 - Latin 1 (Windows)
-/ 1253 - Greek (Windows)
-/ 1254 - Turkish (Windows)
-/ 1255 - Hebrew (Windows)
-/ 1256 - Arabic (Windows)
-/ 1257 - Baltic (Windows)
-/ 1258 - Vietnam (OEM, Windows)
-/ 437 - U.S. (OEM)
-/ 720 - Arabic (OEM)
-/ 737 - Greek (OEM)
-/ 775 - Baltic (OEM)
-/ 850 - Multilingual Latin 1 (OEM)
-/ 858 - Multilingual Latin 1 + Euro (OEM)
-/ 852 - Latin 2 (OEM)
-/ 855 - Cyrillic (OEM)
-/ 866 - Russian (OEM)
-/ 857 - Turkish (OEM)
-/ 862 - Hebrew (OEM)
-/ 874 - Thai (OEM, Windows)
-/ 1 - ASCII only (Valid for non LFN cfg.)
-*/
-
-
-#define _USE_LFN 0 /* 0 to 3 */
-#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
-/* The _USE_LFN option switches the LFN support.
-/
-/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
-/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
-/ 2: Enable LFN with dynamic working buffer on the STACK.
-/ 3: Enable LFN with dynamic working buffer on the HEAP.
-/
-/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
-/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
-/ to the project. When enable to use heap, memory control functions
-/ ff_memalloc() and ff_memfree() must be added to the project. */
-
-
-#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
-/* To switch the character code set on FatFs API to Unicode,
-/ enable LFN feature and set _LFN_UNICODE to 1. */
-
-
-#define _FS_RPATH 0 /* 0 to 2 */
-/* The _FS_RPATH option configures relative path feature.
-/
-/ 0: Disable relative path feature and remove related functions.
-/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
-/ 2: f_getcwd() is available in addition to 1.
-/
-/ Note that output of the f_readdir fnction is affected by this option. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ Physical Drive Configurations
-/----------------------------------------------------------------------------*/
-
-#define _VOLUMES 1
-/* Number of volumes (logical drives) to be used. */
-
-
-#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
-/* Maximum sector size to be handled.
-/ Always set 512 for memory card and hard disk but a larger value may be
-/ required for floppy disk (512/1024) and optical disk (512/2048).
-/ When _MAX_SS is larger than 512, GET_SECTOR_SIZE command must be implememted
-/ to the disk_ioctl function. */
-
-
-#define _MULTI_PARTITION 0 /* 0:Single partition or 1:Multiple partition */
-/* When set to 0, each volume is bound to the same physical drive number and
-/ it can mount only first primaly partition. When it is set to 1, each volume
-/ is tied to the partitions listed in VolToPart[]. */
-
-
-#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
-/* To enable sector erase feature, set _USE_ERASE to 1. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ System Configurations
-/----------------------------------------------------------------------------*/
-
-#define _WORD_ACCESS 0 /* 0 or 1 */
-/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
-/ option defines which access method is used to the word data on the FAT volume.
-/
-/ 0: Byte-by-byte access.
-/ 1: Word access. Do not choose this unless following condition is met.
-/
-/ When the byte order on the memory is big-endian or address miss-aligned word
-/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
-/ If it is not the case, the value can also be set to 1 to improve the
-/ performance and code size. */
-
-
-/* Include a header file here to define sync object types on the O/S */
-/* #include <windows.h>, <ucos_ii.h.h>, <semphr.h> or ohters. */
-
-#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
-#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
-#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
-
-/* The _FS_REENTRANT option switches the reentrancy of the FatFs module.
-/
-/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
-/ 1: Enable reentrancy. Also user provided synchronization handlers,
-/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
-/ function must be added to the project. */
-
-
-#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */
-/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value
- defines how many files can be opened simultaneously. */
-
-
-#endif /* _FFCONFIG */
diff --git a/quad/zybo_fsbl/src/fsbl.h b/quad/zybo_fsbl/src/fsbl.h
deleted file mode 100644
index edb0e039e48855ad119c479d2a66d84465a5f979..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/fsbl.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file fsbl.h
-*
-* Contains the function prototypes, defines and macros for the
-* First Stage Boot Loader (FSBL) functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 03/04/11 Initial release
-* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
-* xparameters.h file
-* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
-* Added the debug levels
-* 4.00a sgd 02/28/13 Removed DDR initialization check
-* Removed DDR ECC initialization code
-* Modified hand off address check to 1MB
-* Added RSA authentication support
-* Removed LPBK_DLY_ADJ register setting code as we use
-* divisor 8
-* Removed check for Fabric is already initialized
-*
-* CR's fixed and description
-* 689026: FSBL doesn't hold PL resets active during
-* bit download
-* Resolution: PL resets are released just before
-* handoff
-*
-* 689077: FSBL hangs at Handoff clearing the
-* TX UART buffer
-* Resolution: STDOUT_BASEADDRESS macro value changes
-* based UART select, hence used STDOUT_BASEADDRESS
-* as UART base address
-*
-* 695578: FSBL failed to load standalone application
-* in secure bootmode
-* Resolution: Application will be placed at load address
-* instead of DDR temporary address
-*
-* 699475: FSBL functionality is broken and its
-* not able to boot in QSPI/NAND bootmode
-* Resolution: New flags are added DevCfg driver
-* for handling loopback
-* XDCFG_CONCURRENT_NONSEC_READ_WRITE
-* XDCFG_CONCURRENT_SECURE_READ_WRITE
-*
-* 683145: Define stack area for FIQ, UNDEF modes
-* in linker file
-* Resolution: FSBL linker modified to create stack area
-* for FIQ, UNDEF
-*
-* 705664: FSBL fails to decrypt the bitstream when
-* the image is AES encrypted using non-zero key value
-* Resolution: Fabric cleaning will not be done
-* for AES-E-Fuse encryption
-*
-* Watchdog disabled for AES E-Fuse encryption
-*
-* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
-* Added QSPI Flash Size > 128Mbit support
-* QSPI Dual Stack support
-* Added Md5 checksum support
-*
-* CR's fixed and description
-* 692045 FSBL: Linker script of FSBL has PHDR workaround,
-* this needs to be fixed
-* Resolution: Removed PHDR from Linker file
-*
-* 704287 FSBL: fsbl.h file has a few error codes that
-* are not used by FSBL, that needs to be removed
-* Resolution: Removed unused error codes
-*
-* 704379 FSBL: Check if DDR is in proper state before
-* handoff
-* Resolution: Added DDR initialization check
-*
-* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
-* the debug level is FSBL_DEBUG only.
-*
-* 710128 FSBL: Linux boot failing without load attribute
-* set for Linux partitions in BIF
-* Resolution: FSBL will load partitions with valid load
-* address and stop loading if any invalid load address
-*
-* 708728 Issues seen while making HP interconnect
-* 32 bit wide
-* Resolution: ps7_post_config function generated by PCW
-* will be called after Bit stream download
-* Added MMC support
-* 6.00a kc 07/31/2013 CR's fixed and description
-* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
-* for authenticating the Partition images
-* Resolution: FSBL now uses the PPK left by Boot ROM in
-* OCM for authencating the SPK
-*
-* 724165 Partition Header used by FSBL is not
-* authenticated
-* Resolution: FSBL now authenticates the partition header
-*
-* 691150 ps7_init does not check for peripheral
-* initialization failures or timeout on polls
-* Resolution: Return value of ps7_init() is now checked
-* by FSBL and prints the error string
-*
-* 708316 PS7_init.tcl file should have Error mechanism
-* for all mask_poll
-* Resolution: Return value of ps7_init() is now checked
-* by FSBL and prints the error string
-*
-* 732062 FSBL fails to build if UART not available
-* Resolution: Added define to call xil_printf only
-* if uart is defined
-*
-* 722979 Provide customer-friendly changelogs in FSBL
-* Resolution: Added CR description for all the files
-*
-* 732865 Backward compatibility for ps7_init function
-* Resolution: Added a new define for ps7_init success
-* and value is defined based on ps7_init define
-*
-* Fix for CR#739711 - FSBL not able to read Large
-* QSPI (512M) in IO Mode
-* Resolution: Modified the address calculation
-* algorithm in dual parallel mode for QSPI
-*
-* </pre>
-*
-* </pre>
-*
-* @note
-*
-* Flags in FSBL
-*
-* FSBL_PERF
-*
-* This Flag can be set at compilation time. This flag is set for
-* measuring the performance of FSBL.That is the time taken to execute is
-* measured.when this flag is set.Execution time with reference to
-* global timer is taken here
-*
-* Total Execution time is the time taken for executing FSBL till handoff
-* to any application .
-* If there is a bitstream in the partition header then the
-* execution time includes the copying of the bitstream to DDR
-* (in case of SD/NAND bootmode)
-* and programming the devcfg dma is accounted.
-*
-* FSBL provides two debug levels
-* DEBUG GENERAL - fsbl_printf under this category will appear only when the
-* FSBL_DEBUG flag is set during compilation
-* DEBUG_INFO - fsbl_printf under this category will appear when the
-* FSBL_DEBUG_INFO flag is set during compilation
-* For a more detailed output log can be used.
-* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
-* RSA functions
-* These macros are input to the fsbl_printf function
-*
-* DEBUG LEVELS
-* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
-* that are with the DEBUG_GENERAL argument are shown
-* FSBL_DEBUG_INFO is level 2, when this flag is set during the
-* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
-*
-* DEFAULT LEVEL
-* By default no print messages will appear.
-*
-* NON_PS_INSTANTIATED_BITSTREAM
-*
-* FSBL will not enable the level shifters for a NON PS instantiated
-* Bitstream.This flag can be set during compilation for a NON PS instantiated
-* bitstream
-*
-* ECC_ENABLE
-* This flag will be defined in the ps7_init.h file when ECC is enabled
-* in the DDR configuration (XPS GUI)
-*
-* RSA_SUPPORT
-* This flag is used to enable authentication feature
-* Default this macro disabled, reason to avoid increase in code size
-*
-* MMC_SUPPORT
-* This flag is used to enable MMC support feature
-*
-*******************************************************************************/
-#ifndef XIL_FSBL_H
-#define XIL_FSBL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "xparameters.h"
-#include "xpseudo_asm.h"
-#include "xil_printf.h"
-#include "pcap.h"
-#include "fsbl_debug.h"
-#include "ps7_init.h"
-#ifdef FSBL_PERF
-#include "xtime_l.h"
-#include <stdio.h>
-#endif
-
-
-/************************** Constant Definitions *****************************/
-/*
- * SDK release version
- */
-#define SDK_RELEASE_VER 14
-#define SDK_SUB_VER 7
-#define SDK_RELEASE_YEAR 2013
-#define SDK_RELEASE_QUARTER 3
-
-#define WORD_LENGTH_SHIFT 2
-
-/*
- * On a Successful handoff to an application FSBL sets this SUCCESS code
- */
-#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
-
-/*
- * Backward compatibility for ps7_init
- */
-#ifdef NEW_PS7_ERR_CODE
-#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
-#else
-#define FSBL_PS7_INIT_SUCCESS (1)
-#endif
-
-/*
- * ERROR CODES
- * The following are the Error codes that FSBL uses
- * If the Debug prints are enabled only then the error codes will be
- * seen on the com port.Without the debug prints enabled no error codes will
- * be visible.There are not saved in any register
- * Boot Mode States used for error and status output
- * Error codes are defined below
- */
-#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
-#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
-#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
-#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
-#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
-#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
-#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
-#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
-#define NO_DDR 0xA008 /**< DDR missing */
-#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
-#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
-#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
-#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
-#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
-#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
-#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
-#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
-#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
-#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
-/*
- * FSBL Exception error codes
- */
-#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
-#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
-#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
-#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
-#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
-#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
-
-/*
- * FSBL hook routine failures
- */
-#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
-#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
- download hook failed */
-#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
- download hook failed */
-
-/*
- * Watchdog related Error codes
- */
-#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
-#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
-
-/*
- * SLCR Registers
- */
-#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
-#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
-#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
-#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
-#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
-#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
-#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
-
-/*
- * Efuse Status Register
- */
-#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
-#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
-
-/*
- * PS reset control register define
- */
-#define PS_RST_MASK 0x1 /**< PS software reset */
-
-/*
- * SLCR BOOT Mode Register defines
- */
-#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
-
-/*
- * Boot Modes
- */
-#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
-#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
-#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
-#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
-#define SD_MODE 0x00000005 /**< SD Boot Mode */
-#define MMC_MODE 0x00000006 /**< MMC Boot Device */
-
-#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
-#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
-
-/*
- * Golden image offset
- */
-#define GOLDEN_IMAGE_OFFSET 0x8000
-
-/*
- * Silicon Version
- */
-#define SILICON_VERSION_1 0
-#define SILICON_VERSION_2 1
-#define SILICON_VERSION_3 2
-#define SILICON_VERSION_3_1 3
-
-/*
- * DDR start address for storing the data temporarily(1M)
- * Need to finalize correct logic
- */
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
-#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
-#else
-/*
- * In case of PL DDR, this macros defined based PL DDR address
- */
-#define DDR_START_ADDR 0x00
-#define DDR_END_ADDR 0x00
-#endif
-
-#define DDR_TEMP_START_ADDR DDR_START_ADDR
-/*
- * DDR test pattern
- */
-#define DDR_TEST_PATTERN 0xAA55AA55
-#define DDR_TEST_OFFSET 0x100000
-/*
- *
- */
-#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
-#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
-#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
-#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
-#define LQSPI_CFG_OFFSET 0xA0
-#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
-
-/*
- * These are the SLCR lock and unlock macros
- */
-#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
-#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
-
-#define IMAGE_HEADER_CHECKSUM_COUNT 10
-
-/* Boot ROM Image defines */
-#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
-#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
-#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
-#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
-#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
-#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
-#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
-#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
-#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
-#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
-#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
-#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
-
-/* Reboot status register defines:
- * 0xF0000000 for FSBL fallback mask to notify Boot Rom
- * 0x60000000 for FSBL to mark that FSBL has not handoff yet
- * 0x00FFFFFF for user application to use across soft reset
- */
-#define FSBL_FAIL_MASK 0xF0000000
-#define FSBL_IN_MASK 0x60000000
-
-/* The address that holds the base address for the image Boot ROM found */
-#define BASEADDR_HOLDER 0xFFFFFFF8
-
-/**************************** Type Definitions *******************************/
-
-/************************** Function Prototypes ******************************/
-
-void OutputStatus(u32 State);
-void FsblFallback(void);
-
-int FsblSetNextPartition(int Num);
-void *(memcpy_rom)(void * s1, const void * s2, u32 n);
-char *strcpy_rom(char *Dest, const char *Src);
-
-void ClearFSBLIn(void);
-void MarkFSBLIn(void);
-void FsblHandoff(u32 FsblStartAddr);
-u32 GetResetReason(void);
-
-#ifdef FSBL_PERF
-void FsblGetGlobalTime (XTime tCur);
-void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
-#endif
-void GetSiliconVersion(void);
-void FsblHandoffExit(u32 FsblStartAddr);
-void FsblHandoffJtagExit();
-/************************** Variable Definitions *****************************/
-extern int SkipPartition;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/zybo_fsbl/src/fsbl_debug.h b/quad/zybo_fsbl/src/fsbl_debug.h
deleted file mode 100644
index a03cf621695cd4a7fed8a90bc3f66ecb1f8d81e9..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/fsbl_debug.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**************************************************************
- * (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
- *
- * This file contains confidential and proprietary information
- * of Xilinx, Inc. and is protected under U.S. and
- * international copyright and other intellectual property
- * laws.
- *
- * DISCLAIMER
- * This disclaimer is not a license and does not grant any
- * rights to the materials distributed herewith. Except as
- * otherwise provided in a valid license issued to you by
- * Xilinx, and to the maximum extent permitted by applicable
- * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- * (2) Xilinx shall not be liable (whether in contract or tort,
- * including negligence, or under any other theory of
- * liability) for any loss or damage of any kind or nature
- * related to, arising under or in connection with these
- * materials, including for any direct, or any indirect,
- * special, incidental, or consequential loss or damage
- * (including loss of data, profits, goodwill, or any type of
- * loss or damage suffered as a result of any action brought
- * by a third party) even if such damage or loss was
- * reasonably foreseeable or Xilinx had been advised of the
- * possibility of the same.
- *
- * CRITICAL APPLICATIONS
- * Xilinx products are not designed or intended to be fail-
- * safe, or for use in any application requiring fail-safe
- * performance, such as life-support or safety devices or
- * systems, Class III medical devices, nuclear facilities,
- * applications related to the deployment of airbags, or any
- * other applications that could lead to death, personal
- * injury, or severe property or environmental damage
- * (individually and collectively, "Critical
- * Applications"). Customer assumes the sole risk and
- * liability of any use of Xilinx products in Critical
- * Applications, subject only to applicable laws and
- * regulations governing limitations on product liability.
- *
- * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- * PART OF THIS FILE AT ALL TIMES.
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file fsbl_debug.h
-*
-* This file contains the debug verbose information for FSBL print functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a mb 01/09/12 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef _FSBL_DEBUG_H
-#define _FSBL_DEBUG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#define DEBUG_GENERAL 0x00000001 /* general debug messages */
-#define DEBUG_INFO 0x00000002 /* More debug information */
-
-#if defined (FSBL_DEBUG_INFO)
-#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
-#elif defined (FSBL_DEBUG)
-#define fsbl_dbg_current_types (DEBUG_GENERAL)
-#else
-#define fsbl_dbg_current_types 0
-#endif
-
-#ifdef STDOUT_BASEADDRESS
-#define fsbl_printf(type,...) \
- if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
-#else
-#define fsbl_printf(type, ...)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FSBL_DEBUG_H */
diff --git a/quad/zybo_fsbl/src/fsbl_handoff.S b/quad/zybo_fsbl/src/fsbl_handoff.S
deleted file mode 100644
index 8aa30897745719594c39cea15aebee2e160cceb5..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/fsbl_handoff.S
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file handoff.S
-*
-* Contains the code that does the handoff to the loaded application. This
-* code lives high in the ROM.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date.word Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 03/01/10 Initial release
-*
-* </pre>
-*
-* @note
-* Assumes that the starting address of the FSBL is provided by the calling routine
-* in R0.
-*
-******************************************************************************/
-
-.globl FsblHandoffJtagExit
-
-.globl FsblHandoffExit
-
-.section .handoff,"axS"
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-FsblHandoffJtagExit:
- mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
- mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
-
- dsb
- isb /* make sure it completes */
-
- ldr r4, =0
- mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
-
- isb /* make sure it completes */
-Loop:
- wfe
- b Loop
-
-FsblHandoffExit:
- mov lr, r0 /* move the destination address into link register */
-
- mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
- mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
-
- dsb
- isb /* make sure it completes */
-
- ldr r4, =0
- mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
-
- isb /* make sure it completes */
-
-
- bx lr /* force the switch, destination should have been in r0 */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-.end
diff --git a/quad/zybo_fsbl/src/fsbl_hooks.c b/quad/zybo_fsbl/src/fsbl_hooks.c
deleted file mode 100644
index 7b27a25e79d5c78438b8d5b4e1b09fcbc8eb2a99..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/fsbl_hooks.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-
-/*****************************************************************************
-*
-* @file fsbl_hooks.c
-*
-* This file provides functions that serve as user hooks. The user can add the
-* additional functionality required into these routines. This would help retain
-* the normal FSBL flow unchanged.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a np 08/03/12 Initial release
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-
-#include "fsbl.h"
-#include "xstatus.h"
-#include "fsbl_hooks.h"
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/******************************************************************************
-* This function is the hook which will be called before the bitstream download.
-* The user can add all the customized code required to be executed before the
-* bitstream download to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookBeforeBitstreamDload(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here. Errors to be stored in the status variable
- * and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
-
- return (Status);
-}
-
-/******************************************************************************
-* This function is the hook which will be called after the bitstream download.
-* The user can add all the customized code required to be executed after the
-* bitstream download to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookAfterBitstreamDload(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
-
- return (Status);
-}
-
-/******************************************************************************
-* This function is the hook which will be called before the FSBL does a handoff
-* to the application. The user can add all the customized code required to be
-* executed before the handoff to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookBeforeHandoff(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
-
- return (Status);
-}
-
-
-/******************************************************************************
-* This function is the hook which will be called in case FSBL fall back
-*
-* @param None
-*
-* @return None
-*
-****************************************************************************/
-void FsblHookFallback(void)
-{
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
- while(1);
-}
-
-
diff --git a/quad/zybo_fsbl/src/fsbl_hooks.h b/quad/zybo_fsbl/src/fsbl_hooks.h
deleted file mode 100644
index 6ba5c039fb67ec6696820987f7ad7d87f558deae..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/fsbl_hooks.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file fsbl_hooks.h
-*
-* Contains the function prototypes, defines and macros required by fsbl_hooks.c
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a np/mb 10/08/12 Initial release
-* Corrected the prototype
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef FSBL_HOOKS_H_
-#define FSBL_HOOKS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-
-/************************** Function Prototypes ******************************/
-
-/* FSBL hook function which is called before bitstream download */
-u32 FsblHookBeforeBitstreamDload(void);
-
-/* FSBL hook function which is called after bitstream download */
-u32 FsblHookAfterBitstreamDload(void);
-
-/* FSBL hook function which is called before handoff to the application */
-u32 FsblHookBeforeHandoff(void);
-
-/* FSBL hook function which is called in FSBL fallback */
-void FsblHookFallback(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/quad/zybo_fsbl/src/image_mover.c b/quad/zybo_fsbl/src/image_mover.c
deleted file mode 100644
index 81ab06a5135fffa9f2bcf9117b611c323326f447..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/image_mover.c
+++ /dev/null
@@ -1,1301 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file image_mover.c
-*
-* Move partitions to either DDR to execute or to program FPGA.
-* It performs partition walk.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 05/24/11 Initial release
-* 2.00a jz 06/30/11 Updated partition header defs for 64-byte
-* alignment change in data2mem tool
-* 2.00a mb 05/25/12 Updated for standalone based bsp FSBL
-* Nand/SD encryption and review comments
-* 3.00a np 08/30/12 Added FSBL user hook calls
-* (before and after bitstream download.)
-* 4.00a sgd 02/28/13 Fix for CR#691148
-* Fix for CR#695578
-*
-* 4.00a sgd 04/23/13 Fix for CR#710128
-* 5.00a kc 07/30/13 Fix for CR#724165
-* Fix for CR#724166
-* Fix for CR#732062
-*
-* </pre>
-*
-* @note
-* A partition is either an executable or a bitstream to program FPGA
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "image_mover.h"
-#include "xil_printf.h"
-#include "xreg_cortexa9.h"
-#include "pcap.h"
-#include "fsbl_hooks.h"
-#include "md5.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-#ifdef RSA_SUPPORT
-#include "rsa.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/* We are 32-bit machine */
-#define MAXIMUM_IMAGE_WORD_LEN 0x40000000
-#define MD5_CHECKSUM_SIZE 16
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset);
-u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum);
-u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum);
-
-/************************** Variable Definitions *****************************/
-/*
- * Partition information flags
- */
-u8 EncryptedPartitionFlag;
-u8 PLPartitionFlag;
-u8 PSPartitionFlag;
-u8 SignedPartitionFlag;
-u8 PartitionChecksumFlag;
-u8 BitstreamFlag;
-u8 ApplicationFlag;
-
-u32 ExecutionAddress;
-ImageMoverType MoveImage;
-
-/*
- * Header array
- */
-PartHeader PartitionHeader[MAX_PARTITION_NUMBER];
-u32 PartitionCount;
-u32 FsblLength;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-extern u32 Silicon_Version;
-extern u32 FlashReadBaseAddress;
-extern u8 LinearBootDeviceFlag;
-extern XDcfg *DcfgInstPtr;
-
-/*****************************************************************************/
-/**
-*
-* This function
-*
-* @param
-*
-* @return
-*
-*
-* @note None
-*
-****************************************************************************/
-u32 LoadBootImage(void)
-{
- u32 RebootStatusRegister = 0;
- u32 MultiBootReg = 0;
- u32 ImageStartAddress = 0;
- u32 PartitionNum;
- u32 PartitionDataLength;
- u32 PartitionImageLength;
- u32 PartitionTotalSize;
- u32 PartitionExecAddr;
- u32 PartitionAttr;
- u32 ExecAddress = 0;
- u32 PartitionLoadAddr;
- u32 PartitionStartAddr;
- u32 PartitionChecksumOffset;
- u8 ExecAddrFlag = 0 ;
- u32 Status;
- PartHeader *HeaderPtr;
- u32 EfuseStatusRegValue;
-#ifdef RSA_SUPPORT
- u32 HeaderSize;
-#endif
- /*
- * Resetting the Flags
- */
- BitstreamFlag = 0;
- ApplicationFlag = 0;
-
- RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
- fsbl_printf(DEBUG_INFO,
- "Reboot status register: 0x%08x\r\n",RebootStatusRegister);
-
- if (Silicon_Version == SILICON_VERSION_1) {
- /*
- * Clear out fallback mask from previous run
- * We start from the first partition again
- */
- if ((RebootStatusRegister & FSBL_FAIL_MASK) ==
- FSBL_FAIL_MASK) {
- fsbl_printf(DEBUG_INFO,
- "Reboot status shows previous run falls back\r\n");
- RebootStatusRegister &= ~(FSBL_FAIL_MASK);
- Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister);
- }
-
- /*
- * Read the image start address
- */
- ImageStartAddress = *(u32 *)BASEADDR_HOLDER;
- } else {
- /*
- * read the multiboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08x\r\n",MultiBootReg);
-
- /*
- * Compute the image start address
- */
- ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
- }
-
- fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08x\r\n",ImageStartAddress);
-
- /*
- * Get partitions header information
- */
- Status = GetPartitionHeaderInfo(ImageStartAddress);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
-
- /*
- * RSA is not implemented in 1.0 and 2.0
- * silicon
- */
- if ((Silicon_Version != SILICON_VERSION_1) &&
- (Silicon_Version != SILICON_VERSION_2)) {
- /*
- * Read Efuse Status Register
- */
- EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG);
- if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) {
- fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n");
-#ifdef RSA_SUPPORT
- /*
- * Set the Ppk
- */
- SetPpk();
-
- /*
- * Read partition header with signature
- */
- Status = GetImageHeaderAndSignature(ImageStartAddress,
- (u32 *)DDR_TEMP_START_ADDR);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,
- "Read Partition Header signature Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
- HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE;
-
- Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,
- "Partition Header signature Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
-#else
- /*
- * In case user not enabled RSA authentication feature
- */
- fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
- OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
- FsblFallback();
-#endif
- }
- }
-
-#ifdef MMC_SUPPORT
- /*
- * In case of MMC support
- * boot image preset in MMC will not have FSBL partition
- */
- PartitionNum = 0;
-#else
- /*
- * First partition header was ignored by FSBL
- * As it contain FSBL partition information
- */
- PartitionNum = 1;
-#endif
-
- while (PartitionNum < PartitionCount) {
-
- fsbl_printf(DEBUG_INFO, "Partition Number: %d\r\n", PartitionNum);
-
- HeaderPtr = &PartitionHeader[PartitionNum];
-
- /*
- * Print partition header information
- */
- HeaderDump(HeaderPtr);
-
- /*
- * Validate partition header
- */
- Status = ValidateHeader(HeaderPtr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n");
- OutputStatus(INVALID_HEADER_FAIL);
- FsblFallback();
- }
-
- /*
- * Load partition header information in to local variables
- */
- PartitionDataLength = HeaderPtr->DataWordLen;
- PartitionImageLength = HeaderPtr->ImageWordLen;
- PartitionExecAddr = HeaderPtr->ExecAddr;
- PartitionAttr = HeaderPtr->PartitionAttr;
- PartitionLoadAddr = HeaderPtr->LoadAddr;
- PartitionChecksumOffset = HeaderPtr->CheckSumOffset;
- PartitionStartAddr = HeaderPtr->PartitionStart;
- PartitionTotalSize = HeaderPtr->PartitionWordLen;
-
-
- if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) {
- fsbl_printf(DEBUG_INFO, "Bitstream\r\n");
- PLPartitionFlag = 1;
- PSPartitionFlag = 0;
- BitstreamFlag = 1;
- if (ApplicationFlag == 1) {
-#ifdef STDOUT_BASEADDRESS
- xil_printf("\r\nFSBL Warning !!!"
- "Bitstream not loaded into PL\r\n");
- xil_printf("Partition order invalid\r\n");
-#endif
- break;
- }
- }
-
- if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) {
- fsbl_printf(DEBUG_INFO, "Application\r\n");
- PSPartitionFlag = 1;
- PLPartitionFlag = 0;
- ApplicationFlag = 1;
- }
-
- /*
- * Encrypted partition will have different value
- * for Image length and data length
- */
- if (PartitionDataLength != PartitionImageLength) {
- fsbl_printf(DEBUG_INFO, "Encrypted\r\n");
- EncryptedPartitionFlag = 1;
- } else {
- EncryptedPartitionFlag = 0;
- }
-
- /*
- * Check for partition checksum check
- */
- if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) {
- PartitionChecksumFlag = 1;
- } else {
- PartitionChecksumFlag = 0;
- }
-
- /*
- * RSA signature check
- */
- if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) {
- fsbl_printf(DEBUG_INFO, "RSA Signed\r\n");
- SignedPartitionFlag = 1;
- } else {
- SignedPartitionFlag = 0;
- }
-
- /*
- * Load address check
- * Loop will break when PS load address zero and partition is
- * un-signed or un-encrypted
- */
- if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) {
- if ((PartitionLoadAddr == 0) &&
- (!((SignedPartitionFlag == 1) ||
- (EncryptedPartitionFlag == 1)))) {
- break;
- } else {
- fsbl_printf(DEBUG_GENERAL,
- "INVALID_LOAD_ADDRESS_FAIL\r\n");
- OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
- FsblFallback();
- }
- }
-
- if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) {
- fsbl_printf(DEBUG_GENERAL,
- "INVALID_LOAD_ADDRESS_FAIL\r\n");
- OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
- FsblFallback();
- }
-
- /*
- * Load execution address of first PS partition
- */
- if (PSPartitionFlag && (!ExecAddrFlag)) {
- ExecAddrFlag++;
- ExecAddress = PartitionExecAddr;
- }
-
- /*
- * FSBL user hook call before bitstream download
- */
- if (PLPartitionFlag) {
- Status = FsblHookBeforeBitstreamDload();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n");
- OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL);
- FsblFallback();
- }
- }
-
- /*
- * Move partitions from boot device
- */
- Status = PartitionMove(ImageStartAddress, HeaderPtr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n");
- OutputStatus(PARTITION_MOVE_FAIL);
- FsblFallback();
- }
-
- if ((SignedPartitionFlag) || (PartitionChecksumFlag)) {
- if(PLPartitionFlag) {
- /*
- * PL partition loaded in to DDR temporary address
- * for authentication and checksum verification
- */
- PartitionStartAddr = DDR_TEMP_START_ADDR;
- } else {
- PartitionStartAddr = PartitionLoadAddr;
- }
-
- if (PartitionChecksumFlag) {
- /*
- * Validate the partition data with checksum
- */
- Status = ValidateParition(PartitionStartAddr,
- (PartitionTotalSize << WORD_LENGTH_SHIFT),
- (PartitionChecksumOffset << WORD_LENGTH_SHIFT));
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n");
- OutputStatus(PARTITION_CHECKSUM_FAIL);
- FsblFallback();
- }
-
- fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n");
- }
-
- /*
- * Authentication Partition
- */
- if (SignedPartitionFlag == 1 ) {
-#ifdef RSA_SUPPORT
- Status = AuthenticatePartition((u8*)PartitionStartAddr,
- (PartitionTotalSize << WORD_LENGTH_SHIFT));
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n");
- OutputStatus(AUTHENTICATION_FAIL);
- FsblFallback();
- }
- fsbl_printf(DEBUG_INFO,"Authentication Done\r\n");
-#else
- /*
- * In case user not enabled RSA authentication feature
- */
- fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
- OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
- FsblFallback();
-#endif
- }
-
- /*
- * Decrypt PS partition
- */
- if (EncryptedPartitionFlag && PSPartitionFlag) {
- Status = DecryptPartition(PartitionStartAddr,
- PartitionDataLength,
- PartitionImageLength);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n");
- OutputStatus(DECRYPTION_FAIL);
- FsblFallback();
- }
- }
-
- /*
- * Load Signed PL partition in Fabric
- */
- if (PLPartitionFlag) {
- Status = PcapLoadPartition((u32*)PartitionStartAddr,
- (u32*)PartitionLoadAddr,
- PartitionImageLength,
- PartitionDataLength,
- EncryptedPartitionFlag);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n");
- OutputStatus(BITSTREAM_DOWNLOAD_FAIL);
- FsblFallback();
- }
- }
- }
-
-
- /*
- * FSBL user hook call after bitstream download
- */
- if (PLPartitionFlag) {
- Status = FsblHookAfterBitstreamDload();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n");
- OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL);
- FsblFallback();
- }
- }
- /*
- * Increment partition number
- */
- PartitionNum++;
- }
-
- return ExecAddress;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function loads all partition header information in global array
-*
-* @param ImageAddress is the start address of the image
-*
-* @return - XST_SUCCESS if Get partition Header information successful
-* - XST_FAILURE if Get Partition Header information failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
-{
- u32 PartitionHeaderOffset;
- u32 Status;
-
-
- /*
- * Get the length of the FSBL from BootHeader
- */
- Status = GetFsblLength(ImageBaseAddress, &FsblLength);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Get the start address of the partition header table
- */
- Status = GetPartitionHeaderStartAddr(ImageBaseAddress,
- &PartitionHeaderOffset);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Header offset on flash
- */
- PartitionHeaderOffset += ImageBaseAddress;
-
- fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08x\r\n",
- PartitionHeaderOffset);
-
- /*
- * Load all partitions header data in to global variable
- */
- Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset,
- &PartitionHeader[0]);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Get partitions count from partitions header information
- */
- PartitionCount = GetPartitionCount(&PartitionHeader[0]);
-
- fsbl_printf(DEBUG_INFO, "Partition Count: %d\r\n", PartitionCount);
-
- /*
- * Partition Count check
- */
- if (PartitionCount >= MAX_PARTITION_NUMBER) {
- fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n");
- return XST_FAILURE;
-
- } else if (PartitionCount <= 1) {
- fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function goes to the partition header of the specified partition
-*
-* @param ImageAddress is the start address of the image
-*
-* @return Offset Partition header address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function goes to the partition header of the specified partition
-*
-* @param ImageAddress is the start address of the image
-*
-* @return Offset to Image header table address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-/*****************************************************************************/
-/**
-*
-* This function gets the length of the FSBL
-*
-* @param ImageAddress is the start address of the image
-*
-* @return FsblLength is the length of the fsbl
-*
-* @return - XST_SUCCESS if fsbl length reading is successful
-* - XST_FAILURE if fsbl length reading failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET,
- (u32)FsblLength, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-#ifdef RSA_SUPPORT
-/*****************************************************************************/
-/**
-*
-* This function goes to read the image headers and its signature. Image
-* header consists of image header table, image headers, partition
-* headers
-*
-* @param ImageBaseAddress is the start address of the image header
-*
-* @return Offset Partition header address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset)
-{
- u32 Status;
- u32 ImageHeaderOffset;
-
- /*
- * Get the start address of the partition header table
- */
- Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset,
- TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
-/*****************************************************************************/
-/**
-*
-* This function get the header information of the all the partitions and load into
-* global array
-*
-* @param PartHeaderOffset Offset address where the header information present
-*
-* @param Header Partition header pointer
-*
-* @return - XST_SUCCESS if Load Partitions Header information successful
-* - XST_FAILURE if Load Partitions Header information failed
-*
-* @note None
-*
-****************************************************************************/
-u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header)
-{
- u32 Status;
-
- Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function dumps the partition header.
-*
-* @param Header Partition header pointer
-*
-* @return None
-*
-* @note None
-*
-******************************************************************************/
-void HeaderDump(PartHeader *Header)
-{
- fsbl_printf(DEBUG_INFO, "Header Dump\r\n");
- fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08x\r\n",
- Header->ImageWordLen);
- fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08x\r\n",
- Header->DataWordLen);
- fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08x\r\n",
- Header->PartitionWordLen);
- fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08x\r\n",
- Header->LoadAddr);
- fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08x\r\n",
- Header->ExecAddr);
- fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08x\r\n",
- Header->PartitionStart);
- fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08x\r\n",
- Header->PartitionAttr);
- fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08x\r\n",
- Header->CheckSumOffset);
- fsbl_printf(DEBUG_INFO, "Section Count: 0x%08x\r\n",
- Header->SectionCount);
- fsbl_printf(DEBUG_INFO, "Checksum: 0x%08x\r\n",
- Header->CheckSum);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function calculates the partitions count from header information
-*
-* @param Header Partition header pointer
-*
-* @return Count Partition count
-*
-* @note None
-*
-*******************************************************************************/
-u32 GetPartitionCount(PartHeader *Header)
-{
- u32 Count=0;
- struct HeaderArray *Hap;
-
- for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) {
- Hap = (struct HeaderArray *)&Header[Count];
- if(IsLastPartition(Hap)!=XST_FAILURE)
- break;
- }
-
- return Count;
-}
-
-/******************************************************************************/
-/**
-* This function check whether the current partition is the end of partitions
-*
-* The partition is the end of the partitions if it looks like this:
-* 0x00000000
-* 0x00000000
-* ....
-* 0x00000000
-* 0x00000000
-* 0xFFFFFFFF
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS if it is the last partition
-* - XST_FAILURE if it is not last partition
-*
-****************************************************************************/
-u32 IsLastPartition(struct HeaderArray *H)
-{
- int Index;
-
- if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) {
- return XST_FAILURE;
- }
-
- for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) {
-
- if (H->Fields[Index] != 0x0) {
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function validates the partition header.
-*
-* @param Header Partition header pointer
-*
-* @return
-* - XST_FAILURE if bad header.
-* - XST_SUCCESS if successful.
-*
-* @note None
-*
-*******************************************************************************/
-u32 ValidateHeader(PartHeader *Header)
-{
- struct HeaderArray *Hap;
-
- Hap = (struct HeaderArray *)Header;
-
- /*
- * If there are no partitions to load, fail
- */
- if (IsEmptyHeader(Hap) == XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Validate partition header checksum
- */
- if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Validate partition data size
- */
- if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) {
- fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-* This function check whether the current partition header is empty.
-* A partition header is considered empty if image word length is 0 and the
-* last word is 0.
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS , If the partition header is empty
-* - XST_FAILURE , If the partition header is NOT empty
-*
-* @note Caller is responsible to make sure the address is valid.
-*
-*
-****************************************************************************/
-u32 IsEmptyHeader(struct HeaderArray *H)
-{
- int Index;
-
- for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) {
- if (H->Fields[Index] != 0x0) {
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function checks the header checksum If the header checksum is not valid
-* XST_FAILURE is returned.
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS is header checksum is ok
-* - XST_FAILURE if the header checksum is not correct
-*
-* @note None.
-*
-****************************************************************************/
-u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H)
-{
- u32 Checksum;
- u32 Count;
-
- Checksum = 0;
-
- for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) {
- /*
- * Read the word from the header
- */
- Checksum += H->Fields[Count];
- }
-
- /*
- * Invert checksum, last bit of error checking
- */
- Checksum ^= 0xFFFFFFFF;
-
- /*
- * Validate the checksum
- */
- if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) {
- fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8x != 0x%8.8x\r\n",
- Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function load the partition from boot device
-*
-* @param ImageBaseAddress Base address on flash
-* @param Header Partition header pointer
-*
-* @return
-* - XST_SUCCESS if partition move successful
-* - XST_FAILURE if check failed move failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header)
-{
- u32 SourceAddr;
- u32 Status;
- u8 SecureTransferFlag = 0;
- u32 LoadAddr;
- u32 ImageWordLen;
- u32 DataWordLen;
-
- SourceAddr = ImageBaseAddress;
- SourceAddr += Header->PartitionStart<<WORD_LENGTH_SHIFT;
- LoadAddr = Header->LoadAddr;
- ImageWordLen = Header->ImageWordLen;
- DataWordLen = Header->DataWordLen;
-
- /*
- * Add flash base address for linear boot devices
- */
- if (LinearBootDeviceFlag) {
- SourceAddr += FlashReadBaseAddress;
- }
-
- /*
- * Partition encrypted
- */
- if(EncryptedPartitionFlag) {
- SecureTransferFlag = 1;
- }
-
- /*
- * For Signed partition, Total partition image need to copied to DDR
- */
- if (SignedPartitionFlag) {
- ImageWordLen = Header->PartitionWordLen;
- DataWordLen = Header->PartitionWordLen;
- }
-
- /*
- * Encrypted and Signed PS partition need to be loaded on to DDR
- * without decryption
- */
- if (PSPartitionFlag &&
- (SignedPartitionFlag || PartitionChecksumFlag) &&
- EncryptedPartitionFlag) {
- SecureTransferFlag = 0;
- }
-
- /*
- * CPU is used for data transfer in case of non-linear
- * boot device
- */
- if (!LinearBootDeviceFlag) {
- /*
- * PL partition copied to DDR temporary location
- */
- if (PLPartitionFlag) {
- LoadAddr = DDR_TEMP_START_ADDR;
- }
-
- Status = MoveImage(SourceAddr,
- LoadAddr,
- (ImageWordLen << WORD_LENGTH_SHIFT));
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * As image present at load address
- */
- SourceAddr = LoadAddr;
- }
-
- if ((LinearBootDeviceFlag && PLPartitionFlag &&
- (SignedPartitionFlag || PartitionChecksumFlag)) ||
- (LinearBootDeviceFlag && PSPartitionFlag) ||
- ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) {
- /*
- * PL signed partition copied to DDR temporary location
- * using non-secure PCAP for linear boot device
- */
- if(PLPartitionFlag){
- SecureTransferFlag = 0;
- LoadAddr = DDR_TEMP_START_ADDR;
- }
-
- /*
- * Data transfer using PCAP
- */
- Status = PcapDataTransfer((u32*)SourceAddr,
- (u32*)LoadAddr,
- ImageWordLen,
- DataWordLen,
- SecureTransferFlag);
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * As image present at load address
- */
- SourceAddr = LoadAddr;
- }
-
- /*
- * Load Bitstream partition in to fabric only
- * if checksum and authentication bits are not set
- */
- if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) {
- Status = PcapLoadPartition((u32*)SourceAddr,
- (u32*)Header->LoadAddr,
- Header->ImageWordLen,
- Header->DataWordLen,
- EncryptedPartitionFlag);
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n");
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function load the decrypts partition
-*
-* @param StartAddr Source start address
-* @param DataLength Data length in words
-* @param ImageLength Image length in words
-*
-* @return
-* - XST_SUCCESS if decryption successful
-* - XST_FAILURE if decryption failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength)
-{
- u32 Status;
- u8 SecureTransferFlag =1;
-
- /*
- * Data transfer using PCAP
- */
- Status = PcapDataTransfer((u32*)StartAddr,
- (u32*)StartAddr,
- ImageLength,
- DataLength,
- SecureTransferFlag);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Validate Partition Data by using checksum preset in image
-*
-* @param Partition header pointer
-* @param Partition check sum offset
-* @return
-* - XST_SUCCESS if partition data is ok
-* - XST_FAILURE if partition data is corrupted
-*
-* @note None
-*
-*******************************************************************************/
-u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset)
-{
- u8 Checksum[MD5_CHECKSUM_SIZE];
- u8 CalcChecksum[MD5_CHECKSUM_SIZE];
- u32 Status;
- u32 Index;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * Get checksum from flash
- */
- Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO, "Actual checksum\r\n");
-
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]);
- }
-
- fsbl_printf(DEBUG_INFO, "\r\n");
-
- /*
- * Calculate checksum for the partition
- */
- Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n");
-
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]);
- }
-
- fsbl_printf(DEBUG_INFO, "\r\n");
-
- /*
- * Compare actual checksum with the calculated checksum
- */
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- if(Checksum[Index] != CalcChecksum[Index]) {
- fsbl_printf(DEBUG_GENERAL, "Error: "
- "Partition DataChecksum 0x%0x!= 0x%0x\r\n",
- Checksum[Index], CalcChecksum[Index]);
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function gets partition checksum from flash
-*
-* @param Check sum offset
-* @param Checksum pointer
-* @return
-* - XST_SUCCESS if checksum read success
-* - XST_FAILURE if unable get checksum
-*
-* @note None
-*
-*******************************************************************************/
-u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum)
-{
- u32 Status;
-
- Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function calculates the checksum preset in image
-*
-* @param Start address
-* @param Length of the data
-* @param Checksum pointer
-*
-* @return
-* - XST_SUCCESS if Checksum calculate successful
-* - XST_FAILURE if Checksum calculate failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum)
-{
- /*
- * Calculate checksum using MD5 algorithm
- */
- md5((u8*)SourceAddr, DataLength, Checksum, 0 );
-
- return XST_SUCCESS;
-}
-
diff --git a/quad/zybo_fsbl/src/image_mover.h b/quad/zybo_fsbl/src/image_mover.h
deleted file mode 100644
index e74d0bebc73914649fe4215781373086dfe4059c..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/image_mover.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file image_mover.h
-*
-* This file contains the interface for moving the image from FLASH to OCM
-
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 03/04/11 Initial release
-* 2.00a jz 06/04/11 partition header expands to 12 words
-* 5.00a kc 07/30/13 Added defines for image header information
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___IMAGE_MOVER_H___
-#define ___IMAGE_MOVER_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define PARTITION_NUMBER_SHIFT 24
-#define MAX_PARTITION_NUMBER (0xE)
-
-/* Boot Image Header defines */
-#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
-#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
-#define IMAGE_HEADER_SIZE (64)
-#define IMAGE_HEADER_TABLE_SIZE (64)
-#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
-#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
-#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
- TOTAL_IMAGE_HEADER_SIZE + \
- TOTAL_PARTITION_HEADER_SIZE + 64)
-
-/* Partition Header defines */
-#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
-#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
-#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
-#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
-#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
-#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
-#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
-#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
-#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
-#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
-#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
-
-/* Attribute word defines */
-#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
-#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
-#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
-#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
-#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
-
-
-/**************************** Type Definitions *******************************/
-typedef u32 (*ImageMoverType)( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-typedef struct StructPartHeader {
- u32 ImageWordLen; /* 0x0 */
- u32 DataWordLen; /* 0x4 */
- u32 PartitionWordLen; /* 0x8 */
- u32 LoadAddr; /* 0xC */
- u32 ExecAddr; /* 0x10 */
- u32 PartitionStart; /* 0x14 */
- u32 PartitionAttr; /* 0x18 */
- u32 SectionCount; /* 0x1C */
- u32 CheckSumOffset; /* 0x20 */
- u32 Pads1[1];
- u32 ACOffset; /* 0x28 */
- u32 Pads2[4];
- u32 CheckSum; /* 0x3C */
-}PartHeader;
-
-struct HeaderArray {
- u32 Fields[16];
-};
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define MoverIn32 Xil_In32
-#define MoverOut32 Xil_Out32
-
-/************************** Function Prototypes ******************************/
-u32 LoadBootImage(void);
-u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
-u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
-u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
-u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
-u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset);
-u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
-u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
-u32 IsEmptyHeader(struct HeaderArray *H);
-u32 IsLastPartition(struct HeaderArray *H);
-void HeaderDump(PartHeader *Header);
-u32 GetPartitionCount(PartHeader *Header);
-u32 ValidateHeader(PartHeader *Header);
-u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___IMAGE_MOVER_H___ */
-
-
-
-
diff --git a/quad/zybo_fsbl/src/integer.h b/quad/zybo_fsbl/src/integer.h
deleted file mode 100644
index 75f5709a3873ba02f6928f1fc612d2f62d7aa028..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/integer.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*-------------------------------------------*/
-/* Integer type definitions for FatFs module */
-/*-------------------------------------------*/
-
-#ifndef _INTEGER
-#define _INTEGER
-
-#ifdef _WIN32 /* FatFs development platform */
-
-#include <tchar.h>
-
-#else /* Embedded platform */
-
-/* These types must be 16-bit, 32-bit or larger integer */
-typedef int INT;
-typedef unsigned int UINT;
-
-/* These types must be 8-bit integer */
-typedef char CHAR;
-typedef unsigned char UCHAR;
-typedef unsigned char BYTE;
-
-/* These types must be 16-bit integer */
-typedef short SHORT;
-typedef unsigned short USHORT;
-typedef unsigned short WORD;
-typedef unsigned short WCHAR;
-
-/* These types must be 32-bit integer */
-typedef long LONG;
-typedef unsigned long ULONG;
-typedef unsigned long DWORD;
-
-#endif
-
-#endif
diff --git a/quad/zybo_fsbl/src/librsa.a b/quad/zybo_fsbl/src/librsa.a
deleted file mode 100644
index cdf35a3f339c3d48fe2c67eea6e13806618178a2..0000000000000000000000000000000000000000
Binary files a/quad/zybo_fsbl/src/librsa.a and /dev/null differ
diff --git a/quad/zybo_fsbl/src/lscript.ld b/quad/zybo_fsbl/src/lscript.ld
deleted file mode 100644
index d86df11b1e9cc1e5f3a74586509fdd18dfbda07b..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/lscript.ld
+++ /dev/null
@@ -1,287 +0,0 @@
-/*******************************************************************/
-/* */
-/* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved */
-/* */
-/* Description : FSBL Linker Script */
-/* */
-/*******************************************************************/
-
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
-
-_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
-
-_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
-_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
-_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
-_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
-
-/* Define Memories in the system */
-
-MEMORY
-{
- ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
- ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
-}
-
-/* Specify the default entry point to the program */
-
-ENTRY(_vector_table)
-
-
-SECTIONS
-{
-.text : {
- *(.vectors)
- *(.boot)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
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- KEEP (*(.fini_array))
- __fini_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rsa_ac : {
- . = ALIGN(64);
- __rsa_ac_start = .;
- . += _RSA_AC_SIZE;
- __rsa_ac_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ARM.attributes : {
- __ARM.attributes_start = .;
- *(.ARM.attributes)
- __ARM.attributes_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sdata : {
- __sdata_start = .;
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- __sdata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sbss (NOLOAD) : {
- __sbss_start = .;
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- __sbss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.tdata : {
- __tdata_start = .;
- *(.tdata)
- *(.tdata.*)
- *(.gnu.linkonce.td.*)
- __tdata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.tbss : {
- __tbss_start = .;
- *(.tbss)
- *(.tbss.*)
- *(.gnu.linkonce.tb.*)
- __tbss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.bss (NOLOAD) : {
- __bss_start = .;
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- __bss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
-
-_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
-
-/* Generate Stack and Heap definitions */
-
-.heap (NOLOAD) : {
- . = ALIGN(16);
- _heap = .;
- HeapBase = .;
- _heap_start = .;
- . += _HEAP_SIZE;
- _heap_end = .;
- HeapLimit = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.stack (NOLOAD) : {
- . = ALIGN(16);
- _stack_end = .;
- . += _STACK_SIZE;
- _stack = .;
- __stack = _stack;
- . = ALIGN(16);
- _irq_stack_end = .;
- . += _STACK_SIZE;
- __irq_stack = .;
- _supervisor_stack_end = .;
- . += _SUPERVISOR_STACK_SIZE;
- . = ALIGN(16);
- __supervisor_stack = .;
- _abort_stack_end = .;
- . += _ABORT_STACK_SIZE;
- . = ALIGN(16);
- __abort_stack = .;
- _fiq_stack_end = .;
- . += _FIQ_STACK_SIZE;
- . = ALIGN(16);
- __fiq_stack = .;
- _undef_stack_end = .;
- . += _UNDEF_STACK_SIZE;
- . = ALIGN(16);
- __undef_stack = .;
-} > ps7_ram_1_S_AXI_BASEADDR
-
-_end = .;
-}
-
diff --git a/quad/zybo_fsbl/src/main.c b/quad/zybo_fsbl/src/main.c
deleted file mode 100644
index aff88aebf52fe41d711a91aee3bf4785050bb1ba..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/main.c
+++ /dev/null
@@ -1,1516 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file main.c
-*
-* The main file for the First Stage Boot Loader (FSBL).
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 06/04/11 Initial release
-* 2.00a mb 25/05/12 standalone based FSBL
-* 3.00a np/mb 08/03/12 Added call to FSBL user hook - before handoff.
-* DDR ECC initialization added
-* fsbl print with verbose added
-* Performance measurement added
-* Flushed the UART Tx buffer
-* Added the performance time for ECC DDR init
-* Added clearing of ECC Error Code
-* Added the watchdog timer value
-* 4.00a sgd 02/28/13 Code Cleanup
-* Fix for CR#681014 - ECC init in FSBL should not
-* call fabric_init()
-* Fix for CR#689077 - FSBL hangs at Handoff clearing the
-* TX UART buffer when using UART0
-* instead of UART1
-* Fix for CR#694038 - FSBL debug logs always prints 14.3
-* as the Revision number - this is
-* incorrect
-* Fix for CR#694039 - FSBL prints "unsupported silicon
-* version for v3.0" 3.0 Silicon
-* Fix for CR#699475 - FSBL functionality is broken and
-* its not able to boot in QSPI/NAND
-* bootmode
-* Removed DDR initialization check
-* Removed DDR ECC initialization code
-* Modified hand off address check to 1MB
-* Added RSA authentication support
-* Watchdog disabled for AES E-Fuse encryption
-* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
-* Fix for CR#708728 - Issues seen while making HP
-* interconnect 32 bit wide
-* 6.00a kc 07/30/13 Fix for CR#708316 - PS7_init.tcl file should have
-* Error mechanism for all mask_poll
-* Fix for CR#691150 - ps7_init does not check for
-* peripheral initialization failures
-* or timeout on polls
-* Fix for CR#724165 - Partition Header used by FSBL is
-* not authenticated
-* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
-* by Boot ROM for authenticating
-* the Partition images
-* Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* Fix for CR#732865 - Backward compatibility for ps7_init
-* function
-* </pre>
-*
-* @note
-* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy
-* the partitions from the flash device. If the partition is bitstream then
-* the bitstream is programmed in the Fabric and for an partition that is
-* an application , FSBL will copy the application into DDR and does a
-* handoff.The application should not be starting at the OCM address,
-* FSBL does not remap the DDR. Application should use DDR starting from 1MB
-*
-* FSBL can be stitched along with bitstream and application using bootgen
-*
-* Refer to fsbl.h file for details on the compilation flags supported in FSBL
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "fsbl.h"
-#include "qspi.h"
-#include "nand.h"
-#include "nor.h"
-#include "sd.h"
-#include "pcap.h"
-#include "image_mover.h"
-#include "xparameters.h"
-#include "xil_cache.h"
-#include "xil_exception.h"
-#include "xstatus.h"
-#include "fsbl_hooks.h"
-#include "xtime_l.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-#ifdef STDOUT_BASEADDRESS
-#include "xuartps_hw.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID
-#define WDT_EXPIRE_TIME 100
-#define WDT_CRV_SHIFT 12
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-/************************** Function Prototypes ******************************/
-extern int ps7_init();
-extern char* getPS7MessageInfo(unsigned key);
-#ifdef PS7_POST_CONFIG
-extern int ps7_post_config();
-#endif
-#ifdef PEEP_CODE
-extern void init_ddr(void);
-#endif
-
-static void Update_MultiBootRegister(void);
-/* Exception handlers */
-static void RegisterHandlers(void);
-static void Undef_Handler (void);
-static void SVC_Handler (void);
-static void PreFetch_Abort_Handler (void);
-static void Data_Abort_Handler (void);
-static void IRQ_Handler (void);
-static void FIQ_Handler (void);
-
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-int InitWatchDog(void);
-u32 ConvertTime_WdtCounter(u32 seconds);
-void CheckWDTReset(void);
-#endif
-
-u32 NextValidImageCheck(void);
-
-u32 DDRInitCheck(void);
-
-/************************** Variable Definitions *****************************/
-/*
- * Base Address for the Read Functionality for Image Processing
- */
-u32 FlashReadBaseAddress = 0;
-/*
- * Silicon Version
- */
-u32 Silicon_Version;
-
-/*
- * Boot Device flag
- */
-u8 LinearBootDeviceFlag;
-
-u32 PcapCtrlRegVal;
-
-u8 SystemInitFlag;
-
-extern ImageMoverType MoveImage;
-extern XDcfg *DcfgInstPtr;
-extern u8 BitstreamFlag;
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-extern u32 QspiFlashSize;
-#endif
-/*****************************************************************************/
-/**
-*
-* This is the main function for the FSBL ROM code.
-*
-*
-* @param None.
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-* @note
-*
-****************************************************************************/
-int main(void)
-{
- u32 BootModeRegister = 0;
- u32 HandoffAddress = 0;
- u32 Status = XST_SUCCESS;
-
-#ifdef PEEP_CODE
- /*
- * PEEP DDR initialization
- */
- init_ddr();
-#else
- /*
- * PCW initialization for MIO,PLL,CLK and DDR
- */
- Status = ps7_init();
- if (Status != FSBL_PS7_INIT_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n",
- getPS7MessageInfo(Status));
- OutputStatus(PS7_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-#endif
-
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-
- /* If Performance measurement is required
- * then read the Global Timer value , Please note that the
- * time taken for mio, clock and ddr initialisation
- * done in the ps7_init function is not accounted in the FSBL
- *
- */
-#ifdef FSBL_PERF
- XTime tCur = 0;
- FsblGetGlobalTime(tCur);
-#endif
-
- /*
- * Flush the Caches
- */
- Xil_DCacheFlush();
-
- /*
- * Disable Data Cache
- */
- Xil_DCacheDisable();
-
- /*
- * Register the Exception handlers
- */
- RegisterHandlers();
-
- /*
- * Print the FSBL Banner
- */
- fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r");
- fsbl_printf(DEBUG_GENERAL,"Release %d.%d/%d.%d %s-%s\r\n",
- SDK_RELEASE_VER, SDK_SUB_VER,
- SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER,
- __DATE__,__TIME__);
-
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-
- /*
- * DDR Read/write test
- */
- Status = DDRInitCheck();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n");
- /* Error Handling here */
- OutputStatus(DDR_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
-
- /*
- * PCAP initialization
- */
- Status = InitPcap();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r");
- OutputStatus(PCAP_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
- fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n");
-
- /*
- * Get the Silicon Version
- */
- GetSiliconVersion();
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Check if WDT Reset has occurred or not
- */
- CheckWDTReset();
-
- /*
- * Initialize the Watchdog Timer so that it is ready to use
- */
- Status = InitWatchDog();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r");
- OutputStatus(WDT_INIT_FAIL);
- FsblFallback();
- }
- fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n");
-#endif
-
- /*
- * Get PCAP controller settings
- */
- PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK) {
- /*
- * For E-Fuse AES encryption Watch dog Timer disabled and
- * User not allowed to do system reset
- */
-#ifdef XPAR_XWDTPS_0_BASEADDR
- fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n");
- XWdtPs_Stop(&Watchdog);
-#endif
- fsbl_printf(DEBUG_INFO,"User not allowed to do "
- "any system resets\r\n");
- }
-
- /*
- * Store FSBL run state in Reboot Status Register
- */
- MarkFSBLIn();
-
- /*
- * Read bootmode register
- */
- BootModeRegister = Xil_In32(BOOT_MODE_REG);
- BootModeRegister &= BOOT_MODES_MASK;
-
- /*
- * QSPI BOOT MODE
- */
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-
-#ifdef MMC_SUPPORT
- /*
- * To support MMC boot
- * QSPI boot mode detection ignored
- */
- if (BootModeRegister == QSPI_MODE) {
- BootModeRegister = MMC_MODE;
- }
-#endif
-
- if (BootModeRegister == QSPI_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r");
- InitQspi();
- MoveImage = QspiAccess;
- fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n");
- } else
-#endif
-
- /*
- * NAND BOOT MODE
- */
-#ifdef XPAR_PS7_NAND_0_BASEADDR
- if (BootModeRegister == NAND_FLASH_MODE) {
- /*
- * Boot ROM always initialize the nand at lower speed
- * This is the chance to put it to an optimum speed for your nand
- * device
- */
- fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n");
-
- Status = InitNand();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n");
- /*
- * Error Handling here
- */
- OutputStatus(NAND_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = NandAccess;
- fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n");
- } else
-#endif
-
- /*
- * NOR BOOT MODE
- */
- if (BootModeRegister == NOR_FLASH_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r");
- /*
- * Boot ROM always initialize the nor at lower speed
- * This is the chance to put it to an optimum speed for your nor
- * device
- */
- InitNor();
- fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n");
- MoveImage = NorAccess;
- } else
-
- /*
- * SD BOOT MODE
- */
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-
- if (BootModeRegister == SD_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n");
-
- /*
- * SD initialization returns file open error or success
- */
- Status = InitSD("BOOT.BIN");
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n");
- OutputStatus(SD_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = SDAccess;
- fsbl_printf(DEBUG_INFO,"SD Init Done \r\n");
- } else
-
- if (BootModeRegister == MMC_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n");
-
- /*
- * MMC initialization returns file open error or success
- */
- Status = InitSD("BOOT.BIN");
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n");
- OutputStatus(SD_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = SDAccess;
- fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n");
- } else
-
-#endif
-
- /*
- * JTAG BOOT MODE
- */
- if (BootModeRegister == JTAG_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n");
- /*
- * Stop the Watchdog before JTAG handoff
- */
-#ifdef XPAR_XWDTPS_0_BASEADDR
- XWdtPs_Stop(&Watchdog);
-#endif
- /*
- * Clear our mark in reboot status register
- */
- ClearFSBLIn();
-
- /*
- * SLCR lock
- */
- SlcrLock();
-
- FsblHandoffJtagExit();
- } else {
- fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n");
- OutputStatus(ILLEGAL_BOOT_MODE);
- /*
- * fallback starts, no return
- */
- FsblFallback();
- }
-
- fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08x\r\n", FlashReadBaseAddress);
-
- /*
- * Check for valid flash address
- */
- if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) &&
- (FlashReadBaseAddress != XPS_NAND_BASEADDR) &&
- (FlashReadBaseAddress != XPS_NOR_BASEADDR) &&
- (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) {
- fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n");
- OutputStatus(INVALID_FLASH_ADDRESS);
- FsblFallback();
- }
-
- /*
- * NOR and QSPI (parallel) are linear boot devices
- */
- if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) {
- fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n");
- LinearBootDeviceFlag = 1;
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * This used only in case of E-Fuse encryption
- * For image search
- */
- SystemInitFlag = 1;
-
- /*
- * Load boot image
- */
- HandoffAddress = LoadBootImage();
-
- fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08x\r\n",HandoffAddress);
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Total Execution time is ");
- FsblMeasurePerfTime(tCur,tEnd);
-#endif
-
- /*
- * FSBL handoff to valid handoff address or
- * exit in JTAG
- */
- FsblHandoff(HandoffAddress);
-
-#else
- OutputStatus(NO_DDR);
- FsblFallback();
-#endif
-
- return Status;
-}
-
-/******************************************************************************/
-/**
-*
-* This function reset the CPU and goes for Boot ROM fallback handling
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void FsblFallback(void)
-{
- u32 RebootStatusReg;
- u32 Status;
- u32 HandoffAddr;
- u32 BootModeRegister;
-
- /*
- * Read bootmode register
- */
- BootModeRegister = Xil_In32(BOOT_MODE_REG);
- BootModeRegister &= BOOT_MODES_MASK;
-
- /*
- * Fallback support check
- */
- if (!((BootModeRegister == QSPI_MODE) ||
- (BootModeRegister == NAND_FLASH_MODE) ||
- (BootModeRegister == NOR_FLASH_MODE))) {
- fsbl_printf(DEBUG_INFO,"\r\n"
- "This Boot Mode Doesn't Support Fallback\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
-
- /*
- * update the Multiboot Register for Golden search hunt
- */
- Update_MultiBootRegister();
-
- /*
- * Notify Boot ROM something is wrong
- */
- RebootStatusReg = Xil_In32(REBOOT_STATUS_REG);
-
- /*
- * Set the FSBL Fail mask
- */
- Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK);
-
- /*
- * Barrier for synchronization
- */
- asm(
- "dsb\n\t"
- "isb"
- );
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK) {
- /*
- * Next valid image search can happen only
- * when system initialization done
- */
- if (SystemInitFlag == 1) {
- /*
- * Clean the Fabric
- */
- FabricInit();
-
- /*
- * Search for next valid image
- */
- Status = NextValidImageCheck();
- if(Status != XST_SUCCESS){
- fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
-
- /*
- * Load next valid image
- */
- HandoffAddr = LoadBootImage();
-
- /*
- * Handoff to next image
- */
- FsblHandoff(HandoffAddr);
- } else {
- fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n");
- fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
- }
-
- /*
- * Reset PS, so Boot ROM will restart
- */
- Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function hands the A9/PS to the loaded user code.
-*
-* @param none
-*
-* @return none
-*
-* @note This function does not return.
-*
-****************************************************************************/
-void FsblHandoff(u32 FsblStartAddr)
-{
- u32 Status;
-
- /*
- * Enable level shifter
- */
- if(BitstreamFlag) {
- /*
- * FSBL will not enable the level shifters for a NON PS instantiated
- * Bitstream
- * CR# 671028
- * This flag can be set during compilation for a NON PS instantiated
- * bitstream
- */
-#ifndef NON_PS_INSTANTIATED_BITSTREAM
-#ifdef PS7_POST_CONFIG
- ps7_post_config();
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-#else
- /*
- * Set Level Shifters DT618760
- */
- Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS);
- fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS "
- "Address = 0x%x Value = 0x%x \n\r",
- PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN));
-
- /*
- * Enable AXI interface
- */
- Xil_Out32(FPGA_RESET_REG, 0);
- fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r");
- fsbl_printf(DEBUG_INFO, "FPGA Reset Register "
- "Address = 0x%x , Value = 0x%x \r\n",
- FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG));
-#endif
-#endif
- }
-
- /*
- * FSBL user hook call before handoff to the application
- */
- Status = FsblHookBeforeHandoff();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n");
- OutputStatus(FSBL_HANDOFF_HOOK_FAIL);
- FsblFallback();
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- XWdtPs_Stop(&Watchdog);
-#endif
-
- /*
- * Clear our mark in reboot status register
- */
- ClearFSBLIn();
-
- if(FsblStartAddr == 0) {
- /*
- * SLCR lock
- */
- SlcrLock();
-
- fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n");
- FsblHandoffJtagExit();
- } else {
- fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n");
- OutputStatus(SUCCESSFUL_HANDOFF);
- FsblHandoffExit(FsblStartAddr);
- }
-
- OutputStatus(ILLEGAL_RETURN);
-
- FsblFallback();
-}
-
-/******************************************************************************/
-/**
-*
-* This function outputs the status for the provided State in the boot process.
-*
-* @param State is where in the boot process the output is desired.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void OutputStatus(u32 State)
-{
-#ifdef STDOUT_BASEADDRESS
- u32 UartReg = 0;
-
- fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4x\r\n", State);
- /*
- * The TX buffer needs to be flushed out
- * If this is not done some of the prints will not appear on the
- * serial output
- */
- UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
- while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) {
- UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
- }
-#endif
-}
-
-/******************************************************************************/
-/**
-*
-* This function handles the error and lockdown processing and outputs the status
-* for the provided State in the boot process.
-*
-* This function is called upon exceptions.
-*
-* @param State - where in the boot process the error occured.
-*
-* @return None.
-*
-* @note This function does not return, the PS block is reset
-*
-****************************************************************************/
-void ErrorLockdown(u32 State)
-{
- /*
- * Store the error status
- */
- OutputStatus(State);
-
- /*
- * Fall back
- */
- FsblFallback();
-}
-
-/******************************************************************************/
-/**
-*
-* This function copies a memory region to another memory region
-*
-* @param s1 is starting address for destination
-* @param s2 is starting address for the source
-* @param n is the number of bytes to copy
-*
-* @return Starting address for destination
-*
-****************************************************************************/
-void *(memcpy_rom)(void * s1, const void * s2, u32 n)
-{
- char *dst = (char *)s1;
- const char *src = (char *)s2;
-
- /*
- * Loop and copy
- */
- while (n-- != 0)
- *dst++ = *src++;
- return s1;
-}
-/******************************************************************************/
-/**
-*
-* This function copies a string to another, the source string must be null-
-* terminated.
-*
-* @param Dest is starting address for the destination string
-* @param Src is starting address for the source string
-*
-* @return Starting address for the destination string
-*
-****************************************************************************/
-char *strcpy_rom(char *Dest, const char *Src)
-{
- unsigned i;
- for (i=0; Src[i] != '\0'; ++i)
- Dest[i] = Src[i];
- Dest[i] = '\0';
- return Dest;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function sets FSBL is running mask in reboot status register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void MarkFSBLIn(void)
-{
- Xil_Out32(REBOOT_STATUS_REG,
- Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function clears FSBL is running mask in reboot status register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void ClearFSBLIn(void)
-{
- Xil_Out32(REBOOT_STATUS_REG,
- (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK));
-}
-
-/******************************************************************************/
-/**
-*
-* This function Registers the Exception Handlers
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-static void RegisterHandlers(void)
-{
- Xil_ExceptionInit();
-
- /*
- * Initialize the vector table. Register the stub Handler for each
- * exception.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
- (Xil_ExceptionHandler)Undef_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT,
- (Xil_ExceptionHandler)SVC_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
- (Xil_ExceptionHandler)PreFetch_Abort_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
- (Xil_ExceptionHandler)Data_Abort_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
- (Xil_ExceptionHandler)IRQ_Handler,(void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
- (Xil_ExceptionHandler)FIQ_Handler,(void *) 0);
-
- Xil_ExceptionEnable();
-
-}
-
-static void Undef_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n");
- ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT);
-}
-
-static void SVC_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_SWI_INT);
-}
-
-static void PreFetch_Abort_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT);
-}
-
-static void Data_Abort_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT);
-}
-
-static void IRQ_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_IRQ_INT);
-}
-
-static void FIQ_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_FIQ_INT);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function Updates the Multi boot Register to enable golden image
-* search for boot rom
-*
-* @param None
-*
-* @return
-* return none
-*
-****************************************************************************/
-static void Update_MultiBootRegister(void)
-{
- u32 MultiBootReg = 0;
-
- if (Silicon_Version != SILICON_VERSION_1) {
- /*
- * Read the mulitboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- /*
- * Incrementing multiboot register by one
- */
- MultiBootReg++;
-
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET,
- MultiBootReg);
-
- fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08x\r\n",
- MultiBootReg);
- }
-}
-
-
-/******************************************************************************
-*
-* This function reset the CPU and goes for Boot ROM fallback handling
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-*******************************************************************************/
-
-u32 GetResetReason(void)
-{
- u32 Regval;
-
- /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */
- /* for storing the RESET_REASON register value*/
- Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF);
-
- return Regval;
-}
-
-
-/******************************************************************************
-*
-* This function Gets the ticks from the Global Timer
-*
-* @param Current time
-*
-* @return
-* None
-*
-* @note None
-*
-*******************************************************************************/
-#ifdef FSBL_PERF
-void FsblGetGlobalTime (XTime tCur)
-{
- XTime_GetTime(&tCur);
-}
-
-
-/******************************************************************************
-*
-* This function Measures the execution time
-*
-* @param Current time , End time
-*
-* @return
-* None
-*
-* @note None
-*
-*******************************************************************************/
-void FsblMeasurePerfTime (XTime tCur, XTime tEnd)
-{
- double tDiff = 0.0;
- double tPerfSeconds;
- XTime_GetTime(&tEnd);
- tDiff = (double)tEnd - (double)tCur;
-
- /*
- * Convert tPerf into Seconds
- */
- tPerfSeconds = tDiff/COUNTS_PER_SECOND;
-
- /*
- * Convert tPerf into Seconds
- */
- tPerfSeconds = tDiff/COUNTS_PER_SECOND;
-
-#if defined(FSBL_DEBUG) || defined(FSBL_DEBUG_INFO)
- printf("%f seconds \r\n",tPerfSeconds);
-#endif
-
-}
-#endif
-
-/******************************************************************************
-*
-* This function initializes the Watchdog driver and starts the timer
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the Watchdog driver is initialized
-* - XST_FAILURE if Watchdog driver initialization fails
-*
-* @note None
-*
-*******************************************************************************/
-#ifdef XPAR_XWDTPS_0_BASEADDR
-int InitWatchDog(void)
-{
- u32 Status = XST_SUCCESS;
- XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */
- u32 CounterValue = 1;
-
- ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID);
- Status = XWdtPs_CfgInitialize(&Watchdog,
- ConfigPtr,
- ConfigPtr->BaseAddress);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r");
- return XST_FAILURE;
- }
-
- /*
- * Setting the divider value
- */
- XWdtPs_SetControlValue(&Watchdog,
- XWDTPS_CLK_PRESCALE,
- XWDTPS_CCR_PSCALE_4096);
- /*
- * Convert time to Watchdog counter reset value
- */
- CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME);
-
- /*
- * Set the Watchdog counter reset value
- */
- XWdtPs_SetControlValue(&Watchdog,
- XWDTPS_COUNTER_RESET,
- CounterValue);
- /*
- * enable reset output, as we are only using this as a basic counter
- */
- XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL);
-
- /*
- * Start the Watchdog timer
- */
- XWdtPs_Start(&Watchdog);
-
- XWdtPs_RestartWdt(&Watchdog);
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function checks whether WDT reset has happened during FSBL run
-*
-* If WDT reset happened during FSBL run, then need to fallback
-*
-* @param None.
-*
-* @return
-* None
-*
-* @note None
-*
-****************************************************************************/
-void CheckWDTReset(void)
-{
- u32 ResetReason;
- u32 RebootStatusRegister;
-
- RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
-
- /*
- * For 1.0 Silicon the reason for Reset is in the ResetReason Register
- * Hence this register can be read to know the cause for previous reset
- * that happened.
- * Check if that reset is a Software WatchDog reset that happened
- */
- if (Silicon_Version == SILICON_VERSION_1) {
- ResetReason = Xil_In32(RESET_REASON_REG);
- } else {
- ResetReason = GetResetReason();
- }
- /*
- * If the FSBL_IN_MASK Has not been cleared, WDT happened
- * before FSBL exits
- */
- if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) {
- if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) {
- /*
- * Clear the SWDT Reset bit
- */
- ResetReason &= ~RESET_REASON_SWDT;
- if (Silicon_Version == SILICON_VERSION_1) {
- /*
- * for 1.0 Silicon we need to write
- * 1 to the RESET REASON Clear register
- */
- Xil_Out32(RESET_REASON_CLR, 1);
- } else {
- Xil_Out32(REBOOT_STATUS_REG, ResetReason);
- }
-
- fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r");
- }
- }
-}
-
-
-/******************************************************************************
-*
-* This function converts time into Watchdog counter value
-*
-* @param watchdog expire time in seconds
-*
-* @return
-* Counter value for Watchdog
-*
-* @note None
-*
-*******************************************************************************/
-u32 ConvertTime_WdtCounter(u32 seconds)
-{
- double time = 0.0;
- double CounterValue;
- u32 Crv = 0;
- u32 Prescaler,PrescalerValue;
-
- Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE);
-
- if (Prescaler == XWDTPS_CCR_PSCALE_0008)
- PrescalerValue = 8;
- if (Prescaler == XWDTPS_CCR_PSCALE_0064)
- PrescalerValue = 64;
- if (Prescaler == XWDTPS_CCR_PSCALE_4096)
- PrescalerValue = 4096;
-
- time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ;
-
- CounterValue = seconds / time;
-
- Crv = (u32)CounterValue;
- Crv >>= WDT_CRV_SHIFT;
-
- return Crv;
-}
-
-#endif
-
-
-/******************************************************************************
-*
-* This function Gets the Silicon Version stores in global variable
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-*******************************************************************************/
-void GetSiliconVersion(void)
-{
- /*
- * Get the silicon version
- */
- Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr);
- if(Silicon_Version == SILICON_VERSION_3_1) {
- fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n");
- } else {
- fsbl_printf(DEBUG_GENERAL,"Silicon Version %d.0\r\n",
- Silicon_Version + 1);
- }
-}
-
-
-/******************************************************************************
-*
-* This function HeaderChecksum will calculates the header checksum and
-* compares with checksum read from flash
-*
-* @param FlashOffsetAddress Flash offset address
-*
-* @return
-* - XST_SUCCESS if ID matches
-* - XST_FAILURE if ID mismatches
-*
-* @note None
-*
-*******************************************************************************/
-u32 HeaderChecksum(u32 FlashOffsetAddress){
- u32 Checksum = 0;
- u32 Count;
- u32 TempValue = 0;
-
- for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) {
- /*
- * Read the word from the header
- */
- MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4);
-
- /*
- * Update checksum
- */
- Checksum += TempValue;
- }
-
- /*
- * Invert checksum, last bit of error checking
- */
- Checksum ^= 0xFFFFFFFF;
- MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4);
-
- /*
- * Validate the checksum
- */
- if (TempValue != Checksum){
- fsbl_printf(DEBUG_INFO, "Checksum = %8.8x\r\n", Checksum);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function ImageCheckID will do check for XLNX pattern
-*
-* @param FlashOffsetAddress Flash offset address
-*
-* @return
-* - XST_SUCCESS if ID matches
-* - XST_FAILURE if ID mismatches
-*
-* @note None
-*
-*******************************************************************************/
-u32 ImageCheckID(u32 FlashOffsetAddress){
- u32 ID;
-
- /*
- * Read in the header info
- */
- MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4);
-
- /*
- * Check the ID, make sure image is XLNX format
- */
- if (ID != IMAGE_IDENT){
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function NextValidImageCheck search for valid boot image
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if valid image found
-* - XST_FAILURE if no image found
-*
-* @note None
-*
-*******************************************************************************/
-u32 NextValidImageCheck(void)
-{
- u32 ImageBaseAddr;
- u32 MultiBootReg;
- u32 BootDevMaxSize=0;
-
- fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image");
-
- /*
- * Setting variable with maximum flash size based on boot mode
- */
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
- if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) {
- BootDevMaxSize = QspiFlashSize;
- }
-#endif
-
- if (FlashReadBaseAddress == XPS_NAND_BASEADDR) {
- BootDevMaxSize = NAND_FLASH_SIZE;
- }
-
- if (FlashReadBaseAddress == XPS_NOR_BASEADDR) {
- BootDevMaxSize = NOR_FLASH_SIZE;
- }
-
- /*
- * Read the multiboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- /*
- * Compute the image start address
- */
- ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
-
- /*
- * Valid image search continue till end of the flash
- * With increment 32KB in each iteration
- */
- while (ImageBaseAddr < BootDevMaxSize) {
-
- fsbl_printf(DEBUG_INFO,".");
-
- /*
- * Valid image search using XLNX pattern at fixed offset
- * and header checksum
- */
- if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) &&
- (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) {
-
- fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8x\r\n",
- ImageBaseAddr);
- /*
- * Update multiboot register
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET,
- MultiBootReg);
-
- return XST_SUCCESS;
- }
-
- /*
- * Increment mulitboot count
- */
- MultiBootReg++;
-
- /*
- * Compute the image start address
- */
- ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
- }
-
- return XST_FAILURE;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Checks for the ddr initialization completion
-*
-* @param None.
-*
-* @return
-* - XST_SUCCESS if the initialization is successful
-* - XST_FAILURE if the initialization is NOT successful
-*
-* @note None.
-*
-****************************************************************************/
-u32 DDRInitCheck(void)
-{
- u32 ReadVal;
-
- /*
- * Write and Read from the DDR location for sanity checks
- */
- Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN);
- ReadVal = Xil_In32(DDR_START_ADDR);
- if (ReadVal != DDR_TEST_PATTERN) {
- return XST_FAILURE;
- }
-
- /*
- * Write and Read from the DDR location for sanity checks
- */
- Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN);
- ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET);
- if (ReadVal != DDR_TEST_PATTERN) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
diff --git a/quad/zybo_fsbl/src/md5.c b/quad/zybo_fsbl/src/md5.c
deleted file mode 100644
index 1aa0819001d70a519d62e404ecdf96b66cce7a8f..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/md5.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
- * All rights reserved.
- *
- * This package is an SSL implementation written
- * by Eric Young (eay@cryptsoft.com).
- * The implementation was written so as to conform with Netscapes SSL.
- *
- * This library is free for commercial and non-commercial use as long as
- * the following conditions are aheared to. The following conditions
- * apply to all code found in this distribution, be it the RC4, RSA,
- * lhash, DES, etc., code; not just the SSL code. The SSL documentation
- * included with this distribution is covered by the same copyright terms
- * except that the holder is Tim Hudson (tjh@cryptsoft.com).
- *
- * Copyright remains Eric Young's, and as such any Copyright notices in
- * the code are not to be removed.
- * If this package is used in a product, Eric Young should be given attribution
- * as the author of the parts of the library used.
- * This can be in the form of a textual message at program startup or
- * in documentation (online or textual) provided with the package.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * "This product includes cryptographic software written by
- * Eric Young (eay@cryptsoft.com)"
- * The word 'cryptographic' can be left out if the rouines from the library
- * being used are not cryptographic related :-).
- * 4. If you include any Windows specific code (or a derivative thereof) from
- * the apps directory (application code) you must include an acknowledgement:
- * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
- *
- * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * The licence and distribution terms for any publically available version or
- * derivative of this code cannot be changed. i.e. this code cannot simply be
- * copied and put under another distribution licence
- * [including the GNU Public Licence.]
- */
-/*****************************************************************************/
-/**
-*
-* @file md5.c
-*
-* Contains code to calculate checksum using md5 algorithm
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00a sgd 05/17/13 Initial release
-*
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-/****************************** Include Files *********************************/
-
-#include "md5.h"
-
-/******************************************************************************/
-/**
-*
-* This function sets the memory
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void * _memset( void *dest, int ch, u32 count )
-{
- register char *dst8 = (char*)dest;
-
- while( count-- )
- *dst8++ = ch;
-
- return dest;
-}
-
-/******************************************************************************/
-/**
-*
-* This function copy the memory
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void * _memcpy( void *dest, const void *src,
- u32 count, boolean doByteSwap )
-{
- register char * dst8 = (char*)dest;
- register char * src8 = (char*)src;
-
- if( doByteSwap == FALSE ) {
- while( count-- )
- *dst8++ = *src8++;
- } else {
- count /= sizeof( u32 );
-
- while( count-- ) {
- dst8[ 0 ] = src8[ 3 ];
- dst8[ 1 ] = src8[ 2 ];
- dst8[ 2 ] = src8[ 1 ];
- dst8[ 3 ] = src8[ 0 ];
-
- dst8 += 4;
- src8 += 4;
- }
- }
-
- return dest;
-}
-
-/******************************************************************************/
-/**
-*
-* This function is the core of the MD5 algorithm,
-* this alters an existing MD5 hash to
-* reflect the addition of 16 longwords of new data. MD5Update blocks
-* the data and converts bytes into longwords for this routine.
-*
-* Use binary integer part of the sine of integers (Radians) as constants.
-* Calculated as:
-*
-* for( i = 0; i < 63; i++ )
-* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
-*
-* Following number is the per-round shift amount.
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void MD5Transform( u32 *buffer, u32 *intermediate )
-{
- register u32 a, b, c, d;
-
- a = buffer[ 0 ];
- b = buffer[ 1 ];
- c = buffer[ 2 ];
- d = buffer[ 3 ];
-
- MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
-
- MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
-
- MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
-
- MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
-
- buffer[ 0 ] += a;
- buffer[ 1 ] += b;
- buffer[ 2 ] += c;
- buffer[ 3 ] += d;
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function Start MD5 accumulation
-* Set bit count to 0 and buffer to mysterious initialization constants
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Init( MD5Context *context )
-{
-
- context->buffer[ 0 ] = 0x67452301;
- context->buffer[ 1 ] = 0xefcdab89;
- context->buffer[ 2 ] = 0x98badcfe;
- context->buffer[ 3 ] = 0x10325476;
-
- context->bits[ 0 ] = 0;
- context->bits[ 1 ] = 0;
-
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function updates context to reflect the concatenation of another
-* buffer full of bytes
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Update( MD5Context *context, u8 *buffer,
- u32 len, boolean doByteSwap )
-{
- register u32 temp;
- register u8 * p;
-
- /*
- * Update bitcount
- */
-
- temp = context->bits[ 0 ];
-
- if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
- /*
- * Carry from low to high
- */
- context->bits[ 1 ]++;
- }
-
- context->bits[ 1 ] += len >> 29;
-
- /*
- * Bytes already in shsInfo->data
- */
-
- temp = ( temp >> 3 ) & 0x3f;
-
- /*
- * Handle any leading odd-sized chunks
- */
-
- if( temp ) {
- p = (u8 *)context->intermediate + temp;
-
- temp = MD5_SIGNATURE_BYTE_SIZE - temp;
-
- if( len < temp ) {
- _memcpy( p, buffer, len, doByteSwap );
- return;
- }
-
- _memcpy( p, buffer, temp, doByteSwap );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- buffer += temp;
- len -= temp;
-
- }
-
- /*
- * Process data in 64-byte, 512 bit, chunks
- */
-
- while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
- _memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
- doByteSwap );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- buffer += MD5_SIGNATURE_BYTE_SIZE;
- len -= MD5_SIGNATURE_BYTE_SIZE;
-
- }
-
- /*
- * Handle any remaining bytes of data
- */
- _memcpy( context->intermediate, buffer, len, doByteSwap );
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function final wrap-up - pad to 64-byte boundary with the bit pattern
-* 1 0* (64-bit count of bits processed, MSB-first
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Final( MD5Context *context, u8 *digest,
- boolean doByteSwap )
-{
- u32 count;
- u8 * p;
-
- /*
- * Compute number of bytes mod 64
- */
- count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
-
- /*
- * Set the first char of padding to 0x80. This is safe since there is
- * always at least one byte free
- */
- p = context->intermediate + count;
- *p++ = 0x80;
-
- /*
- * Bytes of padding needed to make 64 bytes
- */
- count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
-
- /*
- * Pad out to 56 mod 64
- */
- if( count < 8 ) {
- /*
- * Two lots of padding: Pad the first block to 64 bytes
- */
- _memset( p, 0, count );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- /*
- * Now fill the next block with 56 bytes
- */
- _memset( context->intermediate, 0, 56 );
- } else {
- /*
- * Pad block to 56 bytes
- */
- _memset( p, 0, count - 8 );
- }
-
- /*
- * Append length in bits and transform
- */
- ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
- ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- /*
- * Now return the digest
- */
- _memcpy( digest, context->buffer, 16, doByteSwap );
-}
-
-/******************************************************************************/
-/**
-*
-* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
-* 'input'. 'digest' must have enough space to hold 16 bytes
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
-{
- MD5Context context;
-
- MD5Init( &context );
-
- MD5Update( &context, input, len, doByteSwap );
-
- MD5Final( &context, digest, doByteSwap );
-}
diff --git a/quad/zybo_fsbl/src/md5.h b/quad/zybo_fsbl/src/md5.h
deleted file mode 100644
index a00c17b1a1f3bba0a90b0105b93e2746aff3070c..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/md5.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file md5.h
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00a sgd 05/17/13 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___MD5_H___
-#define ___MD5_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-#define MD5_SIGNATURE_BYTE_SIZE 64
-
-/**************************** Type Definitions *******************************/
-
-typedef u8 boolean;
-typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
-
-struct MD5Context
- {
- u32 buffer[ 4 ];
- u32 bits[ 2 ];
- signature intermediate;
- };
-typedef struct MD5Context MD5Context;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * The four core functions - F1 is optimized somewhat
- */
-#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
-#define F2( x, y, z ) F1( z, x, y )
-#define F3( x, y, z ) ( x ^ y ^ z )
-#define F4( x, y, z ) ( y ^ ( x | ~z ) )
-
-
-/*
- * This is the central step in the MD5 algorithm
- */
-#define MD5_STEP( f, w, x, y, z, data, s ) \
- ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
-
-
-/************************** Function Prototypes ******************************/
-
-void * _memset( void *dest, int ch, u32 count );
-
-void * _memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
-
-void MD5Transform( u32 *buffer, u32 *intermediate );
-
-void MD5Init( MD5Context *context );
-
-void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
-
-void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
-
-void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___MD5_H___ */
diff --git a/quad/zybo_fsbl/src/mmc.c b/quad/zybo_fsbl/src/mmc.c
deleted file mode 100644
index 8543b10c404dd636f1c595ba0842e5aee91748ed..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/mmc.c
+++ /dev/null
@@ -1,1181 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file mmc.c
-*
-* SD interface to FatFS
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a bh 05/28/11 Initial release
-* 1.00a nm 03/20/12 Changed the SD base clock divider from
- 0x40 to 0x04.
-* 3.00a mb 08/16/12 Added the flag XPAR_PS7_SD_0_S_AXI_BASEADDR
-* 3.00a sgd 08/16/12 SD Boot time improvement
-* Added SD high speed and 4bit support check
-* 4.00a sgd 02/28/13 Code cleanup
-* 5.00a sgd 05/17/13 Added MMC support
-* To support MMC, added two separate functions
-* sd_init for SD initialization
-* mmc_init for MMC initialization
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "fsbl.h"
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-
-#include "diskio.h" /* Common include file for FatFs and disk I/O layer */
-#include "ff.h"
-#include "xil_types.h"
-#include "sd_hardware.h"
-#include "sleep.h"
-#ifndef PEEP_CODE
-#include "ps7_init.h"
-#endif
-
-/*
- * Map logical volume to physical drive + partition.
- * Logical X [0-3] to Physical 0, partition X
- */
-#if _MULTI_PARTITION
-const PARTITION VolToPart[] = {
- {0, 0}, {0, 1}, {0, 2}, {0, 3} };
-#endif
-
-static DSTATUS Stat; /* Disk status */
-static BYTE CardType; /* b0:MMC, b1:SDv1, b2:SDv2, b3:Block addressing */
-
-/* Block Count variable */
-static u16 blkcnt;
-/* Block Size variable */
-static u16 blksize;
-
-/* ADMA2 descriptor table */
-static u32 desc_table[4];
-
-#define sd_out32(OutAddress, Value) Xil_Out32((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (OutAddress), (Value))
-#define sd_out16(OutAddress, Value) Xil_Out16((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (OutAddress), (Value))
-#define sd_out8(OutAddress, Value) Xil_Out8((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (OutAddress), (Value))
-
-#define sd_in32(InAddress) Xil_In32((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (InAddress))
-#define sd_in16(InAddress) Xil_In16((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (InAddress))
-#define sd_in8(InAddress) Xil_In8((XPAR_PS7_SD_0_S_AXI_BASEADDR) + (InAddress))
-
-#ifdef MMC_SUPPORT
-
-#define MMC_CLK_52M 52000000
-#define MMC_CLK_26M 26000000
-#define MMC_HS_SUPPORT 0x1
-#define MMC_4BIT_SUPPORT 0x1
-#define EXT_CSD_BUS_WIDTH 183
-#define EXT_CSD_HS_TIMING 185
-#define MMC_SWITCH_MODE_WRITE_BYTE 0x03
-#define MMC_OCR_REG_VALUE ((0x1 << 30) | (0x1FF << 15))
-
-static DRESULT mmc_init(void);
-#else
-
-static DRESULT sd_init(void);
-
-#endif
-/******************************************************************************/
-/**
-*
-* This function Initializes the SD controller
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-static void init_port(void)
-{
- unsigned clk;
- unsigned clk_div;
-
- Stat = STA_NOINIT;
-
- /*
- * Power off the card
- */
- sd_out8(SD_PWR_CTRL_R, 0);
-
- /*
- * Disable interrupts
- */
- sd_out32(SD_SIG_ENA_R, 0);
-
- /*
- * Perform soft reset
- */
- sd_out8(SD_SOFT_RST_R, SD_RST_ALL);
-
- /*
- * Wait for reset to complete
- */
- while (sd_in8(SD_SOFT_RST_R)) {
- ;
- }
-
- /*
- * Power on the card
- */
- sd_out8(SD_PWR_CTRL_R, SD_POWER_33|SD_POWER_ON);
-
- /*
- * Enable ADMA2
- */
- sd_out8(SD_HOST_CTRL_R, SD_HOST_ADMA2);
-
- clk_div = (SDIO_FREQ/SD_CLK_400K);
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- clk = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, clk);
- do {
- clk = sd_in16(SD_CLK_CTL_R);
- } while (!(clk & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- clk |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, clk);
-
- sd_out32(SD_SIG_ENA_R, 0xFFFFFFFF);
- sd_out32(SD_INT_ENA_R, 0xFFFFFFFF);
-}
-
-
-/******************************************************************************/
-/**
-*
-* Module Private Functions
-*
-****************************************************************************/
-/*
- * MMC/SD commands
- */
-#define CMD0 (0) /* GO_IDLE_STATE */
-#define CMD1 (1) /* SEND_OP_COND */
-#define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */
-#define CMD2 (2) /* SEND_CID */
-#define CMD3 (3) /* RELATIVE_ADDR */
-#define CMD4 (4) /* SET_DSR */
-#define CMD5 (5) /* SLEEP_WAKE (SDC) */
-#define CMD6 (6) /* SWITCH_FUNC */
-#define ACMD6 (0x80+6) /* SET_BUS_WIDTH (SDC) */
-#define CMD7 (7) /* SELECT */
-#define CMD8 (8) /* SEND_IF_COND/SEND_EXT_CSD */
-#define CMD9 (9) /* SEND_CSD */
-#define CMD10 (10) /* SEND_CID */
-#define CMD12 (12) /* STOP_TRANSMISSION */
-#define ACMD13 (0x80+13) /* SD_STATUS (SDC) */
-#define CMD16 (16) /* SET_BLOCKLEN */
-#define CMD17 (17) /* READ_SINGLE_BLOCK */
-#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
-#define CMD23 (23) /* SET_BLOCK_COUNT */
-#define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */
-#define CMD24 (24) /* WRITE_BLOCK */
-#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
-#define CMD41 (41) /* SEND_OP_COND (ACMD) */
-#define ACMD42 (0x80+42) /* SET_CLR_CARD_DETECT (ACMD) */
-#define ACMD51 (0x80+51) /* SEND_SCR */
-#define CMD52 (52) /* */
-#define CMD55 (55) /* APP_CMD */
-#define CMD58 (58) /* READ_OCR */
-
-/*
- * Card type flags (CardType)
- */
-#define CT_MMC 0x01 /* MMC ver 3 */
-#define CT_SD1 0x02 /* SD ver 1 */
-#define CT_SD2 0x04 /* SD ver 2 */
-#define CT_SDC (CT_SD1|CT_SD2) /* SD */
-#define CT_BLOCK 0x08 /* Block addressing */
-
-
-/******************************************************************************/
-/**
-*
-* This function Determine the value of the controller transfer register
-* for the provided
-*
-* @param cmd command index
-*
-* @return cmd value
-*
-* @note None
-*
-****************************************************************************/
-static int make_command (unsigned cmd)
-{
- unsigned retval;
-
- retval = cmd << 8;
-
-#define RSP_NONE SD_CMD_RESP_NONE
-#define RSP_R1 (SD_CMD_INDEX|SD_CMD_RESP_48 |SD_CMD_CRC)
-#define RSP_R1b (SD_CMD_INDEX|SD_CMD_RESP_48_BUSY|SD_CMD_CRC)
-#define RSP_R2 (SD_CMD_CRC |SD_CMD_RESP_136)
-#define RSP_R3 (SD_CMD_RESP_48)
-#define RSP_R6 (SD_CMD_INDEX|SD_CMD_RESP_48_BUSY|SD_CMD_CRC)
-
- switch(cmd) {
- case CMD0:
- retval |= (SD_CMD_RESP_NONE);
- break;
- case CMD1:
- retval |= RSP_R3;
- break;
- case CMD2:
- retval |= RSP_R2;
- break;
- case CMD3:
- retval |= RSP_R6;
- break;
- case CMD4:
- retval |= (SD_CMD_RESP_NONE);
- break;
- case CMD5:
- retval |= RSP_R1b;
- break;
-#ifdef MMC_SUPPORT
- case CMD6:
- retval |= RSP_R1b;
- break;
-#else
- case CMD6:
- retval |= RSP_R1 | SD_CMD_DATA;
- break;
-#endif
- case ACMD6:
- retval |= RSP_R1;
- break;
- case CMD7:
- retval |= RSP_R1;
- break;
-#ifdef MMC_SUPPORT
- case CMD8:
- retval |= RSP_R1 | SD_CMD_DATA;
- break;
-#else
- case CMD8:
- retval |= RSP_R1;
- break;
-#endif
- case CMD9:
- retval |= RSP_R2;
- break;
- case CMD10:
- case CMD12:
- case ACMD13:
- case CMD16:
- retval |= RSP_R1;
- break;
- case CMD17:
- case CMD18:
- retval |= RSP_R1|SD_CMD_DATA;
- break;
- case CMD23:
- case ACMD23:
- case CMD24:
- case CMD25:
- case CMD41:
- retval |= RSP_R3;
- break;
- case ACMD42:
- retval |= RSP_R1;
- break;
- case ACMD51:
- retval |= RSP_R1|SD_CMD_DATA;
- break;
- case CMD52:
- case CMD55:
- retval |= RSP_R1;
- break;
- case CMD58:
- break;
- }
-
- return retval;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Determine the value of the controller transfer register
-* for the provided
-*
-* @param cmd Command byte
-*
-* @param arg Argument
-*
-* @param response Response from device
-*
-* @return 1 on success
-* 0 on timeout
-*
-* @note None
-*
-****************************************************************************/
-static BYTE send_cmd (BYTE cmd, DWORD arg, DWORD *response)
-{
- u32 status;
- u16 cmdreg;
-
- if (response) {
- *response = 0;
- }
-
- /*
- * Wait until the device is willing to accept commands
- */
- do {
- status = sd_in32(SD_PRES_STATE_R);
- } while (status & (SD_CMD_INHIBIT|SD_DATA_INHIBIT));
-
- /*
- * Clear all pending interrupt status
- */
- sd_out32(SD_INT_STAT_R, 0xFFFFFFFF);
-
- /*
- * 512 byte block size.
- * This is only relevant for data commands.
- */
- sd_out16(SD_BLOCK_SZ_R, blksize);
- sd_out16(SD_BLOCK_CNT_R, blkcnt);
-
- /*
- * Setting timeout to max value
- */
- sd_out8(SD_TIMEOUT_CTL_R, 0xE);
-
- sd_out32(SD_ARG_R, arg);
-
- if (cmd!=CMD18) {
- sd_out16(SD_TRNS_MODE_R, SD_TRNS_READ|SD_TRNS_DMA);
- } else {
- /*
- * Set the transfer mode to read, DMA, multiple block
- * (applicable only to data commands)
- * This is all that this software supports.
- */
- sd_out16(SD_TRNS_MODE_R, SD_TRNS_READ|SD_TRNS_MULTI|
- SD_TRNS_ACMD12|SD_TRNS_BLK_CNT_EN|SD_TRNS_DMA);
- }
-
- /*
- * Initiate the command
- */
- cmdreg = make_command(cmd);
- sd_out16(SD_CMD_R, cmdreg);
-
- /*
- * Poll until operation complete
- */
- while (1) {
- status = sd_in32(SD_INT_STAT_R);
- if (status & SD_INT_ERROR) {
- fsbl_printf(DEBUG_GENERAL,"send_cmd: Error: (0x%08x) cmd: %d arg: 0x%x\n",
- status, cmd, arg);
- sd_out8(SD_SOFT_RST_R, SD_RST_CMD|SD_RST_DATA);
-
- return 0;
- }
- /*
- * Check for Command complete
- */
- if (status & SD_INT_CMD_CMPL) {
- sd_out32(SD_INT_STAT_R, SD_INT_CMD_CMPL);
- break;
- }
- }
-
- status = sd_in32(SD_RSP_R);
- if (response) {
- *response = status;
- }
-
- return 1;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function Setup ADMA2 for data transfer
-*
-* @param buff_ptr
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void setup_adma2_trans(BYTE *buff_ptr)
-{
- /*
- * Set descriptor table
- */
- desc_table[0] = ((blkcnt*blksize) << DESC_ATBR_LEN_SHIFT)|
- DESC_ATBR_ACT_TRAN|DESC_ATBR_END|DESC_ATBR_VALID;
- desc_table[1] = (u32)buff_ptr;
-
- /*
- * Set ADMA system address register
- */
- sd_out32(SD_ADMA_ADDR_R, (u32)&desc_table[0]);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function is wait for DMA transfer complete
-*
-* @param None
-*
-* @return 0 for failure
-* 1 for success
-* @note None
-*
-****************************************************************************/
-static BYTE dma_trans_cmpl(void)
-{
- u32 status;
-
- /*
- * Poll until operation complete
- */
- while (1) {
- status = sd_in32(SD_INT_STAT_R);
- if (status & SD_INT_ERROR) {
- fsbl_printf(DEBUG_GENERAL,"dma_trans_cmpl: Error: (0x%08x)\r\n",
- status);
- return 0;
- }
-
- /*
- * Check for Transfer complete
- */
- if (status & SD_INT_TRNS_CMPL) {
- sd_out32(SD_INT_STAT_R, SD_INT_TRNS_CMPL);
- break;
- }
- }
- return 1;
-}
-
-/*--------------------------------------------------------------------------
-
- Public Functions
-
----------------------------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------------------*/
-/* Get Disk Status */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_status (
- BYTE drv /* Drive number (0) */
-)
-{
- DSTATUS s = Stat;
- unsigned statusreg;
-
- statusreg = sd_in32(SD_PRES_STATE_R);
- if (!(statusreg & SD_CARD_INS)) {
- s = STA_NODISK | STA_NOINIT;
- } else {
- s &= ~STA_NODISK;
- if (statusreg & SD_CARD_WP)
- s |= STA_PROTECT;
- else
- s &= ~STA_PROTECT;
- }
- Stat = s;
-
- return s;
-}
-
-/*-----------------------------------------------------------------------*/
-/* Initialize Disk Drive */
-/*-----------------------------------------------------------------------*/
-
-DSTATUS disk_initialize (
- BYTE drv /* Physical drive number (0) */
-)
-{
- DSTATUS s;
-
- /*
- * Check if card is in the socket
- */
- s = disk_status(drv);
- if (s & STA_NODISK) {
- fsbl_printf(DEBUG_GENERAL,"No SD card present.\n");
- return s;
- }
-
- /*
- * Initialize the host controller
- */
- init_port();
-
-#ifdef MMC_SUPPORT
- s = mmc_init();
- if(s != RES_OK) {
- fsbl_printf(DEBUG_GENERAL,"MMC Initialization Failed.\n");
- return s;
- }
-#else
- s = sd_init();
- if(s != RES_OK) {
- fsbl_printf(DEBUG_GENERAL,"SD Initialization Failed.\n");
- return s;
- }
-#endif
-
- if (CardType) /* Initialization succeeded */
- s &= ~STA_NOINIT;
- else /* Initialization failed */
- s |= STA_NOINIT;
- Stat = s;
-
- return s;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Sector(s) */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_read (
- BYTE drv, /* Physical drive number (0) */
- BYTE *buff, /* Pointer to the data buffer to store read data */
- DWORD sector, /* Start sector number (LBA) */
- BYTE count /* Sector count (1..128) */
-)
-{
- DSTATUS s;
-
- s = disk_status(drv);
- if (s & STA_NOINIT) return RES_NOTRDY;
- if (!count) return RES_PARERR;
- /* Convert LBA to byte address if needed */
- if (!(CardType & CT_BLOCK)) sector *= SD_BLOCK_SZ;
-
- blkcnt = count;
- blksize= SD_BLOCK_SZ;
-
- /* set adma2 for transfer */
- setup_adma2_trans(buff);
-
- /* Multiple block read */
- send_cmd(CMD18, sector, NULL);
-
- /* check for dma transfer complete */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- return RES_OK;
-}
-
-
-/*-----------------------------------------------------------------------*/
-/* Miscellaneous Functions */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_ioctl (
- BYTE drv, /* Physical drive number (0) */
- BYTE ctrl, /* Control code */
- void *buff /* Buffer to send/receive control data */
-)
-{
- DRESULT res;
-
- if (disk_status(drv) & STA_NOINIT) /* Check if card is in the socket */
- return RES_NOTRDY;
-
- res = RES_ERROR;
- switch (ctrl) {
- case CTRL_SYNC : /* Make sure that no pending write process */
- break;
-
- case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
- break;
-
- case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
- *(DWORD*)buff = 128;
- res = RES_OK;
- break;
-
- default:
- res = RES_PARERR;
- break;
- }
-
- return res;
-}
-
-/******************************************************************************/
-/**
-*
-* This function is User Provided Timer Function for FatFs module
-*
-* @param None
-*
-* @return DWORD
-*
-* @note None
-*
-****************************************************************************/
-DWORD get_fattime (void)
-{
- return ((DWORD)(2010 - 1980) << 25) /* Fixed to Jan. 1, 2010 */
- | ((DWORD)1 << 21)
- | ((DWORD)1 << 16)
- | ((DWORD)0 << 11)
- | ((DWORD)0 << 5)
- | ((DWORD)0 >> 1);
-}
-
-
-
-#ifdef MMC_SUPPORT
-/*
- * MMC initialization
- */
-static DRESULT mmc_init(void)
-{
- BYTE ty;
- DSTATUS s;
- DWORD response;
- unsigned rca;
- u16 regval;
- u16 clk_div;
- u32 argument;
- u8 status_data[512];
-
- ty= CT_MMC;
-
- /*
- * Enter Idle state
- */
- send_cmd(CMD0, 0, NULL);
-
- /*
- * Wait for leaving idle state (CMD1 with HCS bit)
- */
- while (1) {
-
- argument = MMC_OCR_REG_VALUE;
-
- s= send_cmd(CMD1, argument, &response);
- if (s == 0) {
- /*
- * command error; probably an SD card
- */
- ty = 0;
- goto fail;
- }
- if (response & 1<<31) {
- break;
- }
- }
-
- if (response & 1<<30) {
- /*
- * Card supports block addressing
- */
- ty |= CT_BLOCK;
- }
-
- /*
- * Get CID
- */
- send_cmd(CMD2, 0, &response);
-
- /*
- * Set RCA
- */
- rca = 0x1234;
- send_cmd(CMD3, rca << 16, &response);
-
- /*
- * Send CSD
- */
- send_cmd(CMD9,rca<<16,&response);
-
- /*
- * select card
- */
- send_cmd(CMD7, rca << 16, &response);
-
- /*
- * Switch the bus width to 4bit
- */
- argument = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
- (EXT_CSD_BUS_WIDTH << 16) |
- (1 << 8);
- send_cmd(CMD6, argument, &response);
-
- /*
- * Delay for device to setup
- */
- usleep(1000);
-
- /*
- * Enable 4bit mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_4BIT;
- sd_out16(SD_HOST_CTRL_R, regval);
-
- /*
- * Switch device to high speed
- */
- argument = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
- (EXT_CSD_HS_TIMING << 16) |
- (1 << 8);
- send_cmd(CMD6, argument, &response);
-
- /*
- * Delay for device to setup
- */
- usleep(1000);
-
- /*
- * Verify Bus width switch to high speed support
- */
- blkcnt = 1;
- blksize= 512;
-
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Check for high speed support switch
- */
- send_cmd(CMD8, 0x0, &response);
-
- /*
- * Check for dma transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * Check for 4bit support
- */
- if (status_data[EXT_CSD_BUS_WIDTH] == MMC_4BIT_SUPPORT) {
- fsbl_printf(DEBUG_INFO, "Bus Width 4Bit\r\n");
- }
-
-
- if (status_data[EXT_CSD_HS_TIMING] == MMC_HS_SUPPORT) {
- fsbl_printf(DEBUG_INFO, "High Speed Mode\r\n");
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- clk_div = (SDIO_FREQ / MMC_CLK_52M);
- if (!(SDIO_FREQ % MMC_CLK_52M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Enable high speed mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_HS;
- sd_out16(SD_HOST_CTRL_R, regval);
- } else {
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Calculating clock divisor
- */
- clk_div = (SDIO_FREQ / MMC_CLK_26M);
- if (!(SDIO_FREQ % MMC_CLK_26M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- }
-
- /*
- * Set R/W block length to 512
- */
- send_cmd(CMD16, SD_BLOCK_SZ, &response);
-
-fail:
- CardType = ty;
-
- return RES_OK;
-}
-
-#else
-/*
- * SD initialization
- */
-DRESULT sd_init(void)
-{
- BYTE ty;
- DSTATUS s;
- DWORD response;
- unsigned rca;
- u16 regval;
- u8 status_data[64];
- u8 sd_4bit_flag=0;
- u8 sd_hs_flag=0;
- u16 clk_div;
-
- /*
- * Enter Idle state
- */
- send_cmd(CMD0, 0, NULL);
-
- ty = CT_SD1;
- /*
- * SDv2?
- */
- if (send_cmd(CMD8, 0x1AA, &response) == 1) {
- /*
- * The card can work at vdd range of 2.7-3.6V
- */
- if (response == 0x1AA) {
- ty = CT_SD2;
- }
- }
-
- /*
- * Wait for leaving idle state (ACMD41 with HCS bit)
- */
- while (1) {
- /*
- * ACMD41, Set Operating Continuous
- */
- send_cmd(CMD55, 0, NULL);
- /* 0x00ff8000 */
- s = send_cmd(CMD41, 0x40300000, &response);
- if (s == 0) {
- /*
- * command error; probably an MMC card
- * presently unsupported; abort
- */
- ty = 0;
- goto fail;
- }
- if (response & 1<<31) {
- break;
- }
- }
- if (response & 1<<30) {
- /*
- * Card supports block addressing
- */
- ty |= CT_BLOCK;
- }
-
- /*
- * Get CID
- */
- send_cmd(CMD2, 0, &response);
-
- /*
- * Get RCA
- */
- rca = 0x1234;
- send_cmd(CMD3, rca << 16, &response);
- rca = response >> 16;
-
- /*
- * select card
- */
- send_cmd(CMD7, rca << 16, &response);
-
- /*
- * Getting 4bit support information
- */
- blkcnt = 1;
- blksize= 8;
-
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Application specific command
- */
- send_cmd(CMD55, rca << 16, &response);
-
- /*
- * Read SD Configuration Register
- */
- send_cmd(ACMD51, 0, &response);
-
- /*
- * Check for dma transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * SD 4-bit support check
- */
- if (status_data[1]&SD_4BIT_SUPPORT) {
- sd_4bit_flag=1;
- }
-
- /*
- * Getting high speed support support information
- */
- blkcnt = 1;
- blksize= 64;
-
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Check for high speed support switch
- */
- send_cmd(CMD6, 0x00FFFFF0, &response);
-
- /*
- * Check for dma transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * SD high speed support check
- */
- if (status_data[13]&SD_HS_SUPPORT) {
- sd_hs_flag=1;
- }
-
- /*
- * Application specific command
- */
- send_cmd(CMD55, rca << 16, &response);
-
- /*
- * Clear card detect pull-up
- */
- send_cmd(ACMD42, 0, &response);
-
- if (sd_4bit_flag) {
- /*
- * Application specific command
- */
- send_cmd(CMD55, rca << 16, &response);
-
- /*
- * Set data bus width to 4-bit
- */
- send_cmd(ACMD6, 2, &response);
-
- /*
- * Enable 4bit mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_4BIT;
- sd_out16(SD_HOST_CTRL_R, regval);
- }
-
- if (sd_hs_flag) {
- /*
- * Set adma2 for transfer
- */
- setup_adma2_trans(&status_data[0]);
-
- /*
- * Switch device to high speed
- */
- send_cmd(CMD6, 0x80FFFFF1, &response);
-
- /*
- * Check for DMA transfer complete
- */
- if (!dma_trans_cmpl()) {
- return RES_ERROR;
- }
-
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- clk_div = (SDIO_FREQ/SD_CLK_50M);
- if (!(SDIO_FREQ%SD_CLK_50M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Enable high speed mode in controller
- */
- regval = sd_in16(SD_HOST_CTRL_R);
- regval |= SD_HOST_HS;
- sd_out16(SD_HOST_CTRL_R, regval);
- } else {
- /*
- * Disable SD clock and internal clock
- */
- regval = sd_in16(SD_CLK_CTL_R);
- regval &= ~(SD_CLK_SD_EN|SD_CLK_INT_EN);
- sd_out16(SD_CLK_CTL_R, regval);
-
- /*
- * Calculating clock divisor
- */
- clk_div = (SDIO_FREQ/SD_CLK_25M);
- if (!(SDIO_FREQ%SD_CLK_25M)) {
- clk_div -=1;
- }
-
- /*
- * Enable Internal clock and wait for it to stabilize
- */
- regval = (clk_div << SD_DIV_SHIFT) | SD_CLK_INT_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- do {
- regval = sd_in16(SD_CLK_CTL_R);
- } while (!(regval & SD_CLK_INT_STABLE));
-
- /*
- * Enable SD clock
- */
- regval |= SD_CLK_SD_EN;
- sd_out16(SD_CLK_CTL_R, regval);
- }
-
- /*
- * Set R/W block length to 512
- */
- send_cmd(CMD16, SD_BLOCK_SZ, &response);
-
-fail:
- CardType = ty;
-
- return RES_OK;
-}
-#endif
-
-#endif
diff --git a/quad/zybo_fsbl/src/nand.c b/quad/zybo_fsbl/src/nand.c
deleted file mode 100644
index 7a50c35bea57061cd536ac5d94ce4aea39206095..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/nand.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nand.c
-*
-* Contains code for the NAND FLASH functionality. Bad Block management
-* is simple: skip the bad blocks and keep going.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
-* 3.00a sgd 30/01/13 Code cleanup
-* 5.00a sgd 17/05/13 Support for Multi Boot
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xparameters.h"
-#include "fsbl.h"
-#ifdef XPAR_PS7_NAND_0_BASEADDR
-#include "nand.h"
-#include "xnandps_bbm.h"
-
-
-/************************** Constant Definitions *****************************/
-
-#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
- u64 Offset,
- u32 Length);
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-extern u32 FlashOffsetAddress;
-
-XNandPs *NandInstPtr;
-XNandPs NandInstance; /* XNand Instance. */
-
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the NAND FLASH interface.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if the controller initializes correctly
-* - XST_FAILURE if the controller fails to initializes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 InitNand(void)
-{
-
- u32 Status;
- XNandPs_Config *ConfigPtr;
-
- /*
- * Set up pointers to instance and the config structure
- */
- NandInstPtr = &NandInstance;
-
- /*
- * Initialize the flash driver.
- */
- ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID);
-
- if (ConfigPtr == NULL) {
- fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
- return XST_FAILURE;
- }
-
- Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
- ConfigPtr->SmcBase,ConfigPtr->FlashBase);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"NAND intialization failed \n \r");
- return XST_FAILURE;
- }
-
- /*
- * Set up base address for access
- */
- FlashReadBaseAddress = XPS_NAND_BASEADDR;
-
- fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
- NandInstPtr->Geometry.FlashWidth);
-
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
- Status);
- return XST_FAILURE;
- }
-
- /*
- * set up the FLASH access pointers
- */
- fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the NAND FLASH interface for the Simplified header
-* functionality. This function handles bad blocks.
-*
-* The source address is the absolute good address, bad blocks are skipped
-* without incrementing the source address.
-*
-* @param SourceAddress is address in FLASH data space, absolute good address
-* @param DestinationAddress is address in OCM data space
-*
-* @return XST_SUCCESS if the transfer completes correctly
-* XST_FAILURE if the transfer fails to completes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u32 ActLen;
- u32 BlockOffset;
- u32 Block;
- u32 Status;
- u32 BytesLeft = LengthBytes;
- u32 BlockSize = NandInstPtr->Geometry.BlockSize;
- u8 *BufPtr = (u8 *)DestinationAddress;
- u32 ReadLen;
- u32 BlockReadLen;
- u32 Offset;
- u32 TmpAddress = 0 ;
- u32 BlockCount = 0;
- u32 BadBlocks = 0;
-
- /*
- * First get bad blocks before the source address
- */
- while (TmpAddress < SourceAddress) {
- while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
- XST_SUCCESS) {
- BlockCount ++;
- BadBlocks ++;
- }
-
- TmpAddress += BlockSize;
- BlockCount ++;
- }
-
- Offset = SourceAddress + BadBlocks * BlockSize;
-
- /*
- * Calculate the actual length including bad blocks
- */
- ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
-
- /*
- * Check if the actual length cross flash size
- */
- if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
- return XST_FAILURE;
- }
-
- while (BytesLeft > 0) {
- BlockOffset = Offset & (BlockSize - 1);
- Block = (Offset & ~(BlockSize - 1))/BlockSize;
- BlockReadLen = BlockSize - BlockOffset;
-
- Status = XNandPs_IsBlockBad(NandInstPtr, Block);
- if (Status == XST_SUCCESS) {
- /* Move to next block */
- Offset += BlockReadLen;
- continue;
- }
-
- /*
- * Check if we cross block boundary
- */
- if (BytesLeft < BlockReadLen) {
- ReadLen = BytesLeft;
- } else {
- ReadLen = BlockReadLen;
- }
-
- /*
- * Read from the NAND flash
- */
- Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
- if (Status != XST_SUCCESS) {
- return Status;
- }
- BytesLeft -= ReadLen;
- Offset += ReadLen;
- BufPtr += ReadLen;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the length including bad blocks from a given offset and
-* length.
-*
-* @param NandInstPtr is the pointer to the XNandPs instance.
-* @param Offset is the flash data address to read from.
-* @param Length is number of bytes to read.
-*
-* @return
-* - Return actual length including bad blocks.
-*
-* @note None.
-*
-******************************************************************************/
-static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
- u64 Offset,
- u32 Length)
-{
- u32 BlockSize = NandInstPtr->Geometry.BlockSize;
- u32 CurBlockLen;
- u32 CurBlock;
- u32 Status;
- u32 TempLen = 0;
- u32 ActLen = 0;
-
- while (TempLen < Length) {
- CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
- CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
-
- /*
- * Check if the block is bad
- */
- Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
- if (Status != XST_SUCCESS) {
- /* Good Block */
- TempLen += CurBlockLen;
- }
- ActLen += CurBlockLen;
- Offset += CurBlockLen;
- if (Offset >= NandInstPtr->Geometry.DeviceSize) {
- break;
- }
- }
-
- return ActLen;
-}
-
-#endif
diff --git a/quad/zybo_fsbl/src/nand.h b/quad/zybo_fsbl/src/nand.h
deleted file mode 100644
index a7bdb08af8284ee66f8bf7b0c8130af0027d25bd..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/nand.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nand.h
-*
-* This file contains the interface for the NAND FLASH functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___NAND_H___
-#define ___NAND_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-
-#include "smc.h"
-
-#ifdef XPAR_PS7_NAND_0_BASEADDR
-
-#include "xnandps.h"
-#include "xnandps_bbm.h"
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 InitNand(void);
-
-u32 NandAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthWords);
-#endif
-/************************** Variable Definitions *****************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___NAND_H___ */
-
diff --git a/quad/zybo_fsbl/src/nor.c b/quad/zybo_fsbl/src/nor.c
deleted file mode 100644
index 0dc6c14ec5e17ebc15ca7f2a1b69b3a336da9f47..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/nor.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nor.c
-*
-* Contains code for the NOR FLASH functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 2.00a mb 25/05/12 mio init removed
-* 3.00a sgd 30/01/13 Code cleanup
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "nor.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-
-/******************************************************************************/
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the NOR FLASH interface.
-*
-* @param None
-*
-* @return None
-*
-* @note None.
-*
-****************************************************************************/
-void InitNor(void)
-{
-
- /*
- * Set up the base address for access
- */
- FlashReadBaseAddress = XPS_NOR_BASEADDR;
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the NOR FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in OCM data space
-* @param LengthBytes is the data length to transfer in bytes
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u32 Data;
- u32 Count;
- u32 *SourceAddr;
- u32 *DestAddr;
- u32 LengthWords;
-
- /*
- * check for non-word tail
- * add bytes to cover the end
- */
- if ((LengthBytes%4) != 0){
-
- LengthBytes += (4 - (LengthBytes & 0x00000003));
- }
-
- LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
-
- SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
- DestAddr = (u32 *)(DestinationAddress);
-
- /*
- * Word transfers, endianism isn't an issue
- */
- for (Count=0; Count < LengthWords; Count++){
-
- Data = Xil_In32((u32)(SourceAddr++));
- Xil_Out32((u32)(DestAddr++), Data);
- }
-
- return XST_SUCCESS;
-}
-
diff --git a/quad/zybo_fsbl/src/nor.h b/quad/zybo_fsbl/src/nor.h
deleted file mode 100644
index 8e5fe0b6ab1f05225e0f9632b10f5c6419cc64c5..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/nor.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file nor.h
-*
-* This file contains the interface for the NOR FLASH functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___NOR_H___
-#define ___NOR_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-
-#include "smc.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-
-void InitNor(void);
-
-u32 NorAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___NOR_H___ */
-
diff --git a/quad/zybo_fsbl/src/pcap.c b/quad/zybo_fsbl/src/pcap.c
deleted file mode 100644
index 50bebab3829103dfdc8ae08aa1284a5c00dcf4f3..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/pcap.c
+++ /dev/null
@@ -1,655 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file pcap.c
-*
-* Contains code for enabling and accessing the PCAP
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 02/10/10 Initial release
-* 2.00a jz 05/28/11 Add SD support
-* 2.00a mb 25/05/12 using the EDK provided devcfg driver
-* Nand/SD encryption and review comments
-* 3.00a mb 16/08/12 Added the poll function
-* Removed the FPGA_RST_CTRL define
-* Added the flag for NON PS instantiated bitstream
-* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
-* fabric_init()
-* Fix for CR#689026 - FSBL doesn't hold PL resets active
-* during bit download
-* Fix for CR#699475 - FSBL functionality is broken and
-* its not able to boot in QSPI/NAND
-* bootmode
-* Fix for CR#705664 - FSBL fails to decrypt the
-* bitstream when the image is AES
-* encrypted using non-zero key value
-* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "pcap.h"
-#include "nand.h" /* For NAND geometry information */
-#include "fsbl.h"
-#include "image_mover.h" /* For MoveImage */
-#include "xparameters.h"
-#include "xil_exception.h"
-#include "xdevcfg.h"
-#include "sleep.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-/************************** Constant Definitions *****************************/
-/*
- * The following constants map to the XPAR parameters created in the
- * xparameters.h file. They are only defined here such that a user can easily
- * change all the needed parameters in one place.
- */
-
-#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
-
-/************************** Variable Definitions *****************************/
-/* Devcfg driver instance */
-static XDcfg DcfgInstance;
-XDcfg *DcfgInstPtr;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-/******************************************************************************/
-/**
-*
-* This function transfer data using PCAP
-*
-* @param SourceDataPtr is a pointer to where the data is read from
-* @param DestinationDataPtr is a pointer to where the data is written to
-* @param SourceLength is the length of the data to be moved in words
-* @param DestinationLength is the length of the data to be moved in words
-* @param SecureTransfer indicated the encryption key location, 0 for
-* non-encrypted
-*
-* @return
-* - XST_SUCCESS if the transfer is successful
-* - XST_FAILURE if the transfer fails
-*
-* @note None
-*
-****************************************************************************/
-u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
- u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
-{
- u32 Status;
- u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
-
- /*
- * Check for secure transfer
- */
- if (SecureTransfer) {
- PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
- }
-
-#ifdef FSBL_PERF
- XTime tXferCur = 0;
- FsblGetGlobalTime(tXferCur);
-#endif
-
- /*
- * Clear the PCAP status registers
- */
- Status = ClearPcapStatus();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
- return XST_FAILURE;
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * PCAP single DMA transfer setup
- */
- SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
- DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
-
- /*
- * Transfer using Device Configuration
- */
- Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
- SourceLength,
- (u8 *)DestinationDataPtr,
- DestinationLength, PcapTransferType);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
- return XST_FAILURE;
- }
-
- /*
- * Dump the PCAP registers
- */
- PcapDumpRegisters();
-
- /*
- * Poll for the DMA done
- */
- Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tXferEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Time taken is ");
- FsblMeasurePerfTime(tXferCur,tXferEnd);
-#endif
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function loads PL partition using PCAP
-*
-* @param SourceDataPtr is a pointer to where the data is read from
-* @param DestinationDataPtr is a pointer to where the data is written to
-* @param SourceLength is the length of the data to be moved in words
-* @param DestinationLength is the length of the data to be moved in words
-* @param SecureTransfer indicated the encryption key location, 0 for
-* non-encrypted
-*
-* @return
-* - XST_SUCCESS if the transfer is successful
-* - XST_FAILURE if the transfer fails
-*
-* @note None
-*
-****************************************************************************/
-u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
- u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
-{
- u32 Status;
- u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
-
- /*
- * Check for secure transfer
- */
- if (SecureTransfer) {
- PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
- }
-
-#ifdef FSBL_PERF
- XTime tXferCur = 0;
- FsblGetGlobalTime(tXferCur);
-#endif
-
- /*
- * Clear the PCAP status registers
- */
- Status = ClearPcapStatus();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
- return XST_FAILURE;
- }
-
- /*
- * For Bitstream case destination address will be 0xFFFFFFFF
- */
- DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
-
- /*
- * New Bitstream download initialization sequence
- */
- FabricInit();
-
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * PCAP single DMA transfer setup
- */
- SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
- DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
-
- /*
- * Transfer using Device Configuration
- */
- Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
- SourceLength,
- (u8 *)DestinationDataPtr,
- DestinationLength, PcapTransferType);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %d \r \n",Status);
- return XST_FAILURE;
- }
-
-
- /*
- * Dump the PCAP registers
- */
- PcapDumpRegisters();
-
-
- /*
- * Poll for the DMA done
- */
- Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
-
- /*
- * Poll for FPGA Done
- */
- Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tXferEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Time taken is ");
- FsblMeasurePerfTime(tXferCur,tXferEnd);
-#endif
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Initializes the PCAP driver.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if the pcap driver initialization is successful
-* - XST_FAILURE if the pcap driver initialization fails
-*
-* @note none
-*
-****************************************************************************/
-int InitPcap(void)
-{
- XDcfg_Config *ConfigPtr;
- int Status = XST_SUCCESS;
- DcfgInstPtr = &DcfgInstance;
-
- /*
- * Initialize the Device Configuration Interface driver.
- */
- ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
-
- Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
- ConfigPtr->BaseAddr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function programs the Fabric for use.
-*
-* @param None
-*
-* @return None
-* - XST_SUCCESS if the Fabric initialization is successful
-* - XST_FAILURE if the Fabric initialization fails
-* @note None
-*
-****************************************************************************/
-void FabricInit(void)
-{
- u32 PcapReg;
- u32 StatusReg;
-
- /*
- * Set Level Shifters DT618760 - PS to PL enabling
- */
- Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
- fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%x \r\n",
- Xil_In32(PS_LVL_SHFTR_EN));
-
- /*
- * Get DEVCFG controller settings
- */
- PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * 5msec delay
- */
- usleep(5000);
- /*
- * Setting PCFG_PROG_B signal to low
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * 5msec delay
- */
- usleep(5000);
- /*
- * Polling the PCAP_INIT status for Reset
- */
- while(XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK);
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Polling the PCAP_INIT status for Set
- */
- while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK));
-
- /*
- * Get Device configuration status
- */
- StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
- fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%x \r\n",StatusReg);
-
- fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
-}
-
-/******************************************************************************/
-/**
-*
-* This function Clears the PCAP status registers.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the pcap status registers are cleared
-* - XST_FAILURE if errors are there
-* - XST_DEVICE_BUSY if Pcap device is busy
-* @note None
-*
-****************************************************************************/
-u32 ClearPcapStatus(void)
-{
-
- u32 StatusReg;
- u32 IntStatusReg;
-
- /*
- * Clear it all, so if Boot ROM comes back, it can proceed
- */
- XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
-
- /*
- * Get PCAP Interrupt Status Register
- */
- IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
- IntStatusReg);
- return XST_FAILURE;
- }
-
- /*
- * Read the PCAP status register for DMA status
- */
- StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
-
- fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8x\r\n", StatusReg);
-
- /*
- * If the queue is full, return w/ XST_DEVICE_BUSY
- */
- if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
- XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
-
- fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
- return XST_DEVICE_BUSY;
- }
-
- fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
-
- /*
- * There are unacknowledged DMA commands outstanding
- */
- if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
- XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
-
- IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
-
- if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
- XDCFG_IXR_DMA_DONE_MASK){
- /*
- * Error state, transfer cannot occur
- */
- fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
- return XST_FAILURE;
- }
- else {
- /*
- * clear out the status
- */
- XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
- }
- }
-
- if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
- XDcfg_IntrClear(DcfgInstPtr, StatusReg &
- XDCFG_STATUS_DMA_DONE_CNT_MASK);
- }
-
- fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function prints PCAP register status.
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-****************************************************************************/
-void PcapDumpRegisters (void) {
-
- fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
-
- fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08x\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
-}
-
-/******************************************************************************/
-/**
-*
-* This function Polls for the DMA done or FPGA done.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if polling for DMA/FPGA done is successful
-* - XST_FAILURE if polling for DMA/FPGA done fails
-*
-* @note none
-*
-****************************************************************************/
-int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
-{
- int Count = MaxCount;
- u32 IntrStsReg = 0;
-
- /*
- * poll for the DMA done
- */
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- while ((IntrStsReg & MaskValue) !=
- MaskValue) {
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- Count -=1;
-
- if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %x\r\n",
- IntrStsReg);
- PcapDumpRegisters();
- return XST_FAILURE;
- }
-
- if(!Count) {
- fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
- return XST_FAILURE;
- }
- if (Count > (MAX_COUNT-100)) {
- fsbl_printf(DEBUG_GENERAL,".");
- }
- }
-
- fsbl_printf(DEBUG_GENERAL,"\n\r");
-
- XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
-
- return XST_SUCCESS;
-}
-
diff --git a/quad/zybo_fsbl/src/pcap.h b/quad/zybo_fsbl/src/pcap.h
deleted file mode 100644
index b0242d78fb5e2783921a263de06af9f71829985c..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/pcap.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file pcap.h
-*
-* This file contains the interface for intiializing and accessing the PCAP
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 02/10/10 Initial release
-* 2.00a mb 16/08/12 Added the macros and function prototypes
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___PCAP_H___
-#define ___PCAP_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xdevcfg.h"
-
-/************************** Function Prototypes ******************************/
-
-
-/* Multiboot register offset mask */
-#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
-#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
-
-#define PCAP_LAST_TRANSFER 1
-#define MAX_COUNT 1000000000
-#define LVL_PL_PS 0x0000000F
-#define LVL_PS_PL 0x0000000A
-
-/* Fix for #672779 */
-#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-int InitPcap(void);
-void PcapDumpRegisters(void);
-u32 ClearPcapStatus(void);
-void FabricInit(void);
-int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
-u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
- u32 DestinationLength, u32 Flags);
-u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
- u32 DestinationLength, u32 Flags);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___PCAP_H___ */
-
diff --git a/quad/zybo_fsbl/src/ps7_init.c b/quad/zybo_fsbl/src/ps7_init.c
deleted file mode 100644
index 182b94b57bd1df0e3e0ca275aca23631f9375d65..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/ps7_init.c
+++ /dev/null
@@ -1,12655 +0,0 @@
- /******************************************************************************
- *
- * (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
- *
- * This file contains confidential and proprietary information of Xilinx, Inc.
- * and is protected under U.S. and international copyright and other
- * intellectual property laws.
- *
- * DISCLAIMER
- * This disclaimer is not a license and does not grant any rights to the
- * materials distributed herewith. Except as otherwise provided in a valid
- * license issued to you by Xilinx, and to the maximum extent permitted by
- * applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND WITH ALL
- * FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
- * IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
- * MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
- * and (2) Xilinx shall not be liable (whether in contract or tort, including
- * negligence, or under any other theory of liability) for any loss or damage
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- * materials, including for any direct, or any indirect, special, incidental,
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- * a third party) even if such damage or loss was reasonably foreseeable or
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- * CRITICAL APPLICATIONS
- * Xilinx products are not designed or intended to be fail-safe, or for use in
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- * safety devices or systems, Class III medical devices, nuclear facilities,
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- * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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- ******************************************************************************/
- /****************************************************************************/
- /**
- *
- * @file ps7_init.c
- *
- * This file is automatically generated
- *
- *****************************************************************************/
-
- #include "ps7_init.h"
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x3
- // .. ==> 0XF8000180[5:4] = 0x00000003U
- // .. ==> MASK : 0x00000030U VAL : 0x00000030U
- // .. DIVISOR0 = 0x6
- // .. ==> 0XF8000180[13:8] = 0x00000006U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000600U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
- // .. SRCSEL = 0x2
- // .. ==> 0XF8000190[5:4] = 0x00000002U
- // .. ==> MASK : 0x00000030U VAL : 0x00000020U
- // .. DIVISOR0 = 0x35
- // .. ==> 0XF8000190[13:8] = 0x00000035U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003500U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000190[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF80001A0[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x101
- // .. .. ==> 0XF8006034[13:4] = 0x00000101U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. FINISH: DDR INITIALIZATION
- // .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. CORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. UNCORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. STAT_NUM_CORR_ERR = 0x0
- // .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. STAT_NUM_UNCORR_ERR = 0x0
- // .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. reg_ddrc_ecc_mode = 0x0
- // .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. reg_ddrc_dis_scrub = 0x1
- // .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. reg_phy_dif_on = 0x0
- // .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. reg_phy_dif_off = 0x0
- // .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x92
- // .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. reg_phy_loopback = 0x0
- // .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_phy_bl2 = 0x0
- // .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_at_spd_atpg = 0x0
- // .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_bist_enable = 0x0
- // .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_bist_force_err = 0x0
- // .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_bist_mode = 0x0
- // .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reg_phy_invert_clkout = 0x1
- // .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reg_phy_sel_logic = 0x0
- // .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_ratio = 0x100
- // .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. reg_phy_ctrl_slave_force = 0x0
- // .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. reg_phy_use_rank0_delays = 0x1
- // .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. reg_phy_lpddr = 0x0
- // .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. reg_phy_cmd_latency = 0x0
- // .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. reg_phy_int_lpbk = 0x0
- // .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. reg_phy_wr_rl_delay = 0x2
- // .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. reg_phy_rd_rl_delay = 0x4
- // .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. reg_phy_dll_lock_diff = 0xf
- // .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. reg_phy_use_wr_level = 0x1
- // .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. reg_phy_use_rd_data_eye_level = 0x1
- // .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reg_phy_dis_calib_rst = 0x0
- // .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. reg_arb_page_addr_mask = 0x0
- // .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. reg_ddrc_lpddr2 = 0x0
- // .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_ddrc_per_bank_refresh = 0x0
- // .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_derate_enable = 0x0
- // .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_ddrc_mr4_margin = 0x0
- // .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. reg_ddrc_mr4_read_interval = 0x0
- // .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. reg_ddrc_t_mrw = 0x5
- // .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. START: POLL ON DCI STATUS
- // .. DONE = 1
- // .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. FINISH: POLL ON DCI STATUS
- // .. START: UNLOCK DDR
- // .. reg_ddrc_soft_rstb = 0x1
- // .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_ddrc_powerdown_en = 0x0
- // .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_data_bus_width = 0x0
- // .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. reg_ddrc_burst8_refresh = 0x0
- // .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. reg_ddrc_rdwr_idle_gap = 1
- // .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. reg_ddrc_dis_rd_bypass = 0x0
- // .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. reg_ddrc_dis_act_bypass = 0x0
- // .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. reg_ddrc_dis_auto_refresh = 0x0
- // .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. FINISH: UNLOCK DDR
- // .. START: CHECK DDR STATUS
- // .. ddrc_reg_operating_mode = 1
- // .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. FINISH: CHECK DDR STATUS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B5C[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B5C[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x00D6861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B68[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B68[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00D6861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x5
- // .. ==> 0XE0001034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0001018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x00000009U),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x5
- // .. ==> 0XE0000034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0000018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x00000009U),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x0
- // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: I2C RESET
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 1
- // .. reserved_3 = 127
- // .. ==> 0XF8000240[31:25] = 0x0000007FU
- // .. ==> MASK : 0xFE000000U VAL : 0xFE000000U
- // .. FPGA_ACP_RST = 1
- // .. ==> 0XF8000240[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. FPGA_AXDS3_RST = 1
- // .. ==> 0XF8000240[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. FPGA_AXDS2_RST = 1
- // .. ==> 0XF8000240[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. FPGA_AXDS1_RST = 1
- // .. ==> 0XF8000240[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. FPGA_AXDS0_RST = 1
- // .. ==> 0XF8000240[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. reserved_2 = 3
- // .. ==> 0XF8000240[19:18] = 0x00000003U
- // .. ==> MASK : 0x000C0000U VAL : 0x000C0000U
- // .. FSSW1_FPGA_RST = 1
- // .. ==> 0XF8000240[17:17] = 0x00000001U
- // .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. FSSW0_FPGA_RST = 1
- // .. ==> 0XF8000240[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reserved_1 = 15
- // .. ==> 0XF8000240[15:14] = 0x0000000FU
- // .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. FPGA_FMSW1_RST = 1
- // .. ==> 0XF8000240[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. FPGA_FMSW0_RST = 1
- // .. ==> 0XF8000240[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. FPGA_DMA3_RST = 1
- // .. ==> 0XF8000240[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. FPGA_DMA2_RST = 1
- // .. ==> 0XF8000240[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. FPGA_DMA1_RST = 1
- // .. ==> 0XF8000240[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. FPGA_DMA0_RST = 1
- // .. ==> 0XF8000240[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. reserved = 15
- // .. ==> 0XF8000240[7:4] = 0x0000000FU
- // .. ==> MASK : 0x000000F0U VAL : 0x000000F0U
- // .. FPGA3_OUT_RST = 1
- // .. ==> 0XF8000240[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. FPGA2_OUT_RST = 1
- // .. ==> 0XF8000240[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. FPGA1_OUT_RST = 1
- // .. ==> 0XF8000240[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. FPGA0_OUT_RST = 1
- // .. ==> 0XF8000240[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
- // .. FINISH: FPGA RESETS TO 1
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x3
- // .. ==> 0XF8000180[5:4] = 0x00000003U
- // .. ==> MASK : 0x00000030U VAL : 0x00000030U
- // .. DIVISOR0 = 0x6
- // .. ==> 0XF8000180[13:8] = 0x00000006U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000600U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
- // .. SRCSEL = 0x2
- // .. ==> 0XF8000190[5:4] = 0x00000002U
- // .. ==> MASK : 0x00000030U VAL : 0x00000020U
- // .. DIVISOR0 = 0x35
- // .. ==> 0XF8000190[13:8] = 0x00000035U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003500U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000190[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF80001A0[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x101
- // .. .. ==> 0XF8006034[13:4] = 0x00000101U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. FINISH: DDR INITIALIZATION
- // .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. CORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. UNCORR_ECC_LOG_VALID = 0x0
- // .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. STAT_NUM_CORR_ERR = 0x0
- // .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. STAT_NUM_UNCORR_ERR = 0x0
- // .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. reg_ddrc_ecc_mode = 0x0
- // .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. reg_ddrc_dis_scrub = 0x1
- // .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. reg_phy_dif_on = 0x0
- // .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. reg_phy_dif_off = 0x0
- // .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_data_slice_in_use = 0x1
- // .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_phy_rdlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_gatelvl_inc_mode = 0x0
- // .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_wrlvl_inc_mode = 0x0
- // .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_tx = 0x0
- // .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_board_lpbk_rx = 0x0
- // .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. reg_phy_bist_shift_dq = 0x0
- // .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. reg_phy_bist_err_clr = 0x0
- // .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. reg_phy_dq_offset = 0x40
- // .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. reg_phy_wrlvl_init_ratio = 0x0
- // .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. reg_phy_gatelvl_init_ratio = 0x92
- // .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. reg_phy_rd_dqs_slave_force = 0x0
- // .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. reg_phy_wr_dqs_slave_force = 0x0
- // .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. reg_phy_fifo_we_in_force = 0x0
- // .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reg_phy_fifo_we_in_delay = 0x0
- // .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. reg_phy_wr_data_slave_force = 0x0
- // .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reg_phy_wr_data_slave_delay = 0x0
- // .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. reg_phy_loopback = 0x0
- // .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_phy_bl2 = 0x0
- // .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_phy_at_spd_atpg = 0x0
- // .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_phy_bist_enable = 0x0
- // .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. reg_phy_bist_force_err = 0x0
- // .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. reg_phy_bist_mode = 0x0
- // .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reg_phy_invert_clkout = 0x1
- // .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reg_phy_sel_logic = 0x0
- // .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_ratio = 0x100
- // .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. reg_phy_ctrl_slave_force = 0x0
- // .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. reg_phy_use_rank0_delays = 0x1
- // .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. reg_phy_lpddr = 0x0
- // .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. reg_phy_cmd_latency = 0x0
- // .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. reg_phy_int_lpbk = 0x0
- // .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. reg_phy_wr_rl_delay = 0x2
- // .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. reg_phy_rd_rl_delay = 0x4
- // .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. reg_phy_dll_lock_diff = 0xf
- // .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. reg_phy_use_wr_level = 0x1
- // .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. reg_phy_use_rd_data_eye_level = 0x1
- // .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reg_phy_dis_calib_rst = 0x0
- // .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_phy_ctrl_slave_delay = 0x0
- // .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. reg_arb_page_addr_mask = 0x0
- // .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_wr_portn = 0x3ff
- // .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_wr_portn = 0x0
- // .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_dis_rmw_portn = 0x1
- // .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. reg_arb_pri_rd_portn = 0x3ff
- // .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. reg_arb_disable_aging_rd_portn = 0x0
- // .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. reg_arb_set_hpr_rd_portn = 0x0
- // .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. reg_ddrc_lpddr2 = 0x0
- // .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. reg_ddrc_per_bank_refresh = 0x0
- // .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_derate_enable = 0x0
- // .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. reg_ddrc_mr4_margin = 0x0
- // .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. reg_ddrc_mr4_read_interval = 0x0
- // .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. reg_ddrc_t_mrw = 0x5
- // .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. START: POLL ON DCI STATUS
- // .. DONE = 1
- // .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. FINISH: POLL ON DCI STATUS
- // .. START: UNLOCK DDR
- // .. reg_ddrc_soft_rstb = 0x1
- // .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. reg_ddrc_powerdown_en = 0x0
- // .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. reg_ddrc_data_bus_width = 0x0
- // .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. reg_ddrc_burst8_refresh = 0x0
- // .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. reg_ddrc_rdwr_idle_gap = 1
- // .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. reg_ddrc_dis_rd_bypass = 0x0
- // .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. reg_ddrc_dis_act_bypass = 0x0
- // .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. reg_ddrc_dis_auto_refresh = 0x0
- // .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. FINISH: UNLOCK DDR
- // .. START: CHECK DDR STATUS
- // .. ddrc_reg_operating_mode = 1
- // .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. FINISH: CHECK DDR STATUS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B5C[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B5C[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x00D6861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x1a
- // .. ==> 0XF8000B68[18:14] = 0x0000001AU
- // .. ==> MASK : 0x0007C000U VAL : 0x00068000U
- // .. SLEW_N = 0x1a
- // .. ==> 0XF8000B68[23:19] = 0x0000001AU
- // .. ==> MASK : 0x00F80000U VAL : 0x00D00000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00D6861CU),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E60U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x5
- // .. ==> 0XE0001034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0001018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x00000009U),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x5
- // .. ==> 0XE0000034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0000018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x00000009U),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x0
- // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: I2C RESET
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 1
- // .. reserved_3 = 127
- // .. ==> 0XF8000240[31:25] = 0x0000007FU
- // .. ==> MASK : 0xFE000000U VAL : 0xFE000000U
- // .. FPGA_ACP_RST = 1
- // .. ==> 0XF8000240[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. FPGA_AXDS3_RST = 1
- // .. ==> 0XF8000240[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. FPGA_AXDS2_RST = 1
- // .. ==> 0XF8000240[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. FPGA_AXDS1_RST = 1
- // .. ==> 0XF8000240[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. FPGA_AXDS0_RST = 1
- // .. ==> 0XF8000240[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. reserved_2 = 3
- // .. ==> 0XF8000240[19:18] = 0x00000003U
- // .. ==> MASK : 0x000C0000U VAL : 0x000C0000U
- // .. FSSW1_FPGA_RST = 1
- // .. ==> 0XF8000240[17:17] = 0x00000001U
- // .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. FSSW0_FPGA_RST = 1
- // .. ==> 0XF8000240[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reserved_1 = 15
- // .. ==> 0XF8000240[15:14] = 0x0000000FU
- // .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. FPGA_FMSW1_RST = 1
- // .. ==> 0XF8000240[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. FPGA_FMSW0_RST = 1
- // .. ==> 0XF8000240[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. FPGA_DMA3_RST = 1
- // .. ==> 0XF8000240[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. FPGA_DMA2_RST = 1
- // .. ==> 0XF8000240[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. FPGA_DMA1_RST = 1
- // .. ==> 0XF8000240[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. FPGA_DMA0_RST = 1
- // .. ==> 0XF8000240[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. reserved = 15
- // .. ==> 0XF8000240[7:4] = 0x0000000FU
- // .. ==> MASK : 0x000000F0U VAL : 0x000000F0U
- // .. FPGA3_OUT_RST = 1
- // .. ==> 0XF8000240[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. FPGA2_OUT_RST = 1
- // .. ==> 0XF8000240[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. FPGA1_OUT_RST = 1
- // .. ==> 0XF8000240[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. FPGA0_OUT_RST = 1
- // .. ==> 0XF8000240[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
- // .. FINISH: FPGA RESETS TO 1
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x177
- // .. .. ==> 0XF8000110[21:12] = 0x00000177U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1a
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1db
- // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x15
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x34
- // .. ==> 0XF8000128[13:8] = 0x00000034U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003400U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x3
- // .. ==> 0XF8000180[5:4] = 0x00000003U
- // .. ==> MASK : 0x00000030U VAL : 0x00000030U
- // .. DIVISOR0 = 0x6
- // .. ==> 0XF8000180[13:8] = 0x00000006U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000600U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
- // .. SRCSEL = 0x2
- // .. ==> 0XF8000190[5:4] = 0x00000002U
- // .. ==> MASK : 0x00000030U VAL : 0x00000020U
- // .. DIVISOR0 = 0x35
- // .. ==> 0XF8000190[13:8] = 0x00000035U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003500U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000190[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF80001A0[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
- // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0x54
- // .. .. ==> 0XF8006014[13:6] = 0x00000054U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x15
- // .. .. ==> 0XF8006018[15:10] = 0x00000015U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U
- // .. .. reg_ddrc_t_ras_max = 0x23
- // .. .. ==> 0XF8006018[21:16] = 0x00000023U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x101
- // .. .. ==> 0XF8006034[13:4] = 0x00000101U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xc845
- // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U
- // .. .. dram_rstn_x1024 = 0x67
- // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8f
- // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8a
- // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x8b
- // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0x92
- // .. .. ==> 0XF8006138[19:10] = 0x00000092U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
- // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
- // .. .. ==> 0XF8006160[9:0] = 0x00000075U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
- // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
- // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
- // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
- // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbc
- // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb5
- // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B00[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFEU ,0x00000600U),
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFEU ,0x00000600U),
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFEU ,0x00000672U),
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFEU ,0x00000672U),
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFEU ,0x00000674U),
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFEU ,0x00000674U),
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFEU ,0x00000600U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x3
- // .. ==> 0XF8000B6C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x0000027FU ,0x00000260U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000000U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x001E3FC3U ,0x00000803U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF8000728[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF800072C[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x5
- // .. ==> 0XE0001034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0001018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x00000009U),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. BDIV = 0x5
- // .. ==> 0XE0000034[7:0] = 0x00000005U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000005U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000005U),
- // .. CD = 0x9
- // .. ==> 0XE0000018[15:0] = 0x00000009U
- // .. ==> MASK : 0x0000FFFFU VAL : 0x00000009U
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x00000009U),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x0
- // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: DIR MODE BANK 1
- // .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: OUTPUT ENABLE
- // .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. FINISH: I2C RESET
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 1
- // .. reserved_3 = 127
- // .. ==> 0XF8000240[31:25] = 0x0000007FU
- // .. ==> MASK : 0xFE000000U VAL : 0xFE000000U
- // .. reserved_FPGA_ACP_RST = 1
- // .. ==> 0XF8000240[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. reserved_FPGA_AXDS3_RST = 1
- // .. ==> 0XF8000240[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. reserved_FPGA_AXDS2_RST = 1
- // .. ==> 0XF8000240[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. reserved_FPGA_AXDS1_RST = 1
- // .. ==> 0XF8000240[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. reserved_FPGA_AXDS0_RST = 1
- // .. ==> 0XF8000240[20:20] = 0x00000001U
- // .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. reserved_2 = 3
- // .. ==> 0XF8000240[19:18] = 0x00000003U
- // .. ==> MASK : 0x000C0000U VAL : 0x000C0000U
- // .. reserved_FSSW1_FPGA_RST = 1
- // .. ==> 0XF8000240[17:17] = 0x00000001U
- // .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. reserved_FSSW0_FPGA_RST = 1
- // .. ==> 0XF8000240[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. reserved_1 = 15
- // .. ==> 0XF8000240[15:14] = 0x0000000FU
- // .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. reserved_FPGA_FMSW1_RST = 1
- // .. ==> 0XF8000240[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. reserved_FPGA_FMSW0_RST = 1
- // .. ==> 0XF8000240[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. reserved_FPGA_DMA3_RST = 1
- // .. ==> 0XF8000240[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. reserved_FPGA_DMA2_RST = 1
- // .. ==> 0XF8000240[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. reserved_FPGA_DMA1_RST = 1
- // .. ==> 0XF8000240[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_FPGA_DMA0_RST = 1
- // .. ==> 0XF8000240[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. reserved = 15
- // .. ==> 0XF8000240[7:4] = 0x0000000FU
- // .. ==> MASK : 0x000000F0U VAL : 0x000000F0U
- // .. FPGA3_OUT_RST = 1
- // .. ==> 0XF8000240[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. FPGA2_OUT_RST = 1
- // .. ==> 0XF8000240[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. FPGA1_OUT_RST = 1
- // .. ==> 0XF8000240[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. FPGA0_OUT_RST = 1
- // .. ==> 0XF8000240[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
- // .. FINISH: FPGA RESETS TO 1
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- int ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
diff --git a/quad/zybo_fsbl/src/ps7_init.h b/quad/zybo_fsbl/src/ps7_init.h
deleted file mode 100644
index d63682e6a8d848399e05e9962eb7473e84e4a954..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/ps7_init.h
+++ /dev/null
@@ -1,139 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define NEW_PS7_ERR_CODE 1
-
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-
-
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10159000
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 100000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 125000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 166666666
-#define I2C_FREQ 108333336
-#define WDT_FREQ 133333333
-#define TTC_FREQ 50000000
-#define CAN_FREQ 100000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 0
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 175000000
-#define FPGA2_FREQ 12288000
-#define FPGA3_FREQ 100000000
-#define C_CPU_REF_CLK_FREQ_HZ 50000000
-
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-char* getPS7MessageInfo(unsigned key);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/quad/zybo_fsbl/src/qspi.c b/quad/zybo_fsbl/src/qspi.c
deleted file mode 100644
index 6e1c15f713b79b95a46e533bfa4c05109415e5db..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/qspi.c
+++ /dev/null
@@ -1,724 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file qspi.c
-*
-* Contains code for the QSPI FLASH functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
-* are set
-* 4.00a sg 02/28/13 Cleanup
-* Removed LPBK_DLY_ADJ register setting code as we use
-* divisor 8
-* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
-* Dual Stack support
-* Fix for CR:721674 - FSBL- Failed to boot from Dual
-* stacked QSPI
-* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* Fix for CR#739711 - FSBL not able to read Large QSPI
-* (512M) in IO Mode
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "qspi.h"
-#include "image_mover.h"
-
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-#include "xqspips_hw.h"
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The following constants map to the XPAR parameters created in the
- * xparameters.h file. They are defined here such that a user can easily
- * change all the needed parameters in one place.
- */
-#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
-
-/*
- * The following constants define the commands which may be sent to the FLASH
- * device.
- */
-#define QUAD_READ_CMD 0x6B
-#define READ_ID_CMD 0x9F
-
-#define WRITE_ENABLE_CMD 0x06
-#define BANK_REG_RD 0x16
-#define BANK_REG_WR 0x17
-/* Bank register is called Extended Address Reg in Micron */
-#define EXTADD_REG_RD 0xC8
-#define EXTADD_REG_WR 0xC5
-
-#define COMMAND_OFFSET 0 /* FLASH instruction */
-#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
-#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
-#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
-#define DATA_OFFSET 4 /* Start of Data for Read/Write */
-#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
- reads */
-#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
- quad reads */
-#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
-#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
-#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
-/*
- * The following constants specify the extra bytes which are sent to the
- * FLASH on the QSPI interface, that are not data, but control information
- * which includes the command and address
- */
-#define OVERHEAD_SIZE 4
-
-/*
- * The following constants specify the max amount of data and the size of the
- * the buffer required to hold the data and overhead to transfer the data to
- * and from the FLASH.
- */
-#define DATA_SIZE 4096
-
-/*
- * The following defines are for dual flash interface.
- */
-#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
-#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
- address and return data */
-
-#define SINGLE_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_STACK_CONFIG_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-XQspiPs QspiInstance;
-XQspiPs *QspiInstancePtr;
-u32 QspiFlashSize;
-u32 QspiFlashMake;
-extern u32 FlashReadBaseAddress;
-extern u8 LinearBootDeviceFlag;
-
-/*
- * The following variables are used to read and write to the eeprom and they
- * are global to avoid having large buffers on the stack
- */
-u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
-u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
-
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the QSPI interface.
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-u32 InitQspi(void)
-{
- XQspiPs_Config *QspiConfig;
- int Status;
-
- QspiInstancePtr = &QspiInstance;
-
- /*
- * Set up the base address for access
- */
- FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
-
- /*
- * Initialize the QSPI driver so that it's ready to use
- */
- QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
- if (NULL == QspiConfig) {
- return XST_FAILURE;
- }
-
- Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
- QspiConfig->BaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Set Manual Chip select options and drive HOLD_B pin high.
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Set the prescaler for QSPI clock
- */
- XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
-
- /*
- * Read Flash ID and extract Manufacture and Size information
- */
- Status = FlashReadID();
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- if (XPAR_PS7_QSPI_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
- /*
- * For Flash size <128Mbit controller configured in linear mode
- */
- if (QspiFlashSize <= FLASH_SIZE_16MB) {
- LinearBootDeviceFlag = 1;
-
- /*
- * Enable linear mode
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Single linear read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, SINGLE_QSPI_CONFIG_QUAD_READ);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- }
- }
-
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
- /*
- * For Single Flash size <128Mbit controller configured in linear mode
- */
- if (QspiFlashSize <= FLASH_SIZE_16MB) {
- /*
- * Setting linear access flag
- */
- LinearBootDeviceFlag = 1;
-
- /*
- * Enable linear mode
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Dual linear read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_QUAD_READ);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- }
-
- /*
- * Total flash size is two time of single flash size
- */
- QspiFlashSize = 2 * QspiFlashSize;
- }
-
- /*
- * It is expected to same flash size for both chip selection
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
-
- QspiFlashSize = 2 * QspiFlashSize;
-
- /*
- * Enable two flash memories on separate buses
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_STACK_CONFIG_READ);
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* This function reads serial FLASH ID connected to the SPI interface.
-* It then deduces the make and size of the flash and obtains the
-* connection mode to point to corresponding parameters in the flash
-* configuration table. The flash driver will function based on this and
-* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
-* Winbond 128Mbit
-*
-* @param none
-*
-* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
-*
-* @note None.
-*
-******************************************************************************/
-u32 FlashReadID(void)
-{
- u32 Status;
-
- /*
- * Read ID in Auto mode.
- */
- WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
- WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
- WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
-
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- RD_ID_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
-
- fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
- ReadBuffer[2],
- ReadBuffer[3]);
-
- /*
- * Deduce flash make
- */
- if (ReadBuffer[1] == MICRON_ID) {
- QspiFlashMake = MICRON_ID;
- fsbl_printf(DEBUG_INFO, "MICRON ");
- } else if(ReadBuffer[1] == SPANSION_ID) {
- QspiFlashMake = SPANSION_ID;
- fsbl_printf(DEBUG_INFO, "SPANSION ");
- } else if(ReadBuffer[1] == WINBOND_ID) {
- QspiFlashMake = WINBOND_ID;
- fsbl_printf(DEBUG_INFO, "WINBOND ");
- }
-
- /*
- * Deduce flash Size
- */
- if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
- QspiFlashSize = FLASH_SIZE_128M;
- fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
- QspiFlashSize = FLASH_SIZE_256M;
- fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_512M) {
- QspiFlashSize = FLASH_SIZE_512M;
- fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_1G) {
- QspiFlashSize = FLASH_SIZE_1G;
- fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function reads from the serial FLASH connected to the
-* QSPI interface.
-*
-* @param Address contains the address to read data from in the FLASH.
-* @param ByteCount contains the number of bytes to read.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void FlashRead(u32 Address, u32 ByteCount)
-{
- /*
- * Setup the write command with the specified address and data for the
- * FLASH
- */
- WriteBuffer[COMMAND_OFFSET] = QUAD_READ_CMD;
- WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
- WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
- WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
-
- ByteCount += DUMMY_SIZE;
-
- /*
- * Send the read command to the FLASH to read the specified number
- * of bytes from the FLASH, send the read command and address and
- * receive the specified number of bytes of data in the data buffer
- */
- XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- ByteCount + OVERHEAD_SIZE);
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the QSPI FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in DDR data space
-* @param LengthBytes is the length of the data in Bytes
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u8 *BufferPtr;
- u32 Length = 0;
- u32 BankSel = 0;
- u32 LqspiCrReg;
- u32 Status;
- u8 BankSwitchFlag = 1;
-
- /*
- * Linear access check
- */
- if (LinearBootDeviceFlag == 1) {
- /*
- * Check for non-word tail, add bytes to cover the end
- */
- if ((LengthBytes%4) != 0){
- LengthBytes += (4 - (LengthBytes & 0x00000003));
- }
-
- memcpy((void*)DestinationAddress,
- (const void*)(SourceAddress + FlashReadBaseAddress),
- (size_t)LengthBytes);
- } else {
- /*
- * Non Linear access
- */
- BufferPtr = (u8*)DestinationAddress;
-
- /*
- * Dual parallel connection actual flash is half
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- SourceAddress = SourceAddress/2;
- }
-
- while(LengthBytes > 0) {
- /*
- * Local of DATA_SIZE size used for read/write buffer
- */
- if(LengthBytes > DATA_SIZE) {
- Length = DATA_SIZE;
- } else {
- Length = LengthBytes;
- }
-
- /*
- * Dual stack connection
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
- /*
- * Get the current LQSPI configuration value
- */
- LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
-
- /*
- * Select lower or upper Flash based on sector address
- */
- if (SourceAddress >= (QspiFlashSize/2)) {
- /*
- * Set selection to U_PAGE
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
- LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
-
- /*
- * Subtract first flash size when accessing second flash
- */
- SourceAddress = SourceAddress - (QspiFlashSize/2);
-
- fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
- }
- }
-
- /*
- * Select bank
- */
- if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
- BankSel = SourceAddress/FLASH_SIZE_16MB;
-
- fsbl_printf(DEBUG_INFO, "Bank Selection %d\n\r", BankSel);
-
- Status = SendBankSelect(BankSel);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
- return XST_FAILURE;
- }
-
- BankSwitchFlag = 0;
- }
-
- /*
- * If data to be read spans beyond the current bank, then
- * calculate length in current bank else no change in length
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- /*
- * In dual parallel mode, check should be for half
- * the length.
- */
- if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
- {
- Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
- /*
- * Above length calculated is for single flash
- * Length should be doubled since dual parallel
- */
- Length = Length * 2;
- BankSwitchFlag = 1;
- }
- } else {
- if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
- {
- Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
- BankSwitchFlag = 1;
- }
- }
-
- /*
- * Copying the image to local buffer
- */
- FlashRead(SourceAddress, Length);
-
- /*
- * Moving the data from local buffer to DDR destination address
- */
- memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
-
- /*
- * Updated the variables
- */
- LengthBytes -= Length;
-
- /*
- * For Dual parallel connection address increment should be half
- */
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- SourceAddress += Length/2;
- } else {
- SourceAddress += Length;
- }
-
- BufferPtr = (u8*)((u32)BufferPtr + Length);
- }
-
- /*
- * Reset Bank selection to zero
- */
- Status = SendBankSelect(0);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
- return XST_FAILURE;
- }
-
- if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
-
- /*
- * Reset selection to L_PAGE
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
- LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
-
- fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-
-/******************************************************************************
-*
-* This functions selects the current bank
-*
-* @param BankSel is the bank to be selected in the flash device(s).
-*
-* @return XST_SUCCESS if bank selected
-* XST_FAILURE if selection failed
-* @note None.
-*
-******************************************************************************/
-u32 SendBankSelect(u8 BankSel)
-{
- u32 Status;
-
- /*
- * bank select commands for Micron and Spansion are different
- */
- if (QspiFlashMake == MICRON_ID) {
- /*
- * For micron command WREN should be sent first
- * except for some specific feature set
- */
- WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- WRITE_ENABLE_CMD_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
- WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (QspiFlashMake == SPANSION_ID) {
- WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
- WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- /*
- * For testing - Read bank to verify
- */
- if (QspiFlashMake == SPANSION_ID) {
- WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (QspiFlashMake == MICRON_ID) {
- WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (ReadBuffer[1] != BankSel) {
- fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
- ReadBuffer[1]);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
-
diff --git a/quad/zybo_fsbl/src/qspi.h b/quad/zybo_fsbl/src/qspi.h
deleted file mode 100644
index 9bac79c382d68927fca61df4d27ae8c0219f0dac..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/qspi.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file qspi.h
-*
-* This file contains the interface for the QSPI FLASH functionality
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
-* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
-* Dual Stack support
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___QSPI_H___
-#define ___QSPI_H___
-
-#include "fsbl.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define SINGLE_FLASH_CONNECTION 0
-#define DUAL_STACK_CONNECTION 1
-#define DUAL_PARALLEL_CONNECTION 2
-#define FLASH_SIZE_16MB 0x1000000
-
-/*
- * Bank mask
- */
-#define BANKMASK 0xF000000
-
-/*
- * Identification of Flash
- * Micron:
- * Byte 0 is Manufacturer ID;
- * Byte 1 is first byte of Device ID - 0xBB or 0xBA
- * Byte 2 is second byte of Device ID describes flash size:
- * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
- * Spansion:
- * Byte 0 is Manufacturer ID;
- * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
- * Byte 2 is second byte of Device ID describes flash size:
- * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
- */
-
-#define MICRON_ID 0x20
-#define SPANSION_ID 0x01
-#define WINBOND_ID 0xEF
-
-#define FLASH_SIZE_ID_128M 0x18
-#define FLASH_SIZE_ID_256M 0x19
-#define FLASH_SIZE_ID_512M 0x20
-#define FLASH_SIZE_ID_1G 0x21
-
-/*
- * Size in bytes
- */
-#define FLASH_SIZE_128M 0x1000000
-#define FLASH_SIZE_256M 0x2000000
-#define FLASH_SIZE_512M 0x4000000
-#define FLASH_SIZE_1G 0x8000000
-
-/************************** Function Prototypes ******************************/
-u32 InitQspi(void);
-
-u32 QspiAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-u32 FlashReadID(void);
-u32 SendBankSelect(u8 BankSel);
-/************************** Variable Definitions *****************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___QSPI_H___ */
-
diff --git a/quad/zybo_fsbl/src/rsa.c b/quad/zybo_fsbl/src/rsa.c
deleted file mode 100644
index 1f43b605330bc6b1c4ef6a03be409cff4c5fb034..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/rsa.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file rsa.c
-*
-* Contains code for the RSA authentication
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.00a sgd 02/28/13 Initial release
-* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
-* Fix for CR#724165 - Partition Header used by FSBL is
-* not authenticated
-* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
-* by Boot ROM for authenticating
-* the Partition images
-* Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "rsa.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-
-/************************** Variable Definitions *****************************/
-
-#ifdef RSA_SUPPORT
-static u8 *PpkModular;
-static u8 *PpkModularEx;
-static u32 PpkExp;
-
-
-extern u32 FsblLength;
-
-void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
-{
-#ifdef FSBL_DEBUG_RSA
- int Index;
- fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
- for (Index=0;Index<Len;Index++)
- {
- fsbl_printf(DEBUG_INFO, "%02x",Buf[Index]);
- if ((Index+1)%16 == 0){
- fsbl_printf(DEBUG_INFO, "\r\n");
- }
- }
- fsbl_printf(DEBUG_INFO, "\r\n %s END\r\n",Str);
-#endif
- return;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function is used to set ppk pointer to ppk in OCM
-*
-* @param None
-*
-* @return
-*
-* @note None
-*
-******************************************************************************/
-
-void SetPpk(void )
-{
- u32 PadSize;
- u8 *PpkPtr;
-
- /*
- * Set PpkPtr to PPK in OCM
- */
-
- /*
- * Skip FSBL Length
- */
- PpkPtr = (u8 *)(FsblLength);
- /*
- * Skip to 64 byte Boundary
- */
- PadSize = ((u32)PpkPtr % 64);
- if(PadSize != 0)
- {
- PpkPtr += (64 - PadSize);
- }
-
- /*
- * Increment the pointer by authentication Header size
- */
- PpkPtr += RSA_HEADER_SIZE;
-
- /*
- * Increment the pointer by Magic word size
- */
- PpkPtr += RSA_MAGIC_WORD_SIZE;
-
- /*
- * Set pointer to PPK
- */
- PpkModular = (u8 *)PpkPtr;
- PpkPtr += RSA_PPK_MODULAR_SIZE;
- PpkModularEx = (u8 *)PpkPtr;
- PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
- PpkExp = *((u32 *)PpkPtr);
-
- return;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function Authenticate Partition Signature
-*
-* @param Partition header pointer
-*
-* @return
-* - XST_SUCCESS if Authentication passed
-* - XST_FAILURE if Authentication failed
-*
-* @note None
-*
-******************************************************************************/
-u32 AuthenticatePartition(u8 *Buffer, u32 Size)
-{
- u8 DecryptSignature[256];
- u8 HashSignature[32];
- u8 *SpkModular;
- u8 *SpkModularEx;
- u32 SpkExp;
- u8 *SignaturePtr;
- u32 Status;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * Point to Authentication Certificate
- */
- SignaturePtr = (u8 *)(Buffer + Size - RSA_SIGNATURE_SIZE);
-
- /*
- * Increment the pointer by authentication Header size
- */
- SignaturePtr += RSA_HEADER_SIZE;
-
- /*
- * Increment the pointer by Magic word size
- */
- SignaturePtr += RSA_MAGIC_WORD_SIZE;
-
- /*
- * Increment the pointer beyond the PPK
- */
- SignaturePtr += RSA_PPK_MODULAR_SIZE;
- SignaturePtr += RSA_PPK_MODULAR_EXT_SIZE;
- SignaturePtr += RSA_PPK_EXPO_SIZE;
-
- /*
- * Calculate Hash Signature
- */
- sha_256((u8 *)SignaturePtr, (RSA_SPK_MODULAR_EXT_SIZE +
- RSA_SPK_EXPO_SIZE + RSA_SPK_MODULAR_SIZE),
- HashSignature);
- FsblPrintArray(HashSignature, 32, "SPK Hash Calculated");
-
- /*
- * Extract SPK signature
- */
- SpkModular = (u8 *)SignaturePtr;
- SignaturePtr += RSA_SPK_MODULAR_SIZE;
- SpkModularEx = (u8 *)SignaturePtr;
- SignaturePtr += RSA_SPK_MODULAR_EXT_SIZE;
- SpkExp = *((u32 *)SignaturePtr);
- SignaturePtr += RSA_SPK_EXPO_SIZE;
-
- /*
- * Decrypt SPK Signature
- */
- rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
- (RSA_NUMBER)SignaturePtr,
- (u32)PpkExp,
- (RSA_NUMBER)PpkModular,
- (RSA_NUMBER)PpkModularEx);
- FsblPrintArray(DecryptSignature, RSA_SPK_SIGNATURE_SIZE,
- "SPK Decrypted Hash");
-
-
- Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Partition SPK Signature "
- "Authentication failed\r\n");
- return XST_FAILURE;
- }
- SignaturePtr += RSA_SPK_SIGNATURE_SIZE;
-
- /*
- * Decrypt Partition Signature
- */
- rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
- (RSA_NUMBER)SignaturePtr,
- (u32)SpkExp,
- (RSA_NUMBER)SpkModular,
- (RSA_NUMBER)SpkModularEx);
- FsblPrintArray(DecryptSignature, RSA_PARTITION_SIGNATURE_SIZE,
- "Partition Decrypted Hash");
-
- /*
- * Partition Authentication
- * Calculate Hash Signature
- */
- sha_256((u8 *)Buffer,
- (Size - RSA_PARTITION_SIGNATURE_SIZE),
- HashSignature);
- FsblPrintArray(HashSignature, 32,
- "Partition Hash Calculated");
-
- Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Partition Signature "
- "Authentication failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function recreates the and check signature
-*
-* @param Partition signature
-* @param Partition hash value which includes boot header, partition data
-* @return
-* - XST_SUCCESS if check passed
-* - XST_FAILURE if check failed
-*
-* @note None
-*
-******************************************************************************/
-u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash)
-{
- u8 T_padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
- 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
- u8 * pad_ptr = signature + 256;
- u32 pad = 256 - 3 - 19 - 32;
- u32 ii;
-
- /*
- * Re-Create PKCS#1v1.5 Padding
- * MSB ----------------------------------------------------LSB
- * 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
- */
- if (*--pad_ptr != 0x00 || *--pad_ptr != 0x01) {
- return XST_FAILURE;
- }
-
- for (ii = 0; ii < pad; ii++) {
- if (*--pad_ptr != 0xFF) {
- return XST_FAILURE;
- }
- }
-
- if (*--pad_ptr != 0x00) {
- return XST_FAILURE;
- }
-
- for (ii = 0; ii < sizeof(T_padding); ii++) {
- if (*--pad_ptr != T_padding[ii]) {
- return XST_FAILURE;
- }
- }
-
- for (ii = 0; ii < 32; ii++) {
- if (*--pad_ptr != hash[ii])
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
diff --git a/quad/zybo_fsbl/src/rsa.h b/quad/zybo_fsbl/src/rsa.h
deleted file mode 100644
index bb1c5f37adeb8b5337cc9c268f06607d0e5463af..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/rsa.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file rsa.h
-*
-* This file contains the RSA algorithm functions
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.00a sg 02/28/13 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___RSA_H___
-#define ___RSA_H___
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************************** Include Files *********************************/
-
-/*
- * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
- * 32-bit digits are approximately 4 times faster
- */
-
-//#define RSA_DIGIT_16
-#define RSA_DIGIT_32
-
-/*
- * RSA loop unrolling selection
- * RSA main loop can be unrolled 2, 4 or 8 ways
- */
-#define RSA_UNROLL 1
-
-/*
- * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
- */
-//#define RSA_ARM_OPTIMIZED
-
-/*
- * Check the compatibility of the selection
- */
-#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
- #error Please select a digit size
-#endif
-#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
- #error Please select just one digit size
-#endif
-#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
- #error Assembly level code is only supported for the GCC/ARM combination
-#endif
-#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
- #error Only 1, 2, 4, and 8 unrolling are supported
-#endif
-
-#ifdef RSA_DIGIT_16
-#define RSA_DIGIT unsigned short
-#define RSA_SDIGIT short
-#define RSA_DDIGIT unsigned long
-#endif
-#ifdef RSA_DIGIT_32
-#define RSA_DIGIT unsigned long
-#define RSA_SDIGIT long
-#define RSA_DDIGIT unsigned long long
-#endif
-
-#define RSA_NUMBER RSA_DIGIT *
-#define RSA_NBITS 2048
-#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
-#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
-
-/*
- * Double-digit to single digit conversion
- */
-#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
-#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
-
-#define SHA_BLKSIZE 512
-#define SHA_BLKBYTES (SHA_BLKSIZE/8)
-#define SHA_BLKWORDS (SHA_BLKBYTES/4)
-
-#define SHA_VALSIZE 256
-#define SHA_VALBYTES (SHA_VALSIZE/8)
-#define SHA_VALWORDS (SHA_VALBYTES/4)
-
-#define RSA_PPK_MODULAR_SIZE 256
-#define RSA_PPK_MODULAR_EXT_SIZE 256
-#define RSA_PPK_EXPO_SIZE 64
-#define RSA_SPK_MODULAR_SIZE 256
-#define RSA_SPK_MODULAR_EXT_SIZE 256
-#define RSA_SPK_EXPO_SIZE 64
-#define RSA_SPK_SIGNATURE_SIZE 256
-#define RSA_PARTITION_SIGNATURE_SIZE 256
-#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
-#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
-#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
-
-/*
- * SHA-256 context structure
- * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
- * total byte length counter (used both to manage the buffer and for padding)
- */
-typedef struct
-{
- unsigned int state[8];
- unsigned char buffer[SHA_BLKBYTES];
- unsigned long long bytes;
-} sha2_context;
-
-/*
- * RSA-2048 user interfaces
- */
-void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
- const unsigned char *modular_ext, const unsigned char *exponent,
- unsigned char *result);
-void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
- unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
-
-/*
- * SHA-256 user interfaces
- */
-void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
-void sha2_starts(sha2_context *ctx);
-void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
-void sha2_finish(sha2_context *ctx, unsigned char* output);
-
-/*
- * Preprocessing interface (pre-computation of R*R mod M)
- */
-void modular_ext(const unsigned char *modular, unsigned char *res);
-
-void SetPpk(void );
-u32 AuthenticatePartition(u8 *Buffer, u32 Size);
-u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___RSA_H___ */
diff --git a/quad/zybo_fsbl/src/sd.c b/quad/zybo_fsbl/src/sd.c
deleted file mode 100644
index b0e4b9ca34c35147259b83a15f7a2d7f63e12578..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/sd.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file sd.c
-*
-* Contains code for the SD card FLASH functionality.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 04/28/11 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xparameters.h"
-#include "fsbl.h"
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-#include "xstatus.h"
-
-#include "ff.h"
-#include "sd.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-
-
-static FIL fil; /* File object */
-static FATFS fatfs;
-static char buffer[32];
-static char *boot_file = buffer;
-
-/******************************************************************************/
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the SD FLASH interface.
-*
-* @param filename of the file that is to be used
-*
-* @return
-* - XST_SUCCESS if the controller initializes correctly
-* - XST_FAILURE if the controller fails to initializes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 InitSD(const char *filename)
-{
-
- FRESULT rc;
-
- /* Register volume work area, initialize device */
- rc = f_mount(0, &fatfs);
- fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
-
- if (rc != FR_OK) {
- return XST_FAILURE;
- }
-
- strcpy_rom(buffer, filename);
- boot_file = (char *)buffer;
- FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
-
- rc = f_open(&fil, boot_file, FA_READ);
- if (rc) {
- fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the SD FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in OCM data space
-* @param LengthBytes is the number of bytes to move
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
-
- FRESULT rc; /* Result code */
- UINT br;
-
- rc = f_lseek(&fil, SourceAddress);
- if (rc) {
- fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %x\n", SourceAddress);
- return XST_FAILURE;
- }
-
- rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
-
- if (rc) {
- fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
- }
-
- return XST_SUCCESS;
-
-} /* End of SDAccess */
-
-
-/******************************************************************************/
-/**
-*
-* This function closes the file object
-*
-* @param None
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void ReleaseSD(void) {
-
- f_close(&fil);
- return;
-
-
-}
-#endif
-
-
diff --git a/quad/zybo_fsbl/src/sd.h b/quad/zybo_fsbl/src/sd.h
deleted file mode 100644
index 9de76281fcca143a55476b5e3002a146ee8a30c4..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/sd.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-*******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file sd.h
-*
-* This file contains the interface for the Secure Digital (SD) card
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a bh 03/10/11 Initial release
-*
-* </pre>
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___SD_H___
-#define ___SD_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef XPAR_PS7_SD_0_S_AXI_BASEADDR
-u32 InitSD(const char *);
-
-u32 SDAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthWords);
-
-void ReleaseSD(void);
-#endif
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___SD_H___ */
-
diff --git a/quad/zybo_fsbl/src/sd_hardware.h b/quad/zybo_fsbl/src/sd_hardware.h
deleted file mode 100644
index 16872f4f9257779db8d3a9c2c67aa4106f6befb1..0000000000000000000000000000000000000000
--- a/quad/zybo_fsbl/src/sd_hardware.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/******************************************************************************
-*
-* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file sd_hardware.h
-*
-* Controller register and bit definitions
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a bh 02/01/11 Initial version,
-* </pre>
-*
-* @note None.
-*
-******************************************************************************/
-#ifndef __SD_HARDWARE_H__
-#define __SD_HARDWARE_H__
-
-#define SD_BLOCK_SZ 0x200
-#define SD_CLK_400K 400000
-#define SD_CLK_50M 50000000
-#define SD_CLK_25M 25000000
-#define SD_HS_SUPPORT 0x2
-#define SD_4BIT_SUPPORT 0x5
-
-#define SD_DMA_ADDR_R 0x00
-#define SD_BLOCK_SZ_R 0x04
-#define SD_BLOCK_CNT_R 0x06
-
-#define SD_ARG_R 0x08
-
-#define SD_TRNS_MODE_R 0x0C
-#define SD_TRNS_DMA 0x01
-#define SD_TRNS_BLK_CNT_EN 0x02
-#define SD_TRNS_ACMD12 0x04
-#define SD_TRNS_READ 0x10
-#define SD_TRNS_MULTI 0x20
-
-#define SD_CMD_R 0x0E
-#define SD_CMD_RESP_NONE 0x00
-#define SD_CMD_RESP_136 0x01
-#define SD_CMD_RESP_48 0x02
-#define SD_CMD_RESP_48_BUSY 0x03
-#define SD_CMD_CRC 0x08
-#define SD_CMD_INDEX 0x10
-#define SD_CMD_DATA 0x20
-
-#define SD_RSP_R 0x10
-
-#define SD_BUFF_R 0x20
-
-#define SD_PRES_STATE_R 0x24
-#define SD_CMD_INHIBIT 0x00000001
-#define SD_DATA_INHIBIT 0x00000002
-#define SD_WRITE_ACTIVE 0x00000100
-#define SD_READ_ACTIVE 0x00000200
-#define SD_CARD_INS 0x00010000
-#define SD_CARD_WP 0x00080000
-
-#define SD_HOST_CTRL_R 0x28
-#define SD_HOST_4BIT 0x02
-#define SD_HOST_HS 0x04
-#define SD_HOST_ADMA1 0x08
-#define SD_HOST_ADMA2 0x10
-
-#define SD_PWR_CTRL_R 0x29
-#define SD_POWER_ON 0x01
-#define SD_POWER_18 0x0A
-#define SD_POWER_30 0x0C
-#define SD_POWER_33 0x0E
-
-#define SD_BLCK_GAP_CTL_R 0x2A
-
-#define SD_WAKE_CTL_R 0x2B
-
-#define SD_CLK_CTL_R 0x2C
-#define SD_DIV_SHIFT 8
-#define SD_CLK_SD_EN 0x0004
-#define SD_CLK_INT_STABLE 0x0002
-#define SD_CLK_INT_EN 0x0001
-
-#define SD_TIMEOUT_CTL_R 0x2E
-
-#define SD_SOFT_RST_R 0x2F
-#define SD_RST_ALL 0x01
-#define SD_RST_CMD 0x02
-#define SD_RST_DATA 0x04
-
-#define SD_INT_STAT_R 0x30
-#define SD_INT_ENA_R 0x34
-#define SD_SIG_ENA_R 0x38
-#define SD_INT_CMD_CMPL 0x00000001
-#define SD_INT_TRNS_CMPL 0x00000002
-#define SD_INT_DMA 0x00000008
-#define SD_INT_ERROR 0x00008000
-#define SD_INT_ERR_CTIMEOUT 0x00010000
-#define SD_INT_ERR_CCRC 0x00020000
-#define SD_INT_ERR_CEB 0x00040000
-#define SD_INT_ERR_IDX 0x00080000
-#define SD_INT_ERR_DTIMEOUT 0x00100000
-#define SD_INT_ERR_DCRC 0x00200000
-#define SD_INT_ERR_DEB 0x00400000
-#define SD_INT_ERR_CLMT 0x00800000
-#define SD_INT_ERR_ACMD12 0x01000000
-#define SD_INT_ERR_ADMA 0x02000000
-#define SD_INT_ERR_TRESP 0x10000000
-
-#define SD_CAPABILITIES_R 0x40
-
-#define SD_ADMA_ADDR_R 0x58
-#define DESC_ATBR_VALID (0x1 << 0)
-#define DESC_ATBR_END (0x1 << 1)
-#define DESC_ATBR_INT (0x1 << 2)
-#define DESC_ATBR_ACT_TRAN (0x2 << 4)
-#define DESC_ATBR_LEN_SHIFT 16
-
-#endif